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Staging: Add initial release of brcm80211 - Broadcom 802.11n wireless LAN driver.

Browse Source 
Signed-off-by: Henry Ptasinski <henryp@broadcom.com>
Cc: Brett Rudley <brudley@broadcom.com>
Cc: Nohee Ko <noheek@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Henry Ptasinski 2010-09-08 21:04:42 -07:00 committed by Greg Kroah-Hartman
parent baa5251e8c
commit a9533e7ea3
129 changed files with 115478 additions and 0 deletions
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8
MAINTAINERS
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@ -1392,6 +1392,14 @@ L: netdev@vger.kernel.org
S: Supported
F: drivers/net/tg3.*
BROADCOM BRCM80211 IEEE802.11n WIRELESS DRIVER
M: Brett Rudley <brudley@broadcom.com>
M: Henry Ptasinski <henryp@broadcom.com>
M: Nohee Ko <noheek@broadcom.com>
L: linux-wireless@vger.kernel.org
S: Supported
F: drivers/staging/brcm80211/
BROCADE BFA FC SCSI DRIVER
M: Jing Huang <huangj@brocade.com>
L: linux-scsi@vger.kernel.org

2
drivers/staging/Kconfig
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@ -61,6 +61,8 @@ source "drivers/staging/echo/Kconfig"
source "drivers/staging/otus/Kconfig"
source "drivers/staging/brcm80211/Kconfig"
source "drivers/staging/rt2860/Kconfig"
source "drivers/staging/rt2870/Kconfig"

1
drivers/staging/Makefile
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@ -14,6 +14,7 @@ obj-$(CONFIG_W35UND) += winbond/
obj-$(CONFIG_PRISM2_USB) += wlan-ng/
obj-$(CONFIG_ECHO) += echo/
obj-$(CONFIG_OTUS) += otus/
obj-$(CONFIG_BRCM80211)) += brcm80211/
obj-$(CONFIG_RT2860) += rt2860/
obj-$(CONFIG_RT2870) += rt2870/
obj-$(CONFIG_COMEDI) += comedi/

14
drivers/staging/brcm80211/Kconfig Normal file
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@ -0,0 +1,14 @@
menuconfig BRCM80211
tristate "Broadcom 802.11 WLAN driver for bcm43xx chips"
depends on PCI && WLAN
select WIRELESS_EXT
select WEXT_PRIV
default N
help
If built as a module, it will be called brcm80211.ko.
config BRCM80211_PCI
bool "Broadcom 802.11 WLAN NIC driver"
depends on BRCM80211
default y

65
drivers/staging/brcm80211/Makefile Normal file
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@ -0,0 +1,65 @@
#
# Makefile fragment for Broadcom 802.11n Networking Device Driver
#
# Copyright (c) 2010 Broadcom Corporation
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
EXTRA_CFLAGS := -DBCMDBG -DWLC_HIGH -DSTA -DWME -DWL11N -DDBAND -DBCMDMA32 -DBCMNVRAMR -Idrivers/staging/brcm80211/sys -Idrivers/staging/brcm80211/phy -Idrivers/staging/brcm80211/util -Idrivers/staging/brcm80211/include -Wall -Wstrict-prototypes -Werror -Wmissing-prototypes
PCI_CFLAGS := -DWLC_LOW
BRCM80211_OFILES := \
util/siutils.o \
util/aiutils.o \
util/bcmotp.o \
util/bcmsrom.o \
util/bcmutils.o \
util/bcmwifi.o \
util/bcmwpa.o \
util/hndpmu.o \
util/linux_osl.o \
sys/wlc_alloc.o \
sys/wlc_antsel.o \
sys/wlc_channel.o \
sys/wlc_event.o \
sys/wlc_mac80211.o \
sys/wlc_rate.o \
sys/wlc_stf.o \
sys/wl_mac80211.o \
sys/wlc_ampdu.o
PCIFILES := \
phy/wlc_phy_cmn.o \
phy/wlc_phy_lcn.o \
phy/wlc_phy_n.o \
phy/wlc_phytbl_lcn.o \
phy/wlc_phytbl_n.o \
sys/wlc_bmac.o \
sys/wlc_phy_shim.o \
sys/wl_ucode_loader.o \
util/hnddma.o \
util/nicpci.o \
util/nvram/nvram_ro.o \
util/qmath.o
MODULEPFX := brcm80211
obj-m += $(MODULEPFX).o
# PCI driver
ifeq ($(CONFIG_BRCM80211_PCI),y)
EXTRA_CFLAGS += $(PCI_CFLAGS)
$(MODULEPFX)-objs = $(BRCM80211_OFILES) $(PCIFILES)
endif

0
drivers/staging/brcm80211/Module.symvers Normal file
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94
drivers/staging/brcm80211/README Normal file
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@ -0,0 +1,94 @@
Broadcom Mac80211 driver
This is a driver in progress. It has features still to be implemented well as
bugs in current code.
What's here and not here
=======================
- Completely open source host driver, no binary object files
- Features Broadcom's OneDriver architecture (single source base for
supported chips and architectures)
- On-chip firmware loaded using standard request_firmware()
- Support for BCM43224, BCM43225, BCM4313 (PCIe NIC)
- Framework for supporting new chips, including mac80211-aware embedded chips
- Does not support older PCI/PCIe chips with SSB backplane
- Driver includes BMAC interface for transparent dongle support
- Uses minstrel_ht rate algorithm
- HW based encryption not enabled yet
What's done
==========
- Integration with mac80211 stack
- A-MPDU single & dual stream rates
- BCM43224: Dualband, Dual stream, 20MHz channels
Throughput (in chamber): ~85-90 Mbits/sec (in both 2.4 & 5 GHz bands)
- BCM43225: 2.4 GHz, Dual Stream, 20MHz channels
Throughput (in chamber): ~85-90 Mbits/sec
- BCM4313: 2.4 GHz, Single Stream
Throughput (in chamber): ~40 Mbits/sec
Things To Be Done
=================
See the TODO file
Firmware installation
======================
Firmware is available from the Linux firmware repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
http://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
https://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
For all chips, copy brcm/bcm43xx-0-610-809-0.fw and
brcm/bcm43xx_hdr-0-610-809-0.fw to /lib/firmware/brcm (or wherever firmware is
normally installed on the system). In the /lib/firmware/brcm directory, then
create the following symlinks:
ln -s bcm43xx-0-610-809-0.fw bcm43xx-0.fw
ln -s bcm43xx_hdr-0-610-809-0.fw bcm43xx_hdr-0.fw
Currently supported chips
==============
PCI
Name Device ID
BCM4313 0x4727
BCM43224 0x4353
BCM43225 0x4357
Bugs/Problems
==============
- Driver can get confused while scanning during high throughput, can cause
burping, hanging, and possible crashing.
- Occasional hangs & burps with BCM43224 on 2.4 GHz with dual stream rates.
- Occasional crashes with BCM43224 on multicore machines.
Note on Regulatory Implementation
================================
This generation of chips contain additional regulatory support independent of
the driver. The devices use a single worldwide regulatory domain, with channels
12-14 (2.4 GHz band) and channels 52-64 and 100-140 (5 GHz band) restricted to
passive operation. Transmission on those channels is suppressed until
appropriate other traffic is observed on those channels.
Within the driver, we use the ficticious country code "X2" to represent this
worldwide regulatory domain. There is currently no interface to configure a
different domain.
The driver reads the SROM country code from the chip and hands it up to
mac80211 as the regulatory hint, however this information is otherwise unused
with the driver.
Contact Info:
=============
Brett Rudley brudley@broadcom.com
Henry Ptasinski henryp@broadcom.com
Nohee Ko noheek@broadcom.com

42
drivers/staging/brcm80211/TODO Normal file
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@ -0,0 +1,42 @@
To Do List for Broadcom Mac80211 driver
Features to be added
=====================
- 40 MHz channels
- Power Save
- AP
- IBSS
- HW-based encryption
- LED support
- RFKILL
- Debugfs and debugability
Code cleanup
============
- Use proper kernel coding standards
- Remove overlap with system header files. (ie much of include/proto/*.h should
be removed)
- Purge unused variables/data structs/functions BUT keep code related to
features that are being added (ie AP mode, 40 Mhz channels, IBSS etc).
- Replace proprietary utility functions with public kernel versions.
Bugs
====
- Various occasional asserts/hangs
- Scanning during data transfer sometimes causes major slowdowns. Sometimes
revcovers when scan is done, other times not.
- Driver does not handle missing firmware gracefully.
- Mac80211 API not completely implemented (ie ops_bss_info_changed,
ops_get_stats, etc)
Other
=====
- wlc_mac80211.[ch], wl_mac80211.[ch] and linux_osl.c all need to be refactored
and combined.
- Replace driver's proprietary ssb interface with generic kernel ssb module
(only used when compiling for SDIO).
- PCI and SDIO support are currently #ifdef'ed exclusive of each other, which
leads to a separate wl.ko for each. This should be changed to runtime
handling of different interfaces so that a single binary driver can be built.
- Add support for new chips (obviously an ongoing item).

374
drivers/staging/brcm80211/include/aidmp.h Normal file
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@ -0,0 +1,374 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _AIDMP_H
#define _AIDMP_H
/* Manufacturer Ids */
#define MFGID_ARM 0x43b
#define MFGID_BRCM 0x4bf
#define MFGID_MIPS 0x4a7
/* Component Classes */
#define CC_SIM 0
#define CC_EROM 1
#define CC_CORESIGHT 9
#define CC_VERIF 0xb
#define CC_OPTIMO 0xd
#define CC_GEN 0xe
#define CC_PRIMECELL 0xf
/* Enumeration ROM registers */
#define ER_EROMENTRY 0x000
#define ER_REMAPCONTROL 0xe00
#define ER_REMAPSELECT 0xe04
#define ER_MASTERSELECT 0xe10
#define ER_ITCR 0xf00
#define ER_ITIP 0xf04
/* Erom entries */
#define ER_TAG 0xe
#define ER_TAG1 0x6
#define ER_VALID 1
#define ER_CI 0
#define ER_MP 2
#define ER_ADD 4
#define ER_END 0xe
#define ER_BAD 0xffffffff
/* EROM CompIdentA */
#define CIA_MFG_MASK 0xfff00000
#define CIA_MFG_SHIFT 20
#define CIA_CID_MASK 0x000fff00
#define CIA_CID_SHIFT 8
#define CIA_CCL_MASK 0x000000f0
#define CIA_CCL_SHIFT 4
/* EROM CompIdentB */
#define CIB_REV_MASK 0xff000000
#define CIB_REV_SHIFT 24
#define CIB_NSW_MASK 0x00f80000
#define CIB_NSW_SHIFT 19
#define CIB_NMW_MASK 0x0007c000
#define CIB_NMW_SHIFT 14
#define CIB_NSP_MASK 0x00003e00
#define CIB_NSP_SHIFT 9
#define CIB_NMP_MASK 0x000001f0
#define CIB_NMP_SHIFT 4
/* EROM MasterPortDesc */
#define MPD_MUI_MASK 0x0000ff00
#define MPD_MUI_SHIFT 8
#define MPD_MP_MASK 0x000000f0
#define MPD_MP_SHIFT 4
/* EROM AddrDesc */
#define AD_ADDR_MASK 0xfffff000
#define AD_SP_MASK 0x00000f00
#define AD_SP_SHIFT 8
#define AD_ST_MASK 0x000000c0
#define AD_ST_SHIFT 6
#define AD_ST_SLAVE 0x00000000
#define AD_ST_BRIDGE 0x00000040
#define AD_ST_SWRAP 0x00000080
#define AD_ST_MWRAP 0x000000c0
#define AD_SZ_MASK 0x00000030
#define AD_SZ_SHIFT 4
#define AD_SZ_4K 0x00000000
#define AD_SZ_8K 0x00000010
#define AD_SZ_16K 0x00000020
#define AD_SZ_SZD 0x00000030
#define AD_AG32 0x00000008
#define AD_ADDR_ALIGN 0x00000fff
#define AD_SZ_BASE 0x00001000 /* 4KB */
/* EROM SizeDesc */
#define SD_SZ_MASK 0xfffff000
#define SD_SG32 0x00000008
#define SD_SZ_ALIGN 0x00000fff
#ifndef _LANGUAGE_ASSEMBLY
typedef volatile struct _aidmp {
uint32 oobselina30; /* 0x000 */
uint32 oobselina74; /* 0x004 */
uint32 PAD[6];
uint32 oobselinb30; /* 0x020 */
uint32 oobselinb74; /* 0x024 */
uint32 PAD[6];
uint32 oobselinc30; /* 0x040 */
uint32 oobselinc74; /* 0x044 */
uint32 PAD[6];
uint32 oobselind30; /* 0x060 */
uint32 oobselind74; /* 0x064 */
uint32 PAD[38];
uint32 oobselouta30; /* 0x100 */
uint32 oobselouta74; /* 0x104 */
uint32 PAD[6];
uint32 oobseloutb30; /* 0x120 */
uint32 oobseloutb74; /* 0x124 */
uint32 PAD[6];
uint32 oobseloutc30; /* 0x140 */
uint32 oobseloutc74; /* 0x144 */
uint32 PAD[6];
uint32 oobseloutd30; /* 0x160 */
uint32 oobseloutd74; /* 0x164 */
uint32 PAD[38];
uint32 oobsynca; /* 0x200 */
uint32 oobseloutaen; /* 0x204 */
uint32 PAD[6];
uint32 oobsyncb; /* 0x220 */
uint32 oobseloutben; /* 0x224 */
uint32 PAD[6];
uint32 oobsyncc; /* 0x240 */
uint32 oobseloutcen; /* 0x244 */
uint32 PAD[6];
uint32 oobsyncd; /* 0x260 */
uint32 oobseloutden; /* 0x264 */
uint32 PAD[38];
uint32 oobaextwidth; /* 0x300 */
uint32 oobainwidth; /* 0x304 */
uint32 oobaoutwidth; /* 0x308 */
uint32 PAD[5];
uint32 oobbextwidth; /* 0x320 */
uint32 oobbinwidth; /* 0x324 */
uint32 oobboutwidth; /* 0x328 */
uint32 PAD[5];
uint32 oobcextwidth; /* 0x340 */
uint32 oobcinwidth; /* 0x344 */
uint32 oobcoutwidth; /* 0x348 */
uint32 PAD[5];
uint32 oobdextwidth; /* 0x360 */
uint32 oobdinwidth; /* 0x364 */
uint32 oobdoutwidth; /* 0x368 */
uint32 PAD[37];
uint32 ioctrlset; /* 0x400 */
uint32 ioctrlclear; /* 0x404 */
uint32 ioctrl; /* 0x408 */
uint32 PAD[61];
uint32 iostatus; /* 0x500 */
uint32 PAD[127];
uint32 ioctrlwidth; /* 0x700 */
uint32 iostatuswidth; /* 0x704 */
uint32 PAD[62];
uint32 resetctrl; /* 0x800 */
uint32 resetstatus; /* 0x804 */
uint32 resetreadid; /* 0x808 */
uint32 resetwriteid; /* 0x80c */
uint32 PAD[60];
uint32 errlogctrl; /* 0x900 */
uint32 errlogdone; /* 0x904 */
uint32 errlogstatus; /* 0x908 */
uint32 errlogaddrlo; /* 0x90c */
uint32 errlogaddrhi; /* 0x910 */
uint32 errlogid; /* 0x914 */
uint32 errloguser; /* 0x918 */
uint32 errlogflags; /* 0x91c */
uint32 PAD[56];
uint32 intstatus; /* 0xa00 */
uint32 PAD[127];
uint32 config; /* 0xe00 */
uint32 PAD[63];
uint32 itcr; /* 0xf00 */
uint32 PAD[3];
uint32 itipooba; /* 0xf10 */
uint32 itipoobb; /* 0xf14 */
uint32 itipoobc; /* 0xf18 */
uint32 itipoobd; /* 0xf1c */
uint32 PAD[4];
uint32 itipoobaout; /* 0xf30 */
uint32 itipoobbout; /* 0xf34 */
uint32 itipoobcout; /* 0xf38 */
uint32 itipoobdout; /* 0xf3c */
uint32 PAD[4];
uint32 itopooba; /* 0xf50 */
uint32 itopoobb; /* 0xf54 */
uint32 itopoobc; /* 0xf58 */
uint32 itopoobd; /* 0xf5c */
uint32 PAD[4];
uint32 itopoobain; /* 0xf70 */
uint32 itopoobbin; /* 0xf74 */
uint32 itopoobcin; /* 0xf78 */
uint32 itopoobdin; /* 0xf7c */
uint32 PAD[4];
uint32 itopreset; /* 0xf90 */
uint32 PAD[15];
uint32 peripherialid4; /* 0xfd0 */
uint32 peripherialid5; /* 0xfd4 */
uint32 peripherialid6; /* 0xfd8 */
uint32 peripherialid7; /* 0xfdc */
uint32 peripherialid0; /* 0xfe0 */
uint32 peripherialid1; /* 0xfe4 */
uint32 peripherialid2; /* 0xfe8 */
uint32 peripherialid3; /* 0xfec */
uint32 componentid0; /* 0xff0 */
uint32 componentid1; /* 0xff4 */
uint32 componentid2; /* 0xff8 */
uint32 componentid3; /* 0xffc */
} aidmp_t;
#endif /* _LANGUAGE_ASSEMBLY */
/* Out-of-band Router registers */
#define OOB_BUSCONFIG 0x020
#define OOB_STATUSA 0x100
#define OOB_STATUSB 0x104
#define OOB_STATUSC 0x108
#define OOB_STATUSD 0x10c
#define OOB_ENABLEA0 0x200
#define OOB_ENABLEA1 0x204
#define OOB_ENABLEA2 0x208
#define OOB_ENABLEA3 0x20c
#define OOB_ENABLEB0 0x280
#define OOB_ENABLEB1 0x284
#define OOB_ENABLEB2 0x288
#define OOB_ENABLEB3 0x28c
#define OOB_ENABLEC0 0x300
#define OOB_ENABLEC1 0x304
#define OOB_ENABLEC2 0x308
#define OOB_ENABLEC3 0x30c
#define OOB_ENABLED0 0x380
#define OOB_ENABLED1 0x384
#define OOB_ENABLED2 0x388
#define OOB_ENABLED3 0x38c
#define OOB_ITCR 0xf00
#define OOB_ITIPOOBA 0xf10
#define OOB_ITIPOOBB 0xf14
#define OOB_ITIPOOBC 0xf18
#define OOB_ITIPOOBD 0xf1c
#define OOB_ITOPOOBA 0xf30
#define OOB_ITOPOOBB 0xf34
#define OOB_ITOPOOBC 0xf38
#define OOB_ITOPOOBD 0xf3c
/* DMP wrapper registers */
#define AI_OOBSELINA30 0x000
#define AI_OOBSELINA74 0x004
#define AI_OOBSELINB30 0x020
#define AI_OOBSELINB74 0x024
#define AI_OOBSELINC30 0x040
#define AI_OOBSELINC74 0x044
#define AI_OOBSELIND30 0x060
#define AI_OOBSELIND74 0x064
#define AI_OOBSELOUTA30 0x100
#define AI_OOBSELOUTA74 0x104
#define AI_OOBSELOUTB30 0x120
#define AI_OOBSELOUTB74 0x124
#define AI_OOBSELOUTC30 0x140
#define AI_OOBSELOUTC74 0x144
#define AI_OOBSELOUTD30 0x160
#define AI_OOBSELOUTD74 0x164
#define AI_OOBSYNCA 0x200
#define AI_OOBSELOUTAEN 0x204
#define AI_OOBSYNCB 0x220
#define AI_OOBSELOUTBEN 0x224
#define AI_OOBSYNCC 0x240
#define AI_OOBSELOUTCEN 0x244
#define AI_OOBSYNCD 0x260
#define AI_OOBSELOUTDEN 0x264
#define AI_OOBAEXTWIDTH 0x300
#define AI_OOBAINWIDTH 0x304
#define AI_OOBAOUTWIDTH 0x308
#define AI_OOBBEXTWIDTH 0x320
#define AI_OOBBINWIDTH 0x324
#define AI_OOBBOUTWIDTH 0x328
#define AI_OOBCEXTWIDTH 0x340
#define AI_OOBCINWIDTH 0x344
#define AI_OOBCOUTWIDTH 0x348
#define AI_OOBDEXTWIDTH 0x360
#define AI_OOBDINWIDTH 0x364
#define AI_OOBDOUTWIDTH 0x368
#if defined(IL_BIGENDIAN) && defined(BCMHND74K)
/* Selective swapped defines for those registers we need in
* big-endian code.
*/
#define AI_IOCTRLSET 0x404
#define AI_IOCTRLCLEAR 0x400
#define AI_IOCTRL 0x40c
#define AI_IOSTATUS 0x504
#define AI_RESETCTRL 0x804
#define AI_RESETSTATUS 0x800
#else /* !IL_BIGENDIAN || !BCMHND74K */
#define AI_IOCTRLSET 0x400
#define AI_IOCTRLCLEAR 0x404
#define AI_IOCTRL 0x408
#define AI_IOSTATUS 0x500
#define AI_RESETCTRL 0x800
#define AI_RESETSTATUS 0x804
#endif /* IL_BIGENDIAN && BCMHND74K */
#define AI_IOCTRLWIDTH 0x700
#define AI_IOSTATUSWIDTH 0x704
#define AI_RESETREADID 0x808
#define AI_RESETWRITEID 0x80c
#define AI_ERRLOGCTRL 0xa00
#define AI_ERRLOGDONE 0xa04
#define AI_ERRLOGSTATUS 0xa08
#define AI_ERRLOGADDRLO 0xa0c
#define AI_ERRLOGADDRHI 0xa10
#define AI_ERRLOGID 0xa14
#define AI_ERRLOGUSER 0xa18
#define AI_ERRLOGFLAGS 0xa1c
#define AI_INTSTATUS 0xa00
#define AI_CONFIG 0xe00
#define AI_ITCR 0xf00
#define AI_ITIPOOBA 0xf10
#define AI_ITIPOOBB 0xf14
#define AI_ITIPOOBC 0xf18
#define AI_ITIPOOBD 0xf1c
#define AI_ITIPOOBAOUT 0xf30
#define AI_ITIPOOBBOUT 0xf34
#define AI_ITIPOOBCOUT 0xf38
#define AI_ITIPOOBDOUT 0xf3c
#define AI_ITOPOOBA 0xf50
#define AI_ITOPOOBB 0xf54
#define AI_ITOPOOBC 0xf58
#define AI_ITOPOOBD 0xf5c
#define AI_ITOPOOBAIN 0xf70
#define AI_ITOPOOBBIN 0xf74
#define AI_ITOPOOBCIN 0xf78
#define AI_ITOPOOBDIN 0xf7c
#define AI_ITOPRESET 0xf90
#define AI_PERIPHERIALID4 0xfd0
#define AI_PERIPHERIALID5 0xfd4
#define AI_PERIPHERIALID6 0xfd8
#define AI_PERIPHERIALID7 0xfdc
#define AI_PERIPHERIALID0 0xfe0
#define AI_PERIPHERIALID1 0xfe4
#define AI_PERIPHERIALID2 0xfe8
#define AI_PERIPHERIALID3 0xfec
#define AI_COMPONENTID0 0xff0
#define AI_COMPONENTID1 0xff4
#define AI_COMPONENTID2 0xff8
#define AI_COMPONENTID3 0xffc
/* resetctrl */
#define AIRC_RESET 1
/* config */
#define AICFG_OOB 0x00000020
#define AICFG_IOS 0x00000010
#define AICFG_IOC 0x00000008
#define AICFG_TO 0x00000004
#define AICFG_ERRL 0x00000002
#define AICFG_RST 0x00000001
#endif /* _AIDMP_H */

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drivers/staging/brcm80211/include/bcm_rpc.h Normal file
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BCM_RPC_H_
#define _BCM_RPC_H_
#include <typedefs.h>
#include <rpc_osl.h>
typedef struct rpc_info rpc_info_t;
typedef struct rpc_buf rpc_buf_t;
struct rpc_transport_info;
typedef void (*rpc_dispatch_cb_t) (void *ctx, struct rpc_buf * buf);
typedef void (*rpc_resync_cb_t) (void *ctx);
typedef void (*rpc_down_cb_t) (void *ctx);
typedef void (*rpc_txdone_cb_t) (void *ctx, struct rpc_buf * buf);
extern struct rpc_info *bcm_rpc_attach(void *pdev, osl_t * osh,
struct rpc_transport_info *rpc_th);
extern void bcm_rpc_detach(struct rpc_info *rpc);
extern void bcm_rpc_down(struct rpc_info *rpc);
extern void bcm_rpc_watchdog(struct rpc_info *rpc);
extern struct rpc_buf *bcm_rpc_buf_alloc(struct rpc_info *rpc, int len);
extern void bcm_rpc_buf_free(struct rpc_info *rpc, struct rpc_buf *b);
/* get rpc transport handle */
extern struct rpc_transport_info *bcm_rpc_tp_get(struct rpc_info *rpc);
/* callback for: data_rx, down, resync */
extern void bcm_rpc_rxcb_init(struct rpc_info *rpc, void *ctx,
rpc_dispatch_cb_t cb, void *dnctx,
rpc_down_cb_t dncb, rpc_resync_cb_t resync_cb,
rpc_txdone_cb_t);
extern void bcm_rpc_rxcb_deinit(struct rpc_info *rpci);
/* HOST or CLIENT rpc call, requiring no return value */
extern int bcm_rpc_call(struct rpc_info *rpc, struct rpc_buf *b);
/* HOST rpc call, demanding return.
* The thread may be suspended and control returns back to OS
* The thread will resume(waked up) on either the return signal received or timeout
* The implementation details depend on OS
*/
extern struct rpc_buf *bcm_rpc_call_with_return(struct rpc_info *rpc,
struct rpc_buf *b);
/* CLIENT rpc call to respond to bcm_rpc_call_with_return, requiring no return value */
extern int bcm_rpc_call_return(struct rpc_info *rpc, struct rpc_buf *retb);
extern uint bcm_rpc_buf_header_len(struct rpc_info *rpci);
#define RPC_PKTLOG_SIZE 50 /* Depth of the history */
#define RPC_PKTLOG_RD_LEN 3
#define RPC_PKTLOG_DUMP_SIZE 150 /* dump size should be more than the product of above two */
extern int bcm_rpc_pktlog_get(struct rpc_info *rpci, uint32 * buf,
uint buf_size, bool send);
extern int bcm_rpc_dump(rpc_info_t * rpci, struct bcmstrbuf *b);
/* HIGH/BMAC: bit 15-8: RPC module, bit 7-0: TP module */
#define RPC_ERROR_VAL 0x0001
#define RPC_TRACE_VAL 0x0002
#define RPC_PKTTRACE_VAL 0x0004
#define RPC_PKTLOG_VAL 0x0008
extern void bcm_rpc_msglevel_set(struct rpc_info *rpci, uint16 msglevel,
bool high_low);
#endif /* _BCM_RPC_H_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcm_rpc_tp_h_
#define _bcm_rpc_tp_h_
#include <bcm_rpc.h>
#define DBUS_RX_BUFFER_SIZE_RPC (2100) /* rxbufsize for dbus_attach, linux only for now */
#define BCM_RPC_TP_ENCAP_LEN 4 /* TP header is 4 bytes */
#define BCM_RPC_TP_HOST_AGG_MASK 0xffff0000
#define BCM_RPC_TP_HOST_AGG_SHIFT 16
#define BCM_RPC_TP_HOST_AGG_AMPDU 0x00010000 /* HOST->DNGL ampdu aggregation */
#define BCM_RPC_TP_HOST_AGG_TEST 0x00100000 /* HOST->DNGL test aggregation */
#define BCM_RPC_TP_DNGL_AGG_MASK 0x0000ffff
#define BCM_RPC_TP_DNGL_AGG_DPC 0x00000001 /* DNGL->HOST data aggregation */
#define BCM_RPC_TP_DNGL_AGG_FLOWCTL 0x00000002 /* DNGL->HOST tx flowcontrol agg */
#define BCM_RPC_TP_DNGL_AGG_TEST 0x00000010 /* DNGL->HOST test agg */
#define BCM_RPC_TP_DNGL_AGG_MAX_SFRAME 3 /* max agg subframes, must be <= USB_NTXD */
#define BCM_RPC_TP_DNGL_AGG_MAX_BYTE 4000 /* max agg bytes */
#define BCM_RPC_TP_HOST_AGG_MAX_SFRAME 3 /* max agg subframes, AMPDU only, 3 is enough */
#define BCM_RPC_TP_HOST_AGG_MAX_BYTE 3400 /* max agg bytes; to fit 2+ tcp/udp pkts. Each one:
* 802.3pkt + 802.11 hdr + rpc hdr + tp hdr < 1700B
* Need to be in sync with dongle usb rx dma
* rxbufsize(USBBULK_RXBUF_GIANT in usbdev_sb.c)
*/
/* TP-DBUS pkts flowcontrol */
#define BCM_RPC_TP_DBUS_NTXQ 50 /* queue size for TX on bulk OUT, aggregation possible */
#define BCM_RPC_TP_DBUS_NRXQ 50 /* queue size for RX on bulk IN, aggregation possible */
#define BCM_RPC_TP_DBUS_NRXQ_CTRL 1 /* queue size for RX on ctl EP0 */
#define BCM_RPC_TP_DBUS_NRXQ_PKT (BCM_RPC_TP_DBUS_NRXQ * BCM_RPC_TP_DNGL_AGG_MAX_SFRAME)
#define BCM_RPC_TP_DBUS_NTXQ_PKT (BCM_RPC_TP_DBUS_NTXQ * BCM_RPC_TP_HOST_AGG_MAX_SFRAME)
typedef struct rpc_transport_info rpc_tp_info_t;
typedef void (*rpc_tx_complete_fn_t) (void *, rpc_buf_t *, int status);
typedef void (*rpc_rx_fn_t) (void *, rpc_buf_t *);
#ifdef WLC_LOW
typedef void (*rpc_txflowctl_cb_t) (void *ctx, bool on);
#endif
extern rpc_tp_info_t *bcm_rpc_tp_attach(osl_t * osh, void *bus);
extern void bcm_rpc_tp_detach(rpc_tp_info_t * rpcb);
extern void bcm_rpc_tp_down(rpc_tp_info_t * rpcb);
extern void bcm_rpc_tp_watchdog(rpc_tp_info_t * rpcb);
extern int bcm_rpc_tp_buf_send(rpc_tp_info_t * rpcb, rpc_buf_t * buf);
/* callback for tx_complete, rx_pkt */
extern void bcm_rpc_tp_register_cb(rpc_tp_info_t * rpcb,
rpc_tx_complete_fn_t txcmplt,
void *tx_context, rpc_rx_fn_t rxpkt,
void *rx_context, rpc_osl_t * rpc_osh);
extern void bcm_rpc_tp_deregister_cb(rpc_tp_info_t * rpcb);
/* Buffer manipulation */
extern uint bcm_rpc_buf_tp_header_len(rpc_tp_info_t * rpcb);
extern rpc_buf_t *bcm_rpc_tp_buf_alloc(rpc_tp_info_t * rpcb, int len);
extern void bcm_rpc_tp_buf_free(rpc_tp_info_t * rpcb, rpc_buf_t * buf);
extern int bcm_rpc_buf_len_get(rpc_tp_info_t * rpcb, rpc_buf_t * b);
extern int bcm_rpc_buf_len_set(rpc_tp_info_t * rpcb, rpc_buf_t * b, uint len);
extern rpc_buf_t *bcm_rpc_buf_next_get(rpc_tp_info_t * rpcb, rpc_buf_t * b);
extern void bcm_rpc_buf_next_set(rpc_tp_info_t * rpcb, rpc_buf_t * b,
rpc_buf_t * nextb);
extern unsigned char *bcm_rpc_buf_data(rpc_tp_info_t * rpcb, rpc_buf_t * b);
extern unsigned char *bcm_rpc_buf_push(rpc_tp_info_t * rpcb, rpc_buf_t * b,
uint delta);
extern unsigned char *bcm_rpc_buf_pull(rpc_tp_info_t * rpcb, rpc_buf_t * b,
uint delta);
extern void bcm_rpc_tp_buf_release(rpc_tp_info_t * rpcb, rpc_buf_t * buf);
extern void bcm_rpc_tp_buf_cnt_adjust(rpc_tp_info_t * rpcb, int adjust);
/* RPC call_with_return */
extern int bcm_rpc_tp_recv_rtn(rpc_tp_info_t * rpcb);
extern int bcm_rpc_tp_get_device_speed(rpc_tp_info_t * rpc_th);
#ifdef BCMDBG
extern int bcm_rpc_tp_dump(rpc_tp_info_t * rpcb, struct bcmstrbuf *b);
#endif
#ifdef WLC_LOW
/* intercept USB pkt to parse RPC header: USB driver rx-> wl_send -> this -> wl driver */
extern void bcm_rpc_tp_rx_from_dnglbus(rpc_tp_info_t * rpc_th, struct lbuf *lb);
/* RPC callreturn pkt, go to USB driver tx */
extern int bcm_rpc_tp_send_callreturn(rpc_tp_info_t * rpc_th, rpc_buf_t * b);
extern void bcm_rpc_tp_dump(rpc_tp_info_t * rpcb);
extern void bcm_rpc_tp_txflowctl(rpc_tp_info_t * rpcb, bool state, int prio);
extern void bcm_rpc_tp_txflowctlcb_init(rpc_tp_info_t * rpc_th, void *ctx,
rpc_txflowctl_cb_t cb);
extern void bcm_rpc_tp_txflowctlcb_deinit(rpc_tp_info_t * rpc_th);
extern void bcm_rpc_tp_txq_wm_set(rpc_tp_info_t * rpc_th, uint8 hiwm,
uint8 lowm);
extern void bcm_rpc_tp_txq_wm_get(rpc_tp_info_t * rpc_th, uint8 * hiwm,
uint8 * lowm);
#endif /* WLC_LOW */
extern void bcm_rpc_tp_agg_set(rpc_tp_info_t * rpcb, uint32 reason, bool set);
extern void bcm_rpc_tp_agg_limit_set(rpc_tp_info_t * rpc_th, uint8 sf,
uint16 bytes);
extern void bcm_rpc_tp_agg_limit_get(rpc_tp_info_t * rpc_th, uint8 * sf,
uint16 * bytes);
#define BCM_RPC_TP_MSG_LEVEL_MASK 0x00ff
/* dongle msg level */
#define RPC_TP_MSG_DNGL_ERR_VAL 0x0001 /* DNGL TP error msg */
#define RPC_TP_MSG_DNGL_DBG_VAL 0x0002 /* DNGL TP dbg msg */
#define RPC_TP_MSG_DNGL_AGG_VAL 0x0004 /* DNGL TP agg msg */
#define RPC_TP_MSG_DNGL_DEA_VAL 0x0008 /* DNGL TP deag msg */
/* host msg level */
#define RPC_TP_MSG_HOST_ERR_VAL 0x0001 /* DNGL TP error msg */
#define RPC_TP_MSG_HOST_DBG_VAL 0x0002 /* DNGL TP dbg msg */
#define RPC_TP_MSG_HOST_AGG_VAL 0x0004 /* DNGL TP agg msg */
#define RPC_TP_MSG_HOST_DEA_VAL 0x0008 /* DNGL TP deag msg */
extern void bcm_rpc_tp_msglevel_set(rpc_tp_info_t * rpc_th, uint8 msglevel,
bool high_low);
#endif /* _bcm_rpc_tp_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BCM_XDR_H
#define _BCM_XDR_H
/*
* bcm_xdr_buf_t
* Structure used for bookkeeping of a buffer being packed or unpacked.
* Keeps a current read/write pointer and size as well as
* the original buffer pointer and size.
*
*/
typedef struct {
uint8 *buf; /* pointer to current position in origbuf */
uint size; /* current (residual) size in bytes */
uint8 *origbuf; /* unmodified pointer to orignal buffer */
uint origsize; /* unmodified orignal buffer size in bytes */
} bcm_xdr_buf_t;
void bcm_xdr_buf_init(bcm_xdr_buf_t * b, void *buf, size_t len);
int bcm_xdr_pack_uint32(bcm_xdr_buf_t * b, uint32 val);
int bcm_xdr_unpack_uint32(bcm_xdr_buf_t * b, uint32 * pval);
int bcm_xdr_pack_int32(bcm_xdr_buf_t * b, int32 val);
int bcm_xdr_unpack_int32(bcm_xdr_buf_t * b, int32 * pval);
int bcm_xdr_pack_int8(bcm_xdr_buf_t * b, int8 val);
int bcm_xdr_unpack_int8(bcm_xdr_buf_t * b, int8 * pval);
int bcm_xdr_pack_opaque(bcm_xdr_buf_t * b, uint len, void *data);
int bcm_xdr_unpack_opaque(bcm_xdr_buf_t * b, uint len, void **pdata);
int bcm_xdr_unpack_opaque_cpy(bcm_xdr_buf_t * b, uint len, void *data);
int bcm_xdr_pack_opaque_varlen(bcm_xdr_buf_t * b, uint len, void *data);
int bcm_xdr_unpack_opaque_varlen(bcm_xdr_buf_t * b, uint * plen, void **pdata);
int bcm_xdr_pack_string(bcm_xdr_buf_t * b, char *str);
int bcm_xdr_unpack_string(bcm_xdr_buf_t * b, uint * plen, char **pstr);
int bcm_xdr_pack_uint8_vec(bcm_xdr_buf_t *, uint8 * vec, uint32 elems);
int bcm_xdr_unpack_uint8_vec(bcm_xdr_buf_t *, uint8 * vec, uint32 elems);
int bcm_xdr_pack_uint16_vec(bcm_xdr_buf_t * b, uint len, void *vec);
int bcm_xdr_unpack_uint16_vec(bcm_xdr_buf_t * b, uint len, void *vec);
int bcm_xdr_pack_uint32_vec(bcm_xdr_buf_t * b, uint len, void *vec);
int bcm_xdr_unpack_uint32_vec(bcm_xdr_buf_t * b, uint len, void *vec);
int bcm_xdr_pack_opaque_raw(bcm_xdr_buf_t * b, uint len, void *data);
int bcm_xdr_pack_opaque_pad(bcm_xdr_buf_t * b);
#endif /* _BCM_XDR_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmdefs_h_
#define _bcmdefs_h_
/*
* One doesn't need to include this file explicitly, gets included automatically if
* typedefs.h is included.
*/
/* Use BCM_REFERENCE to suppress warnings about intentionally-unused function
* arguments or local variables.
*/
#define BCM_REFERENCE(data) ((void)data)
/* Reclaiming text and data :
* The following macros specify special linker sections that can be reclaimed
* after a system is considered 'up'.
* BCMATTACHFN is also used for detach functions (it's not worth having a BCMDETACHFN,
* as in most cases, the attach function calls the detach function to clean up on error).
*/
#define bcmreclaimed 0
#define BCMATTACHDATA(_data) _data
#define BCMATTACHFN(_fn) _fn
#define BCMPREATTACHDATA(_data) _data
#define BCMPREATTACHFN(_fn) _fn
#define BCMINITDATA(_data) _data
#define BCMINITFN(_fn) _fn
#define BCMUNINITFN(_fn) _fn
#define BCMNMIATTACHFN(_fn) _fn
#define BCMNMIATTACHDATA(_data) _data
#define BCMOVERLAY0DATA(_sym) _sym
#define BCMOVERLAY0FN(_fn) _fn
#define BCMOVERLAY1DATA(_sym) _sym
#define BCMOVERLAY1FN(_fn) _fn
#define BCMOVERLAYERRFN(_fn) _fn
#define CONST const
#ifdef mips
#define BCMFASTPATH __attribute__ ((__section__(".text.fastpath")))
#else
#define BCMFASTPATH
#endif
/* Put some library data/code into ROM to reduce RAM requirements */
#define BCMROMDATA(_data) _data
#define BCMROMDAT_NAME(_data) _data
#define BCMROMFN(_fn) _fn
#define BCMROMFN_NAME(_fn) _fn
#define STATIC static
#define BCMROMDAT_ARYSIZ(data) ARRAYSIZE(data)
#define BCMROMDAT_SIZEOF(data) sizeof(data)
#define BCMROMDAT_APATCH(data)
#define BCMROMDAT_SPATCH(data)
/* Bus types */
#define SI_BUS 0 /* SOC Interconnect */
#define PCI_BUS 1 /* PCI target */
#define SDIO_BUS 3 /* SDIO target */
#define JTAG_BUS 4 /* JTAG */
#define USB_BUS 5 /* USB (does not support R/W REG) */
#define SPI_BUS 6 /* gSPI target */
#define RPC_BUS 7 /* RPC target */
/* Allows size optimization for single-bus image */
#ifdef BCMBUSTYPE
#define BUSTYPE(bus) (BCMBUSTYPE)
#else
#define BUSTYPE(bus) (bus)
#endif
/* Allows size optimization for single-backplane image */
#ifdef BCMCHIPTYPE
#define CHIPTYPE(bus) (BCMCHIPTYPE)
#else
#define CHIPTYPE(bus) (bus)
#endif
/* Allows size optimization for SPROM support */
#define SPROMBUS (PCI_BUS)
/* Allows size optimization for single-chip image */
#ifdef BCMCHIPID
#define CHIPID(chip) (BCMCHIPID)
#else
#define CHIPID(chip) (chip)
#endif
#ifdef BCMCHIPREV
#define CHIPREV(rev) (BCMCHIPREV)
#else
#define CHIPREV(rev) (rev)
#endif
/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
#ifdef BCMDMA64OSL
typedef struct {
uint32 loaddr;
uint32 hiaddr;
} dma64addr_t;
typedef dma64addr_t dmaaddr_t;
#define PHYSADDRHI(_pa) ((_pa).hiaddr)
#define PHYSADDRHISET(_pa, _val) \
do { \
(_pa).hiaddr = (_val); \
} while (0)
#define PHYSADDRLO(_pa) ((_pa).loaddr)
#define PHYSADDRLOSET(_pa, _val) \
do { \
(_pa).loaddr = (_val); \
} while (0)
#else
typedef unsigned long dmaaddr_t;
#define PHYSADDRHI(_pa) (0)
#define PHYSADDRHISET(_pa, _val)
#define PHYSADDRLO(_pa) ((_pa))
#define PHYSADDRLOSET(_pa, _val) \
do { \
(_pa) = (_val); \
} while (0)
#endif /* BCMDMA64OSL */
/* One physical DMA segment */
typedef struct {
dmaaddr_t addr;
uint32 length;
} hnddma_seg_t;
#define MAX_DMA_SEGS 4
typedef struct {
void *oshdmah; /* Opaque handle for OSL to store its information */
uint origsize; /* Size of the virtual packet */
uint nsegs;
hnddma_seg_t segs[MAX_DMA_SEGS];
} hnddma_seg_map_t;
/* packet headroom necessary to accommodate the largest header in the system, (i.e TXOFF).
* By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
* There is a compile time check in wlc.c which ensure that this value is at least as big
* as TXOFF. This value is used in dma_rxfill (hnddma.c).
*/
#define BCMEXTRAHDROOM 172
/* Headroom required for dongle-to-host communication. Packets allocated
* locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
* leave this much room in front for low-level message headers which may
* be needed to get across the dongle bus to the host. (These messages
* don't go over the network, so room for the full WL header above would
* be a waste.).
*/
#define BCMDONGLEHDRSZ 12
#define BCMDONGLEPADSZ 16
#define BCMDONGLEOVERHEAD (BCMDONGLEHDRSZ + BCMDONGLEPADSZ)
#ifdef BCMDBG
#define BCMDBG_ERR
#ifndef BCMDBG_ASSERT
#define BCMDBG_ASSERT
#endif /* BCMDBG_ASSERT */
#endif /* BCMDBG */
#if defined(BCMDBG_ASSERT)
#define BCMASSERT_SUPPORT
#endif
/* Macros for doing definition and get/set of bitfields
* Usage example, e.g. a three-bit field (bits 4-6):
* #define <NAME>_M BITFIELD_MASK(3)
* #define <NAME>_S 4
* ...
* regval = R_REG(osh, &regs->regfoo);
* field = GFIELD(regval, <NAME>);
* regval = SFIELD(regval, <NAME>, 1);
* W_REG(osh, &regs->regfoo, regval);
*/
#define BITFIELD_MASK(width) \
(((unsigned)1 << (width)) - 1)
#define GFIELD(val, field) \
(((val) >> field ## _S) & field ## _M)
#define SFIELD(val, field, bits) \
(((val) & (~(field ## _M << field ## _S))) | \
((unsigned)(bits) << field ## _S))
/* define BCMSMALL to remove misc features for memory-constrained environments */
#define BCMSPACE
#define bcmspace TRUE /* if (bcmspace) code is retained */
/* Max. nvram variable table size */
#define MAXSZ_NVRAM_VARS 4096
#define LOCATOR_EXTERN static
#endif /* _bcmdefs_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BCMDEVS_H
#define _BCMDEVS_H
/* PCI vendor IDs */
#define VENDOR_BROADCOM 0x14e4
/* DONGLE VID/PIDs */
#define BCM_DNGL_VID 0x0a5c
#define BCM_DNGL_BDC_PID 0x0bdc
#define BCM4329_D11N_ID 0x432e /* 4329 802.11n dualband device */
#define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */
#define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */
#define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */
#define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */
#define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */
#define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
#define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
#define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */
#define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
#define BCM43236_D11N5G_ID 0x4348 /* 43236 802.11n 5GHz device */
#define BCM43421_D11N_ID 0xA99D /* 43421 802.11n dualband device */
#define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
#define BCM4330_D11N_ID 0x4360 /* 4330 802.11n dualband device */
#define BCM4330_D11N2G_ID 0x4361 /* 4330 802.11n 2.4G device */
#define BCM4330_D11N5G_ID 0x4362 /* 4330 802.11n 5G device */
#define BCM4336_D11N_ID 0x4343 /* 4336 802.11n 2.4GHz device */
#define BCM6362_D11N_ID 0x435f /* 6362 802.11n dualband device */
#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
#define BCM4331_D11N2G_ID 0x4332 /* 4331 802.11n 2.4Ghz band id */
#define BCM4331_D11N5G_ID 0x4333 /* 4331 802.11n 5Ghz band id */
/* Chip IDs */
#define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */
#define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */
#define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */
#define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */
#define BCM43228_CHIP_ID 43228 /* 43228 chipcommon chipid */
#define BCM43421_CHIP_ID 43421 /* 43421 chipcommon chipid */
#define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */
#define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */
#define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */
#define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */
#define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */
#define BCM4336_CHIP_ID 0x4336 /* 4336 chipcommon chipid */
#define BCM4330_CHIP_ID 0x4330 /* 4330 chipcommon chipid */
#define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */
/* these are router chips */
#define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
#define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
#define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
#define BCM5356_CHIP_ID 0x5356 /* 5356 chipcommon chipid */
#define BCM5357_CHIP_ID 0x5357 /* 5357 chipcommon chipid */
/* Package IDs */
#define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */
#define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */
#define BCM4716_PKG_ID 8 /* 4716 package id */
#define BCM4717_PKG_ID 9 /* 4717 package id */
#define BCM4718_PKG_ID 10 /* 4718 package id */
#define BCM5356_PKG_NONMODE 1 /* 5356 package without nmode suppport */
#define BCM5358U_PKG_ID 8 /* 5358U package id */
#define BCM5358_PKG_ID 9 /* 5358 package id */
#define BCM47186_PKG_ID 10 /* 47186 package id */
#define BCM5357_PKG_ID 11 /* 5357 package id */
#define BCM5356U_PKG_ID 12 /* 5356U package id */
#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
#define BCM43224_FAB_CSM 0x8 /* the chip is manufactured by CSM */
#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
#define BCM4336_WLBGA_PKG_ID 0x8
/* boardflags */
#define BFL_RESERVED1 0x00000001
#define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */
#define BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication */
#define BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */
#define BFL_ENETROBO 0x00000010 /* Board has robo switch or core */
#define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
#define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
#define BFL_ENETADM 0x00000080 /* Board has ADMtek switch */
#define BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */
#define BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
#define BFL_FEM 0x00000800 /* Board supports the Front End Module */
#define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
#define BFL_HGPA 0x00002000 /* Board has a high gain PA */
#define BFL_RESERVED2 0x00004000
#define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */
#define BFL_NOPA 0x00010000 /* Board has no PA */
#define BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */
#define BFL_PAREF 0x00040000 /* Board uses the PARef LDO */
#define BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */
#define BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */
#define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */
#define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */
#define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */
#define BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */
#define BFL_PALDO 0x02000000 /* Power topology uses PALDO */
#define BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */
#define BFL_FASTPWR 0x08000000
#define BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */
#define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
#define BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */
#define BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */
#define BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field
* when this flag is set
*/
/* boardflags2 */
#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
#define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
#define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */
#define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */
#define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */
#define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */
#define BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */
#define BFL2_LEGACY 0x00000080
#define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */
#define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
#define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
#define BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */
#define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */
#define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
#define BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */
#define BFL2_FCC_BANDEDGE_WAR 0x00008000 /* using 40Mhz LPF for 20Mhz bandedge channels */
#define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
#define BFL2_IPALVLSHIFT_3P3 0x00020000
#define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */
#define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio "ON"
* Most drivers will turn it off without this flag
* to save power.
*/
/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
#define BOARD_GPIO_RESERVED1 0x010
#define BOARD_GPIO_RESERVED2 0x020
#define BOARD_GPIO_RESERVED3 0x080
#define BOARD_GPIO_RESERVED4 0x100
#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
#define BOARD_GPIO_12 0x1000 /* gpio 12 */
#define BOARD_GPIO_13 0x2000 /* gpio 13 */
#define BOARD_GPIO_RESERVED5 0x0800
#define BOARD_GPIO_RESERVED6 0x2000
#define BOARD_GPIO_RESERVED7 0x4000
#define BOARD_GPIO_RESERVED8 0x8000
#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */
#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */
/* power control defines */
#define PLL_DELAY 150 /* us pll on delay */
#define FREF_DELAY 200 /* us fref change delay */
#define MIN_SLOW_CLK 32 /* us Slow clock period */
#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
/* # of GPIO pins */
#define GPIO_NUMPINS 16
/* Reference board types */
#define SPI_BOARD 0x0402
#endif /* _BCMDEVS_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BCMENDIAN_H_
#define _BCMENDIAN_H_
#include <typedefs.h>
/* Reverse the bytes in a 16-bit value */
#define BCMSWAP16(val) \
((uint16)((((uint16)(val) & (uint16)0x00ffU) << 8) | \
(((uint16)(val) & (uint16)0xff00U) >> 8)))
/* Reverse the bytes in a 32-bit value */
#define BCMSWAP32(val) \
((uint32)((((uint32)(val) & (uint32)0x000000ffU) << 24) | \
(((uint32)(val) & (uint32)0x0000ff00U) << 8) | \
(((uint32)(val) & (uint32)0x00ff0000U) >> 8) | \
(((uint32)(val) & (uint32)0xff000000U) >> 24)))
/* Reverse the two 16-bit halves of a 32-bit value */
#define BCMSWAP32BY16(val) \
((uint32)((((uint32)(val) & (uint32)0x0000ffffU) << 16) | \
(((uint32)(val) & (uint32)0xffff0000U) >> 16)))
/* Byte swapping macros
* Host <=> Network (Big Endian) for 16- and 32-bit values
* Host <=> Little-Endian for 16- and 32-bit values
*/
#ifndef hton16
#ifndef IL_BIGENDIAN
#define HTON16(i) BCMSWAP16(i)
#define hton16(i) bcmswap16(i)
#define HTON32(i) BCMSWAP32(i)
#define hton32(i) bcmswap32(i)
#define NTOH16(i) BCMSWAP16(i)
#define ntoh16(i) bcmswap16(i)
#define NTOH32(i) BCMSWAP32(i)
#define ntoh32(i) bcmswap32(i)
#define LTOH16(i) (i)
#define ltoh16(i) (i)
#define LTOH32(i) (i)
#define ltoh32(i) (i)
#define HTOL16(i) (i)
#define htol16(i) (i)
#define HTOL32(i) (i)
#define htol32(i) (i)
#else /* IL_BIGENDIAN */
#define HTON16(i) (i)
#define hton16(i) (i)
#define HTON32(i) (i)
#define hton32(i) (i)
#define NTOH16(i) (i)
#define ntoh16(i) (i)
#define NTOH32(i) (i)
#define ntoh32(i) (i)
#define LTOH16(i) BCMSWAP16(i)
#define ltoh16(i) bcmswap16(i)
#define LTOH32(i) BCMSWAP32(i)
#define ltoh32(i) bcmswap32(i)
#define HTOL16(i) BCMSWAP16(i)
#define htol16(i) bcmswap16(i)
#define HTOL32(i) BCMSWAP32(i)
#define htol32(i) bcmswap32(i)
#endif /* IL_BIGENDIAN */
#endif /* hton16 */
#ifndef IL_BIGENDIAN
#define ltoh16_buf(buf, i)
#define htol16_buf(buf, i)
#else
#define ltoh16_buf(buf, i) bcmswap16_buf((uint16 *)(buf), (i))
#define htol16_buf(buf, i) bcmswap16_buf((uint16 *)(buf), (i))
#endif /* IL_BIGENDIAN */
/* Unaligned loads and stores in host byte order */
#ifndef IL_BIGENDIAN
#define load32_ua(a) ltoh32_ua(a)
#define store32_ua(a, v) htol32_ua_store(v, a)
#define load16_ua(a) ltoh16_ua(a)
#define store16_ua(a, v) htol16_ua_store(v, a)
#else
#define load32_ua(a) ntoh32_ua(a)
#define store32_ua(a, v) hton32_ua_store(v, a)
#define load16_ua(a) ntoh16_ua(a)
#define store16_ua(a, v) hton16_ua_store(v, a)
#endif /* IL_BIGENDIAN */
#define _LTOH16_UA(cp) ((cp)[0] | ((cp)[1] << 8))
#define _LTOH32_UA(cp) ((cp)[0] | ((cp)[1] << 8) | ((cp)[2] << 16) | ((cp)[3] << 24))
#define _NTOH16_UA(cp) (((cp)[0] << 8) | (cp)[1])
#define _NTOH32_UA(cp) (((cp)[0] << 24) | ((cp)[1] << 16) | ((cp)[2] << 8) | (cp)[3])
#define ltoh_ua(ptr) \
(sizeof(*(ptr)) == sizeof(uint8) ? *(const uint8 *)(ptr) : \
sizeof(*(ptr)) == sizeof(uint16) ? _LTOH16_UA((const uint8 *)(ptr)) : \
sizeof(*(ptr)) == sizeof(uint32) ? _LTOH32_UA((const uint8 *)(ptr)) : \
*(uint8 *)0)
#define ntoh_ua(ptr) \
(sizeof(*(ptr)) == sizeof(uint8) ? *(const uint8 *)(ptr) : \
sizeof(*(ptr)) == sizeof(uint16) ? _NTOH16_UA((const uint8 *)(ptr)) : \
sizeof(*(ptr)) == sizeof(uint32) ? _NTOH32_UA((const uint8 *)(ptr)) : \
*(uint8 *)0)
#ifdef __GNUC__
/* GNU macro versions avoid referencing the argument multiple times, while also
* avoiding the -fno-inline used in ROM builds.
*/
#define bcmswap16(val) ({ \
uint16 _val = (val); \
BCMSWAP16(_val); \
})
#define bcmswap32(val) ({ \
uint32 _val = (val); \
BCMSWAP32(_val); \
})
#define bcmswap32by16(val) ({ \
uint32 _val = (val); \
BCMSWAP32BY16(_val); \
})
#define bcmswap16_buf(buf, len) ({ \
uint16 *_buf = (uint16 *)(buf); \
uint _wds = (len) / 2; \
while (_wds--) { \
*_buf = bcmswap16(*_buf); \
_buf++; \
} \
})
#define htol16_ua_store(val, bytes) ({ \
uint16 _val = (val); \
uint8 *_bytes = (uint8 *)(bytes); \
_bytes[0] = _val & 0xff; \
_bytes[1] = _val >> 8; \
})
#define htol32_ua_store(val, bytes) ({ \
uint32 _val = (val); \
uint8 *_bytes = (uint8 *)(bytes); \
_bytes[0] = _val & 0xff; \
_bytes[1] = (_val >> 8) & 0xff; \
_bytes[2] = (_val >> 16) & 0xff; \
_bytes[3] = _val >> 24; \
})
#define hton16_ua_store(val, bytes) ({ \
uint16 _val = (val); \
uint8 *_bytes = (uint8 *)(bytes); \
_bytes[0] = _val >> 8; \
_bytes[1] = _val & 0xff; \
})
#define hton32_ua_store(val, bytes) ({ \
uint32 _val = (val); \
uint8 *_bytes = (uint8 *)(bytes); \
_bytes[0] = _val >> 24; \
_bytes[1] = (_val >> 16) & 0xff; \
_bytes[2] = (_val >> 8) & 0xff; \
_bytes[3] = _val & 0xff; \
})
#define ltoh16_ua(bytes) ({ \
const uint8 *_bytes = (const uint8 *)(bytes); \
_LTOH16_UA(_bytes); \
})
#define ltoh32_ua(bytes) ({ \
const uint8 *_bytes = (const uint8 *)(bytes); \
_LTOH32_UA(_bytes); \
})
#define ntoh16_ua(bytes) ({ \
const uint8 *_bytes = (const uint8 *)(bytes); \
_NTOH16_UA(_bytes); \
})
#define ntoh32_ua(bytes) ({ \
const uint8 *_bytes = (const uint8 *)(bytes); \
_NTOH32_UA(_bytes); \
})
#else /* !__GNUC__ */
/* Inline versions avoid referencing the argument multiple times */
static INLINE uint16 bcmswap16(uint16 val)
{
return BCMSWAP16(val);
}
static INLINE uint32 bcmswap32(uint32 val)
{
return BCMSWAP32(val);
}
static INLINE uint32 bcmswap32by16(uint32 val)
{
return BCMSWAP32BY16(val);
}
/* Reverse pairs of bytes in a buffer (not for high-performance use) */
/* buf - start of buffer of shorts to swap */
/* len - byte length of buffer */
static INLINE void bcmswap16_buf(uint16 * buf, uint len)
{
len = len / 2;
while (len--) {
*buf = bcmswap16(*buf);
buf++;
}
}
/*
* Store 16-bit value to unaligned little-endian byte array.
*/
static INLINE void htol16_ua_store(uint16 val, uint8 * bytes)
{
bytes[0] = val & 0xff;
bytes[1] = val >> 8;
}
/*
* Store 32-bit value to unaligned little-endian byte array.
*/
static INLINE void htol32_ua_store(uint32 val, uint8 * bytes)
{
bytes[0] = val & 0xff;
bytes[1] = (val >> 8) & 0xff;
bytes[2] = (val >> 16) & 0xff;
bytes[3] = val >> 24;
}
/*
* Store 16-bit value to unaligned network-(big-)endian byte array.
*/
static INLINE void hton16_ua_store(uint16 val, uint8 * bytes)
{
bytes[0] = val >> 8;
bytes[1] = val & 0xff;
}
/*
* Store 32-bit value to unaligned network-(big-)endian byte array.
*/
static INLINE void hton32_ua_store(uint32 val, uint8 * bytes)
{
bytes[0] = val >> 24;
bytes[1] = (val >> 16) & 0xff;
bytes[2] = (val >> 8) & 0xff;
bytes[3] = val & 0xff;
}
/*
* Load 16-bit value from unaligned little-endian byte array.
*/
static INLINE uint16 ltoh16_ua(const void *bytes)
{
return _LTOH16_UA((const uint8 *)bytes);
}
/*
* Load 32-bit value from unaligned little-endian byte array.
*/
static INLINE uint32 ltoh32_ua(const void *bytes)
{
return _LTOH32_UA((const uint8 *)bytes);
}
/*
* Load 16-bit value from unaligned big-(network-)endian byte array.
*/
static INLINE uint16 ntoh16_ua(const void *bytes)
{
return _NTOH16_UA((const uint8 *)bytes);
}
/*
* Load 32-bit value from unaligned big-(network-)endian byte array.
*/
static INLINE uint32 ntoh32_ua(const void *bytes)
{
return _NTOH32_UA((const uint8 *)bytes);
}
#endif /* !__GNUC__ */
#endif /* !_BCMENDIAN_H_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmnvram_h_
#define _bcmnvram_h_
#ifndef _LANGUAGE_ASSEMBLY
#include <typedefs.h>
#include <bcmdefs.h>
struct nvram_header {
uint32 magic;
uint32 len;
uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
uint32 config_ncdl; /* ncdl values for memc */
};
struct nvram_tuple {
char *name;
char *value;
struct nvram_tuple *next;
};
/*
* Get default value for an NVRAM variable
*/
extern char *nvram_default_get(const char *name);
/*
* Initialize NVRAM access. May be unnecessary or undefined on certain
* platforms.
*/
extern int nvram_init(void *sih);
/*
* Append a chunk of nvram variables to the global list
*/
extern int nvram_append(void *si, char *vars, uint varsz);
/*
* Check for reset button press for restoring factory defaults.
*/
extern int nvram_reset(void *sih);
/*
* Disable NVRAM access. May be unnecessary or undefined on certain
* platforms.
*/
extern void nvram_exit(void *sih);
/*
* Get the value of an NVRAM variable. The pointer returned may be
* invalid after a set.
* @param name name of variable to get
* @return value of variable or NULL if undefined
*/
extern char *nvram_get(const char *name);
/*
* Read the reset GPIO value from the nvram and set the GPIO
* as input
*/
extern int BCMINITFN(nvram_resetgpio_init) (void *sih);
/*
* Get the value of an NVRAM variable.
* @param name name of variable to get
* @return value of variable or NUL if undefined
*/
#define nvram_safe_get(name) (nvram_get(name) ? : "")
/*
* Match an NVRAM variable.
* @param name name of variable to match
* @param match value to compare against value of variable
* @return TRUE if variable is defined and its value is string equal
* to match or FALSE otherwise
*/
static INLINE int nvram_match(char *name, char *match)
{
const char *value = nvram_get(name);
return (value && !strcmp(value, match));
}
/*
* Inversely match an NVRAM variable.
* @param name name of variable to match
* @param match value to compare against value of variable
* @return TRUE if variable is defined and its value is not string
* equal to invmatch or FALSE otherwise
*/
static INLINE int nvram_invmatch(char *name, char *invmatch)
{
const char *value = nvram_get(name);
return (value && strcmp(value, invmatch));
}
/*
* Set the value of an NVRAM variable. The name and value strings are
* copied into private storage. Pointers to previously set values
* may become invalid. The new value may be immediately
* retrieved but will not be permanently stored until a commit.
* @param name name of variable to set
* @param value value of variable
* @return 0 on success and errno on failure
*/
extern int nvram_set(const char *name, const char *value);
/*
* Unset an NVRAM variable. Pointers to previously set values
* remain valid until a set.
* @param name name of variable to unset
* @return 0 on success and errno on failure
* NOTE: use nvram_commit to commit this change to flash.
*/
extern int nvram_unset(const char *name);
/*
* Commit NVRAM variables to permanent storage. All pointers to values
* may be invalid after a commit.
* NVRAM values are undefined after a commit.
* @return 0 on success and errno on failure
*/
extern int nvram_commit(void);
/*
* Get all NVRAM variables (format name=value\0 ... \0\0).
* @param buf buffer to store variables
* @param count size of buffer in bytes
* @return 0 on success and errno on failure
*/
extern int nvram_getall(char *nvram_buf, int count);
/*
* returns the crc value of the nvram
* @param nvh nvram header pointer
*/
uint8 nvram_calc_crc(struct nvram_header *nvh);
#endif /* _LANGUAGE_ASSEMBLY */
/* The NVRAM version number stored as an NVRAM variable */
#define NVRAM_SOFTWARE_VERSION "1"
#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
#define NVRAM_CLEAR_MAGIC 0x0
#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
#define NVRAM_VERSION 1
#define NVRAM_HEADER_SIZE 20
#define NVRAM_SPACE 0x8000
#define NVRAM_MAX_VALUE_LEN 255
#define NVRAM_MAX_PARAM_LEN 64
#define NVRAM_CRC_START_POSITION 9 /* magic, len, crc8 to be skipped */
#define NVRAM_CRC_VER_MASK 0xffffff00 /* for crc_ver_init */
#endif /* _bcmnvram_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmotp_h_
#define _bcmotp_h_
/* OTP regions */
#define OTP_HW_RGN 1
#define OTP_SW_RGN 2
#define OTP_CI_RGN 4
#define OTP_FUSE_RGN 8
#define OTP_ALL_RGN 0xf /* From h/w region to end of OTP including checksum */
/* OTP Size */
#define OTP_SZ_MAX (6144/8) /* maximum bytes in one CIS */
/* Fixed size subregions sizes in words */
#define OTPGU_CI_SZ 2
/* OTP usage */
#define OTP4325_FM_DISABLED_OFFSET 188
/* Exported functions */
extern int otp_status(void *oh);
extern int otp_size(void *oh);
extern uint16 otp_read_bit(void *oh, uint offset);
extern void *otp_init(si_t * sih);
extern int otp_read_region(si_t * sih, int region, uint16 * data, uint * wlen);
extern int otp_nvread(void *oh, char *data, uint * len);
#endif /* _bcmotp_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _sdio_api_h_
#define _sdio_api_h_
#define SDIOH_API_RC_SUCCESS (0x00)
#define SDIOH_API_RC_FAIL (0x01)
#define SDIOH_API_SUCCESS(status) (status == 0)
#define SDIOH_READ 0 /* Read request */
#define SDIOH_WRITE 1 /* Write request */
#define SDIOH_DATA_FIX 0 /* Fixed addressing */
#define SDIOH_DATA_INC 1 /* Incremental addressing */
#define SDIOH_CMD_TYPE_NORMAL 0 /* Normal command */
#define SDIOH_CMD_TYPE_APPEND 1 /* Append command */
#define SDIOH_CMD_TYPE_CUTTHRU 2 /* Cut-through command */
#define SDIOH_DATA_PIO 0 /* PIO mode */
#define SDIOH_DATA_DMA 1 /* DMA mode */
typedef int SDIOH_API_RC;
/* SDio Host structure */
typedef struct sdioh_info sdioh_info_t;
/* callback function, taking one arg */
typedef void (*sdioh_cb_fn_t) (void *);
/* attach, return handler on success, NULL if failed.
* The handler shall be provided by all subsequent calls. No local cache
* cfghdl points to the starting address of pci device mapped memory
*/
extern sdioh_info_t *sdioh_attach(osl_t * osh, void *cfghdl, uint irq);
extern SDIOH_API_RC sdioh_detach(osl_t * osh, sdioh_info_t * si);
extern SDIOH_API_RC sdioh_interrupt_register(sdioh_info_t * si,
sdioh_cb_fn_t fn, void *argh);
extern SDIOH_API_RC sdioh_interrupt_deregister(sdioh_info_t * si);
/* query whether SD interrupt is enabled or not */
extern SDIOH_API_RC sdioh_interrupt_query(sdioh_info_t * si, bool * onoff);
/* enable or disable SD interrupt */
extern SDIOH_API_RC sdioh_interrupt_set(sdioh_info_t * si, bool enable_disable);
#if defined(BCMDBG)
extern bool sdioh_interrupt_pending(sdioh_info_t * si);
#endif
extern int sdioh_claim_host_and_lock(sdioh_info_t * si);
extern int sdioh_release_host_and_unlock(sdioh_info_t * si);
/* read or write one byte using cmd52 */
extern SDIOH_API_RC sdioh_request_byte(sdioh_info_t * si, uint rw, uint fnc,
uint addr, uint8 * byte);
/* read or write 2/4 bytes using cmd53 */
extern SDIOH_API_RC sdioh_request_word(sdioh_info_t * si, uint cmd_type,
uint rw, uint fnc, uint addr,
uint32 * word, uint nbyte);
/* read or write any buffer using cmd53 */
extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t * si, uint pio_dma,
uint fix_inc, uint rw, uint fnc_num,
uint32 addr, uint regwidth,
uint32 buflen, uint8 * buffer,
void *pkt);
/* get cis data */
extern SDIOH_API_RC sdioh_cis_read(sdioh_info_t * si, uint fuc, uint8 * cis,
uint32 length);
extern SDIOH_API_RC sdioh_cfg_read(sdioh_info_t * si, uint fuc, uint32 addr,
uint8 * data);
extern SDIOH_API_RC sdioh_cfg_write(sdioh_info_t * si, uint fuc, uint32 addr,
uint8 * data);
/* query number of io functions */
extern uint sdioh_query_iofnum(sdioh_info_t * si);
/* handle iovars */
extern int sdioh_iovar_op(sdioh_info_t * si, const char *name,
void *params, int plen, void *arg, int len, bool set);
/* Issue abort to the specified function and clear controller as needed */
extern int sdioh_abort(sdioh_info_t * si, uint fnc);
/* Start and Stop SDIO without re-enumerating the SD card. */
extern int sdioh_start(sdioh_info_t * si, int stage);
extern int sdioh_stop(sdioh_info_t * si);
/* Reset and re-initialize the device */
extern int sdioh_sdio_reset(sdioh_info_t * si);
/* Helper function */
void *bcmsdh_get_sdioh(bcmsdh_info_t * sdh);
#endif /* _sdio_api_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmsdh_h_
#define _bcmsdh_h_
#define BCMSDH_ERROR_VAL 0x0001 /* Error */
#define BCMSDH_INFO_VAL 0x0002 /* Info */
extern const uint bcmsdh_msglevel;
#ifdef BCMDBG
#define BCMSDH_ERROR(x) do { if ((bcmsdh_msglevel & BCMSDH_ERROR_VAL) && net_ratelimit()) printf x; } while (0)
#define BCMSDH_INFO(x) do { if ((bcmsdh_msglevel & BCMSDH_INFO_VAL) && net_ratelimit()) printf x; } while (0)
#else /* BCMDBG */
#define BCMSDH_ERROR(x)
#define BCMSDH_INFO(x)
#endif /* BCMDBG */
/* forward declarations */
typedef struct bcmsdh_info bcmsdh_info_t;
typedef void (*bcmsdh_cb_fn_t) (void *);
/* Attach and build an interface to the underlying SD host driver.
* - Allocates resources (structs, arrays, mem, OS handles, etc) needed by bcmsdh.
* - Returns the bcmsdh handle and virtual address base for register access.
* The returned handle should be used in all subsequent calls, but the bcmsh
* implementation may maintain a single "default" handle (e.g. the first or
* most recent one) to enable single-instance implementations to pass NULL.
*/
extern bcmsdh_info_t *bcmsdh_attach(osl_t * osh, void *cfghdl, void **regsva,
uint irq);
/* Detach - freeup resources allocated in attach */
extern int bcmsdh_detach(osl_t * osh, void *sdh);
/* Query if SD device interrupts are enabled */
extern bool bcmsdh_intr_query(void *sdh);
/* Enable/disable SD interrupt */
extern int bcmsdh_intr_enable(void *sdh);
extern int bcmsdh_intr_disable(void *sdh);
/* Register/deregister device interrupt handler. */
extern int bcmsdh_intr_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
extern int bcmsdh_intr_dereg(void *sdh);
#if defined(BCMDBG)
/* Query pending interrupt status from the host controller */
extern bool bcmsdh_intr_pending(void *sdh);
#endif
extern int bcmsdh_claim_host_and_lock(void *sdh);
extern int bcmsdh_release_host_and_unlock(void *sdh);
/* Register a callback to be called if and when bcmsdh detects
* device removal. No-op in the case of non-removable/hardwired devices.
*/
extern int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
/* Access SDIO address space (e.g. CCCR) using CMD52 (single-byte interface).
* fn: function number
* addr: unmodified SDIO-space address
* data: data byte to write
* err: pointer to error code (or NULL)
*/
extern uint8 bcmsdh_cfg_read(void *sdh, uint func, uint32 addr, int *err);
extern void bcmsdh_cfg_write(void *sdh, uint func, uint32 addr, uint8 data,
int *err);
/* Read/Write 4bytes from/to cfg space */
extern uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr,
int *err);
extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr,
uint32 data, int *err);
/* Read CIS content for specified function.
* fn: function whose CIS is being requested (0 is common CIS)
* cis: pointer to memory location to place results
* length: number of bytes to read
* Internally, this routine uses the values from the cis base regs (0x9-0xB)
* to form an SDIO-space address to read the data from.
*/
extern int bcmsdh_cis_read(void *sdh, uint func, uint8 * cis, uint length);
/* Synchronous access to device (client) core registers via CMD53 to F1.
* addr: backplane address (i.e. >= regsva from attach)
* size: register width in bytes (2 or 4)
* data: data for register write
*/
extern uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size);
extern uint32 bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data);
/* Indicate if last reg read/write failed */
extern bool bcmsdh_regfail(void *sdh);
/* Buffer transfer to/from device (client) core via cmd53.
* fn: function number
* addr: backplane address (i.e. >= regsva from attach)
* flags: backplane width, address increment, sync/async
* buf: pointer to memory data buffer
* nbytes: number of bytes to transfer to/from buf
* pkt: pointer to packet associated with buf (if any)
* complete: callback function for command completion (async only)
* handle: handle for completion callback (first arg in callback)
* Returns 0 or error code.
* NOTE: Async operation is not currently supported.
*/
typedef void (*bcmsdh_cmplt_fn_t) (void *handle, int status, bool sync_waiting);
extern int bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags,
uint8 * buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle);
extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
uint8 * buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle);
/* Flags bits */
#define SDIO_REQ_4BYTE 0x1 /* Four-byte target (backplane) width (vs. two-byte) */
#define SDIO_REQ_FIXED 0x2 /* Fixed address (FIFO) (vs. incrementing address) */
#define SDIO_REQ_ASYNC 0x4 /* Async request (vs. sync request) */
/* Pending (non-error) return code */
#define BCME_PENDING 1
/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
* rw: read or write (0/1)
* addr: direct SDIO address
* buf: pointer to memory data buffer
* nbytes: number of bytes to transfer to/from buf
* Returns 0 or error code.
*/
extern int bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, uint8 * buf,
uint nbytes);
/* Issue an abort to the specified function */
extern int bcmsdh_abort(void *sdh, uint fn);
/* Start SDIO Host Controller communication */
extern int bcmsdh_start(void *sdh, int stage);
/* Stop SDIO Host Controller communication */
extern int bcmsdh_stop(void *sdh);
/* Returns the "Device ID" of target device on the SDIO bus. */
extern int bcmsdh_query_device(void *sdh);
/* Returns the number of IO functions reported by the device */
extern uint bcmsdh_query_iofnum(void *sdh);
/* Miscellaneous knob tweaker. */
extern int bcmsdh_iovar_op(void *sdh, const char *name,
void *params, int plen, void *arg, int len,
bool set);
/* Reset and reinitialize the device */
extern int bcmsdh_reset(bcmsdh_info_t * sdh);
/* helper functions */
extern void *bcmsdh_get_sdioh(bcmsdh_info_t * sdh);
/* callback functions */
typedef struct {
/* attach to device */
void *(*attach) (uint16 vend_id, uint16 dev_id, uint16 bus, uint16 slot,
uint16 func, uint bustype, void *regsva, osl_t * osh,
void *param);
/* detach from device */
void (*detach) (void *ch);
} bcmsdh_driver_t;
/* platform specific/high level functions */
extern int bcmsdh_register(bcmsdh_driver_t * driver);
extern void bcmsdh_unregister(void);
extern bool bcmsdh_chipmatch(uint16 vendor, uint16 device);
extern void bcmsdh_device_remove(void *sdh);
/* Function to pass device-status bits to DHD. */
extern uint32 bcmsdh_get_dstatus(void *sdh);
/* Function to return current window addr */
extern uint32 bcmsdh_cur_sbwad(void *sdh);
/* Function to pass chipid and rev to lower layers for controlling pr's */
extern void bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev);
#endif /* _bcmsdh_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __BCMSDH_SDMMC_H__
#define __BCMSDH_SDMMC_H__
#ifdef BCMDBG
#define sd_err(x) do { if ((sd_msglevel & SDH_ERROR_VAL) && net_ratelimit()) printf x; } while (0)
#define sd_trace(x) do { if ((sd_msglevel & SDH_TRACE_VAL) && net_ratelimit()) printf x; } while (0)
#define sd_info(x) do { if ((sd_msglevel & SDH_INFO_VAL) && net_ratelimit()) printf x; } while (0)
#define sd_debug(x) do { if ((sd_msglevel & SDH_DEBUG_VAL) && net_ratelimit()) printf x; } while (0)
#define sd_data(x) do { if ((sd_msglevel & SDH_DATA_VAL) && net_ratelimit()) printf x; } while (0)
#define sd_ctrl(x) do { if ((sd_msglevel & SDH_CTRL_VAL) && net_ratelimit()) printf x; } while (0)
#else
#define sd_err(x)
#define sd_trace(x)
#define sd_info(x)
#define sd_debug(x)
#define sd_data(x)
#define sd_ctrl(x)
#endif
/* Allocate/init/free per-OS private data */
extern int sdioh_sdmmc_osinit(sdioh_info_t * sd);
extern void sdioh_sdmmc_osfree(sdioh_info_t * sd);
#define BLOCK_SIZE_64 64
#define BLOCK_SIZE_512 512
/* internal return code */
#define SUCCESS 0
#define ERROR 1
/* private bus modes */
#define SDIOH_MODE_SD4 2
#define CLIENT_INTR 0x100 /* Get rid of this! */
struct sdioh_info {
osl_t *osh; /* osh handler */
bool client_intr_enabled; /* interrupt connnected flag */
bool intr_handler_valid; /* client driver interrupt handler valid */
sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
void *intr_handler_arg; /* argument to call interrupt handler */
uint16 intmask; /* Current active interrupts */
void *sdos_info; /* Pointer to per-OS private data */
uint irq; /* Client irq */
int intrcount; /* Client interrupts */
bool sd_use_dma; /* DMA on CMD53 */
bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
/* Must be on for sd_multiblock to be effective */
bool use_client_ints; /* If this is false, make sure to restore */
int sd_mode; /* SD1/SD4/SPI */
int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
uint8 num_funcs; /* Supported funcs on client */
uint32 com_cis_ptr;
uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
uint max_dma_len;
uint max_dma_descriptors; /* DMA Descriptors supported by this controller. */
/* SDDMA_DESCRIPTOR SGList[32]; *//* Scatter/Gather DMA List */
};
/************************************************************
* Internal interfaces: per-port references into bcmsdh_sdmmc.c
*/
/* Global message bits */
extern uint sd_msglevel;
/* OS-independent interrupt handler */
extern bool check_client_intr(sdioh_info_t * sd);
/* Core interrupt enable/disable of device interrupts */
extern void sdioh_sdmmc_devintr_on(sdioh_info_t * sd);
extern void sdioh_sdmmc_devintr_off(sdioh_info_t * sd);
/**************************************************************
* Internal interfaces: bcmsdh_sdmmc.c references to per-port code
*/
/* Register mapping routines */
extern uint32 *sdioh_sdmmc_reg_map(osl_t * osh, int32 addr, int size);
extern void sdioh_sdmmc_reg_unmap(osl_t * osh, int32 addr, int size);
/* Interrupt (de)registration routines */
extern int sdioh_sdmmc_register_irq(sdioh_info_t * sd, uint irq);
extern void sdioh_sdmmc_free_irq(uint irq, sdioh_info_t * sd);
typedef struct _BCMSDH_SDMMC_INSTANCE {
sdioh_info_t *sd;
struct sdio_func *func[SDIOD_MAX_IOFUNCS];
uint32 host_claimed;
} BCMSDH_SDMMC_INSTANCE, *PBCMSDH_SDMMC_INSTANCE;
#endif /* __BCMSDH_SDMMC_H__ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmsdpcm_h_
#define _bcmsdpcm_h_
/*
* Software allocation of To SB Mailbox resources
*/
/* intstatus bits */
#define I_SMB_NAK I_SMB_SW0 /* To SB Mailbox Frame NAK */
#define I_SMB_INT_ACK I_SMB_SW1 /* To SB Mailbox Host Interrupt ACK */
#define I_SMB_USE_OOB I_SMB_SW2 /* To SB Mailbox Use OOB Wakeup */
#define I_SMB_DEV_INT I_SMB_SW3 /* To SB Mailbox Miscellaneous Interrupt */
#define I_TOSBMAIL (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT)
/* tosbmailbox bits corresponding to intstatus bits */
#define SMB_NAK (1 << 0) /* To SB Mailbox Frame NAK */
#define SMB_INT_ACK (1 << 1) /* To SB Mailbox Host Interrupt ACK */
#define SMB_USE_OOB (1 << 2) /* To SB Mailbox Use OOB Wakeup */
#define SMB_DEV_INT (1 << 3) /* To SB Mailbox Miscellaneous Interrupt */
#define SMB_MASK 0x0000000f /* To SB Mailbox Mask */
/* tosbmailboxdata */
#define SMB_DATA_VERSION_MASK 0x00ff0000 /* host protocol version (sent with F2 enable) */
#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version (sent with F2 enable) */
/*
* Software allocation of To Host Mailbox resources
*/
/* intstatus bits */
#define I_HMB_FC_STATE I_HMB_SW0 /* To Host Mailbox Flow Control State */
#define I_HMB_FC_CHANGE I_HMB_SW1 /* To Host Mailbox Flow Control State Changed */
#define I_HMB_FRAME_IND I_HMB_SW2 /* To Host Mailbox Frame Indication */
#define I_HMB_HOST_INT I_HMB_SW3 /* To Host Mailbox Miscellaneous Interrupt */
#define I_TOHOSTMAIL (I_HMB_FC_CHANGE | I_HMB_FRAME_IND | I_HMB_HOST_INT)
/* tohostmailbox bits corresponding to intstatus bits */
#define HMB_FC_ON (1 << 0) /* To Host Mailbox Flow Control State */
#define HMB_FC_CHANGE (1 << 1) /* To Host Mailbox Flow Control State Changed */
#define HMB_FRAME_IND (1 << 2) /* To Host Mailbox Frame Indication */
#define HMB_HOST_INT (1 << 3) /* To Host Mailbox Miscellaneous Interrupt */
#define HMB_MASK 0x0000000f /* To Host Mailbox Mask */
/* tohostmailboxdata */
#define HMB_DATA_NAKHANDLED 1 /* we're ready to retransmit NAK'd frame to host */
#define HMB_DATA_DEVREADY 2 /* we're ready to to talk to host after enable */
#define HMB_DATA_FC 4 /* per prio flowcontrol update flag to host */
#define HMB_DATA_FWREADY 8 /* firmware is ready for protocol activity */
#define HMB_DATA_FCDATA_MASK 0xff000000 /* per prio flowcontrol data */
#define HMB_DATA_FCDATA_SHIFT 24 /* per prio flowcontrol data */
#define HMB_DATA_VERSION_MASK 0x00ff0000 /* device protocol version (with devready) */
#define HMB_DATA_VERSION_SHIFT 16 /* device protocol version (with devready) */
/*
* Software-defined protocol header
*/
/* Current protocol version */
#define SDPCM_PROT_VERSION 4
/* SW frame header */
#define SDPCM_SEQUENCE_MASK 0x000000ff /* Sequence Number Mask */
#define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */
#define SDPCM_CHANNEL_MASK 0x00000f00 /* Channel Number Mask */
#define SDPCM_CHANNEL_SHIFT 8 /* Channel Number Shift */
#define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */
#define SDPCM_FLAGS_MASK 0x0000f000 /* Mask of flag bits */
#define SDPCM_FLAGS_SHIFT 12 /* Flag bits shift */
#define SDPCM_PACKET_FLAGS(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */
/* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */
#define SDPCM_NEXTLEN_MASK 0x00ff0000 /* Next Read Len Mask */
#define SDPCM_NEXTLEN_SHIFT 16 /* Next Read Len Shift */
#define SDPCM_NEXTLEN_VALUE(p) ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */
#define SDPCM_NEXTLEN_OFFSET 2
/* Data Offset from SOF (HW Tag, SW Tag, Pad) */
#define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
#define SDPCM_DOFFSET_VALUE(p) (((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
#define SDPCM_DOFFSET_MASK 0xff000000
#define SDPCM_DOFFSET_SHIFT 24
#define SDPCM_FCMASK_OFFSET 4 /* Flow control */
#define SDPCM_FCMASK_VALUE(p) (((uint8 *)p)[SDPCM_FCMASK_OFFSET ] & 0xff)
#define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
#define SDPCM_WINDOW_VALUE(p) (((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
#define SDPCM_VERSION_OFFSET 6 /* Version # */
#define SDPCM_VERSION_VALUE(p) (((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff)
#define SDPCM_UNUSED_OFFSET 7 /* Spare */
#define SDPCM_UNUSED_VALUE(p) (((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff)
#define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
/* logical channel numbers */
#define SDPCM_CONTROL_CHANNEL 0 /* Control Request/Response Channel Id */
#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
#define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets (superframes) */
#define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
#define SDPCM_MAX_CHANNEL 15
#define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for eight-bit frame seq number */
#define SDPCM_FLAG_RESVD0 0x01
#define SDPCM_FLAG_RESVD1 0x02
#define SDPCM_FLAG_GSPI_TXENAB 0x04
#define SDPCM_FLAG_GLOMDESC 0x08 /* Superframe descriptor mask */
/* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */
#define SDPCM_GLOMDESC_FLAG (SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT)
#define SDPCM_GLOMDESC(p) (((uint8 *)p)[1] & 0x80)
/* For TEST_CHANNEL packets, define another 4-byte header */
#define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2);
* Semantics of Ext byte depend on command.
* Len is current or requested frame length, not
* including test header; sent little-endian.
*/
#define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */
#define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */
#define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */
#define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count */
#define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off */
/* Handy macro for filling in datagen packets with a pattern */
#define SDPCM_TEST_FILL(byteno, id) ((uint8)(id + byteno))
/*
* Software counters (first part matches hardware counters)
*/
typedef volatile struct {
uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */
uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */
uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */
uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */
uint32 abort; /* AbortCount, SDIO: aborts */
uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */
uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */
uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */
uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */
uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */
uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */
uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */
uint32 rxdescuflo; /* receive descriptor underflows */
uint32 rxfifooflo; /* receive fifo overflows */
uint32 txfifouflo; /* transmit fifo underflows */
uint32 runt; /* runt (too short) frames recv'd from bus */
uint32 badlen; /* frame's rxh len does not match its hw tag len */
uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */
uint32 seqbreak; /* break in sequence # space from one rx frame to the next */
uint32 rxfcrc; /* frame rx header indicates crc error */
uint32 rxfwoos; /* frame rx header indicates write out of sync */
uint32 rxfwft; /* frame rx header indicates write frame termination */
uint32 rxfabort; /* frame rx header indicates frame aborted */
uint32 woosint; /* write out of sync interrupt */
uint32 roosint; /* read out of sync interrupt */
uint32 rftermint; /* read frame terminate interrupt */
uint32 wftermint; /* write frame terminate interrupt */
} sdpcmd_cnt_t;
/*
* Register Access Macros
*/
#define SDIODREV_IS(var, val) ((var) == (val))
#define SDIODREV_GE(var, val) ((var) >= (val))
#define SDIODREV_GT(var, val) ((var) > (val))
#define SDIODREV_LT(var, val) ((var) < (val))
#define SDIODREV_LE(var, val) ((var) <= (val))
#define SDIODDMAREG32(h, dir, chnl) \
((dir) == DMA_TX ? \
(void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].xmt) : \
(void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].rcv))
#define SDIODDMAREG64(h, dir, chnl) \
((dir) == DMA_TX ? \
(void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].xmt) : \
(void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].rcv))
#define SDIODDMAREG(h, dir, chnl) \
(SDIODREV_LT((h)->corerev, 1) ? \
SDIODDMAREG32((h), (dir), (chnl)) : \
SDIODDMAREG64((h), (dir), (chnl)))
#define PCMDDMAREG(h, dir, chnl) \
((dir) == DMA_TX ? \
(void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.xmt) : \
(void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.rcv))
#define SDPCMDMAREG(h, dir, chnl, coreid) \
((coreid) == SDIOD_CORE_ID ? \
SDIODDMAREG(h, dir, chnl) : \
PCMDDMAREG(h, dir, chnl))
#define SDIODFIFOREG(h, corerev) \
(SDIODREV_LT((corerev), 1) ? \
((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod32.dmafifo)) : \
((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod64.dmafifo)))
#define PCMDFIFOREG(h) \
((dma32diag_t *)(uintptr)&((h)->regs->dma.pcm32.dmafifo))
#define SDPCMFIFOREG(h, coreid, corerev) \
((coreid) == SDIOD_CORE_ID ? \
SDIODFIFOREG(h, corerev) : \
PCMDFIFOREG(h))
/*
* Shared structure between dongle and the host.
* The structure contains pointers to trap or assert information.
*/
#define SDPCM_SHARED_VERSION 0x0001
#define SDPCM_SHARED_VERSION_MASK 0x00FF
#define SDPCM_SHARED_ASSERT_BUILT 0x0100
#define SDPCM_SHARED_ASSERT 0x0200
#define SDPCM_SHARED_TRAP 0x0400
typedef struct {
uint32 flags;
uint32 trap_addr;
uint32 assert_exp_addr;
uint32 assert_file_addr;
uint32 assert_line;
uint32 console_addr; /* Address of hndrte_cons_t */
uint32 msgtrace_addr;
} sdpcm_shared_t;
extern sdpcm_shared_t sdpcm_shared;
#endif /* _bcmsdpcm_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmsrom_h_
#define _bcmsrom_h_
#include <bcmsrom_fmt.h>
/* Prototypes */
extern int srom_var_init(si_t * sih, uint bus, void *curmap, osl_t * osh,
char **vars, uint * count);
extern int srom_read(si_t * sih, uint bus, void *curmap, osl_t * osh,
uint byteoff, uint nbytes, uint16 * buf, bool check_crc);
/* parse standard PCMCIA cis, normally used by SB/PCMCIA/SDIO/SPI/OTP
* and extract from it into name=value pairs
*/
extern int srom_parsecis(osl_t * osh, uint8 ** pcis, uint ciscnt,
char **vars, uint * count);
#endif /* _bcmsrom_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmsrom_fmt_h_
#define _bcmsrom_fmt_h_
/* Maximum srom: 6 Kilobits == 768 bytes */
#define SROM_MAX 768
#define SROM_MAXW 384
#define VARS_MAX 4096
/* PCI fields */
#define PCI_F0DEVID 48
#define SROM_WORDS 64
#define SROM3_SWRGN_OFF 28 /* s/w region offset in words */
#define SROM_SSID 2
#define SROM_WL1LHMAXP 29
#define SROM_WL1LPAB0 30
#define SROM_WL1LPAB1 31
#define SROM_WL1LPAB2 32
#define SROM_WL1HPAB0 33
#define SROM_WL1HPAB1 34
#define SROM_WL1HPAB2 35
#define SROM_MACHI_IL0 36
#define SROM_MACMID_IL0 37
#define SROM_MACLO_IL0 38
#define SROM_MACHI_ET0 39
#define SROM_MACMID_ET0 40
#define SROM_MACLO_ET0 41
#define SROM_MACHI_ET1 42
#define SROM_MACMID_ET1 43
#define SROM_MACLO_ET1 44
#define SROM3_MACHI 37
#define SROM3_MACMID 38
#define SROM3_MACLO 39
#define SROM_BXARSSI2G 40
#define SROM_BXARSSI5G 41
#define SROM_TRI52G 42
#define SROM_TRI5GHL 43
#define SROM_RXPO52G 45
#define SROM2_ENETPHY 45
#define SROM_AABREV 46
/* Fields in AABREV */
#define SROM_BR_MASK 0x00ff
#define SROM_CC_MASK 0x0f00
#define SROM_CC_SHIFT 8
#define SROM_AA0_MASK 0x3000
#define SROM_AA0_SHIFT 12
#define SROM_AA1_MASK 0xc000
#define SROM_AA1_SHIFT 14
#define SROM_WL0PAB0 47
#define SROM_WL0PAB1 48
#define SROM_WL0PAB2 49
#define SROM_LEDBH10 50
#define SROM_LEDBH32 51
#define SROM_WL10MAXP 52
#define SROM_WL1PAB0 53
#define SROM_WL1PAB1 54
#define SROM_WL1PAB2 55
#define SROM_ITT 56
#define SROM_BFL 57
#define SROM_BFL2 28
#define SROM3_BFL2 61
#define SROM_AG10 58
#define SROM_CCODE 59
#define SROM_OPO 60
#define SROM3_LEDDC 62
#define SROM_CRCREV 63
/* SROM Rev 4: Reallocate the software part of the srom to accomodate
* MIMO features. It assumes up to two PCIE functions and 440 bytes
* of useable srom i.e. the useable storage in chips with OTP that
* implements hardware redundancy.
*/
#define SROM4_WORDS 220
#define SROM4_SIGN 32
#define SROM4_SIGNATURE 0x5372
#define SROM4_BREV 33
#define SROM4_BFL0 34
#define SROM4_BFL1 35
#define SROM4_BFL2 36
#define SROM4_BFL3 37
#define SROM5_BFL0 37
#define SROM5_BFL1 38
#define SROM5_BFL2 39
#define SROM5_BFL3 40
#define SROM4_MACHI 38
#define SROM4_MACMID 39
#define SROM4_MACLO 40
#define SROM5_MACHI 41
#define SROM5_MACMID 42
#define SROM5_MACLO 43
#define SROM4_CCODE 41
#define SROM4_REGREV 42
#define SROM5_CCODE 34
#define SROM5_REGREV 35
#define SROM4_LEDBH10 43
#define SROM4_LEDBH32 44
#define SROM5_LEDBH10 59
#define SROM5_LEDBH32 60
#define SROM4_LEDDC 45
#define SROM5_LEDDC 45
#define SROM4_AA 46
#define SROM4_AA2G_MASK 0x00ff
#define SROM4_AA2G_SHIFT 0
#define SROM4_AA5G_MASK 0xff00
#define SROM4_AA5G_SHIFT 8
#define SROM4_AG10 47
#define SROM4_AG32 48
#define SROM4_TXPID2G 49
#define SROM4_TXPID5G 51
#define SROM4_TXPID5GL 53
#define SROM4_TXPID5GH 55
#define SROM4_TXRXC 61
#define SROM4_TXCHAIN_MASK 0x000f
#define SROM4_TXCHAIN_SHIFT 0
#define SROM4_RXCHAIN_MASK 0x00f0
#define SROM4_RXCHAIN_SHIFT 4
#define SROM4_SWITCH_MASK 0xff00
#define SROM4_SWITCH_SHIFT 8
/* Per-path fields */
#define MAX_PATH_SROM 4
#define SROM4_PATH0 64
#define SROM4_PATH1 87
#define SROM4_PATH2 110
#define SROM4_PATH3 133
#define SROM4_2G_ITT_MAXP 0
#define SROM4_2G_PA 1
#define SROM4_5G_ITT_MAXP 5
#define SROM4_5GLH_MAXP 6
#define SROM4_5G_PA 7
#define SROM4_5GL_PA 11
#define SROM4_5GH_PA 15
/* Fields in the ITT_MAXP and 5GLH_MAXP words */
#define B2G_MAXP_MASK 0xff
#define B2G_ITT_SHIFT 8
#define B5G_MAXP_MASK 0xff
#define B5G_ITT_SHIFT 8
#define B5GH_MAXP_MASK 0xff
#define B5GL_MAXP_SHIFT 8
/* All the miriad power offsets */
#define SROM4_2G_CCKPO 156
#define SROM4_2G_OFDMPO 157
#define SROM4_5G_OFDMPO 159
#define SROM4_5GL_OFDMPO 161
#define SROM4_5GH_OFDMPO 163
#define SROM4_2G_MCSPO 165
#define SROM4_5G_MCSPO 173
#define SROM4_5GL_MCSPO 181
#define SROM4_5GH_MCSPO 189
#define SROM4_CDDPO 197
#define SROM4_STBCPO 198
#define SROM4_BW40PO 199
#define SROM4_BWDUPPO 200
#define SROM4_CRCREV 219
/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
* This is acombined srom for both MIMO and SISO boards, usable in
* the .130 4Kilobit OTP with hardware redundancy.
*/
#define SROM8_SIGN 64
#define SROM8_BREV 65
#define SROM8_BFL0 66
#define SROM8_BFL1 67
#define SROM8_BFL2 68
#define SROM8_BFL3 69
#define SROM8_MACHI 70
#define SROM8_MACMID 71
#define SROM8_MACLO 72
#define SROM8_CCODE 73
#define SROM8_REGREV 74
#define SROM8_LEDBH10 75
#define SROM8_LEDBH32 76
#define SROM8_LEDDC 77
#define SROM8_AA 78
#define SROM8_AG10 79
#define SROM8_AG32 80
#define SROM8_TXRXC 81
#define SROM8_BXARSSI2G 82
#define SROM8_BXARSSI5G 83
#define SROM8_TRI52G 84
#define SROM8_TRI5GHL 85
#define SROM8_RXPO52G 86
#define SROM8_FEM2G 87
#define SROM8_FEM5G 88
#define SROM8_FEM_ANTSWLUT_MASK 0xf800
#define SROM8_FEM_ANTSWLUT_SHIFT 11
#define SROM8_FEM_TR_ISO_MASK 0x0700
#define SROM8_FEM_TR_ISO_SHIFT 8
#define SROM8_FEM_PDET_RANGE_MASK 0x00f8
#define SROM8_FEM_PDET_RANGE_SHIFT 3
#define SROM8_FEM_EXTPA_GAIN_MASK 0x0006
#define SROM8_FEM_EXTPA_GAIN_SHIFT 1
#define SROM8_FEM_TSSIPOS_MASK 0x0001
#define SROM8_FEM_TSSIPOS_SHIFT 0
#define SROM8_THERMAL 89
/* Temp sense related entries */
#define SROM8_MPWR_RAWTS 90
#define SROM8_TS_SLP_OPT_CORRX 91
/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
#define SROM8_FOC_HWIQ_IQSWP 92
/* Temperature delta for PHY calibration */
#define SROM8_PHYCAL_TEMPDELTA 93
/* Per-path offsets & fields */
#define SROM8_PATH0 96
#define SROM8_PATH1 112
#define SROM8_PATH2 128
#define SROM8_PATH3 144
#define SROM8_2G_ITT_MAXP 0
#define SROM8_2G_PA 1
#define SROM8_5G_ITT_MAXP 4
#define SROM8_5GLH_MAXP 5
#define SROM8_5G_PA 6
#define SROM8_5GL_PA 9
#define SROM8_5GH_PA 12
/* All the miriad power offsets */
#define SROM8_2G_CCKPO 160
#define SROM8_2G_OFDMPO 161
#define SROM8_5G_OFDMPO 163
#define SROM8_5GL_OFDMPO 165
#define SROM8_5GH_OFDMPO 167
#define SROM8_2G_MCSPO 169
#define SROM8_5G_MCSPO 177
#define SROM8_5GL_MCSPO 185
#define SROM8_5GH_MCSPO 193
#define SROM8_CDDPO 201
#define SROM8_STBCPO 202
#define SROM8_BW40PO 203
#define SROM8_BWDUPPO 204
/* SISO PA parameters are in the path0 spaces */
#define SROM8_SISO 96
/* Legacy names for SISO PA paramters */
#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
#define SROM8_CRCREV 219
/* SROM REV 9 */
#define SROM9_2GPO_CCKBW20 160
#define SROM9_2GPO_CCKBW20UL 161
#define SROM9_2GPO_LOFDMBW20 162
#define SROM9_2GPO_LOFDMBW20UL 164
#define SROM9_5GLPO_LOFDMBW20 166
#define SROM9_5GLPO_LOFDMBW20UL 168
#define SROM9_5GMPO_LOFDMBW20 170
#define SROM9_5GMPO_LOFDMBW20UL 172
#define SROM9_5GHPO_LOFDMBW20 174
#define SROM9_5GHPO_LOFDMBW20UL 176
#define SROM9_2GPO_MCSBW20 178
#define SROM9_2GPO_MCSBW20UL 180
#define SROM9_2GPO_MCSBW40 182
#define SROM9_5GLPO_MCSBW20 184
#define SROM9_5GLPO_MCSBW20UL 186
#define SROM9_5GLPO_MCSBW40 188
#define SROM9_5GMPO_MCSBW20 190
#define SROM9_5GMPO_MCSBW20UL 192
#define SROM9_5GMPO_MCSBW40 194
#define SROM9_5GHPO_MCSBW20 196
#define SROM9_5GHPO_MCSBW20UL 198
#define SROM9_5GHPO_MCSBW40 200
#define SROM9_PO_MCS32 202
#define SROM9_PO_LOFDM40DUP 203
#define SROM9_REV_CRC 219
typedef struct {
uint8 tssipos; /* TSSI positive slope, 1: positive, 0: negative */
uint8 extpagain; /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */
uint8 pdetrange; /* support 32 combinations of different Pdet dynamic ranges */
uint8 triso; /* TR switch isolation */
uint8 antswctrllut; /* antswctrl lookup table configuration: 32 possible choices */
} srom_fem_t;
#endif /* _bcmsrom_fmt_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmsrom_tbl_h_
#define _bcmsrom_tbl_h_
#include "sbpcmcia.h"
#include "wlioctl.h"
typedef struct {
const char *name;
uint32 revmask;
uint32 flags;
uint16 off;
uint16 mask;
} sromvar_t;
#define SRFL_MORE 1 /* value continues as described by the next entry */
#define SRFL_NOFFS 2 /* value bits can't be all one's */
#define SRFL_PRHEX 4 /* value is in hexdecimal format */
#define SRFL_PRSIGN 8 /* value is in signed decimal format */
#define SRFL_CCODE 0x10 /* value is in country code format */
#define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
#define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
#define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */
/* Assumptions:
* - Ethernet address spans across 3 consective words
*
* Table rules:
* - Add multiple entries next to each other if a value spans across multiple words
* (even multiple fields in the same word) with each entry except the last having
* it's SRFL_MORE bit set.
* - Ethernet address entry does not follow above rule and must not have SRFL_MORE
* bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
* - The last entry's name field must be NULL to indicate the end of the table. Other
* entries must have non-NULL name.
*/
static const sromvar_t pci_sromvars[] = {
{"devid", 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 0xffff},
{"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK},
{"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
{"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
{"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
{"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
{"", 0, 0, SROM_BFL2, 0xffff},
{"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
{"", 0, 0, SROM3_BFL2, 0xffff},
{"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff},
{"", 0, 0, SROM4_BFL1, 0xffff},
{"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff},
{"", 0, 0, SROM5_BFL1, 0xffff},
{"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff},
{"", 0, 0, SROM8_BFL1, 0xffff},
{"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff},
{"", 0, 0, SROM4_BFL3, 0xffff},
{"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff},
{"", 0, 0, SROM5_BFL3, 0xffff},
{"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff},
{"", 0, 0, SROM8_BFL3, 0xffff},
{"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
{"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
{"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff},
{"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff},
{"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff},
{"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff},
{"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
{"regrev", 0x00000008, 0, SROM_OPO, 0xff00},
{"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff},
{"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff},
{"regrev", 0xffffff00, 0, SROM8_REGREV, 0x00ff},
{"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
{"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
{"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
{"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
{"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
{"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
{"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
{"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
{"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
{"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
{"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
{"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
{"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
{"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
{"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
{"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
{"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
{"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
{"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
{"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff},
{"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
{"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
{"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
{"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
{"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
{"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
{"opo", 0x0000000c, 0, SROM_OPO, 0x00ff},
{"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
{"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
{"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff},
{"aa2g", 0xffffff00, 0, SROM8_AA, 0x00ff},
{"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
{"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00},
{"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00},
{"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff},
{"ag1", 0x0000000e, 0, SROM_AG10, 0xff00},
{"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff},
{"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00},
{"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff},
{"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00},
{"ag0", 0xffffff00, 0, SROM8_AG10, 0x00ff},
{"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00},
{"ag2", 0xffffff00, 0, SROM8_AG32, 0x00ff},
{"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00},
{"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
{"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
{"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
{"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
{"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
{"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
{"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
{"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
{"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
{"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00},
{"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
{"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
{"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
{"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
{"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
{"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
{"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
{"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
{"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
{"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
{"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
{"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
{"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
{"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
{"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
{"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
{"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
{"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
{"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
{"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
{"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
{"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
{"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
{"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
{"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
{"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
{"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
{"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
{"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
{"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
{"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
{"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
{"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff},
{"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00},
{"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
{"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00},
{"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
{"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00},
{"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
{"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
{"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
{"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
{"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
{"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
{"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK},
{"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK},
{"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK},
{"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK},
{"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK},
{"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK},
{"tssipos2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK},
{"extpagain2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK},
{"pdetrange2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK},
{"triso2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
{"antswctl2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK},
{"tssipos5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK},
{"extpagain5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK},
{"pdetrange5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK},
{"triso5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
{"antswctl5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK},
{"tempthresh", 0xffffff00, 0, SROM8_THERMAL, 0xff00},
{"tempoffset", 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
{"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
{"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
{"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
{"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
{"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
{"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
{"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
{"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
{"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
{"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
{"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
{"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
{"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
{"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
{"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
{"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
{"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
{"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
{"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
{"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
{"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
{"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
{"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
{"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
{"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff},
{"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff},
{"leddc", 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff},
{"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff},
{"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff},
{"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff},
{"rawtempsense", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff},
{"measpower", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00},
{"tempsense_slope", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
0x00ff},
{"tempcorrx", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00},
{"tempsense_option", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
0x0300},
{"freqoffset_corr", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
0x000f},
{"iqcal_swp_dis", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010},
{"hw_iqcal_en", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020},
{"phycal_tempdelta", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff},
{"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
{"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
{"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
{"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
{"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
{"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
{"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
{"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
{"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
{"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
{"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
{"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
{"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
{"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
{"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
{"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
{"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
{"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
{"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
{"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
{"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
{"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
{"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
{"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
{"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
{"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
{"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
{"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
{"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
{"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
{"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
{"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
{"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
{"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
{"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
{"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
{"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
{"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
{"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
{"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
{"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
{"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
{"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
{"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
{"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
{"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
{"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
{"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
{"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
{"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
{"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
{"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
{"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
{"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
{"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
{"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
{"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
{"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
{"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
{"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
{"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
{"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
{"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
{"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
{"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
{"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
{"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
{"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
{"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
{"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
{"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
{"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
{"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
{"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
{"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
{"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
{"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
{"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
{"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
{"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
{"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
{"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
{"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff},
{"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff},
{"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff},
{"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
{"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff},
{"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff},
{"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff},
{"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
/* power per rate from sromrev 9 */
{"cckbw202gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
{"cckbw20ul2gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
{"legofdmbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20,
0xffff},
{"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
{"legofdmbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL,
0xffff},
{"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
{"legofdmbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20,
0xffff},
{"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
{"legofdmbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL,
0xffff},
{"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
{"legofdmbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20,
0xffff},
{"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
{"legofdmbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL,
0xffff},
{"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
{"legofdmbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20,
0xffff},
{"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
{"legofdmbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL,
0xffff},
{"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
{"mcsbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff},
{"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
{"mcsbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff},
{"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
{"mcsbw402gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff},
{"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
{"mcsbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff},
{"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
{"mcsbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20UL,
0xffff},
{"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
{"mcsbw405glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff},
{"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
{"mcsbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff},
{"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
{"mcsbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20UL,
0xffff},
{"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
{"mcsbw405gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff},
{"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
{"mcsbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff},
{"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
{"mcsbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20UL,
0xffff},
{"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
{"mcsbw405ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff},
{"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
{"mcs32po", 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
{"legofdm40duppo", 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
{NULL, 0, 0, 0, 0}
};
static const sromvar_t perpath_pci_sromvars[] = {
{"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
{"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
{"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
{"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
{"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
{"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
{"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
{"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
{"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
{"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
{"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
{"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
{"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
{"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
{"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
{"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff},
{"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff},
{"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff},
{"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
{"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff},
{"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff},
{"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff},
{"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
{"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
{"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
{"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
{"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
{"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
{"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
{"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
{"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
{"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
{"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
{"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
{"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
{"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff},
{"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff},
{"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
{"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff},
{"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff},
{NULL, 0, 0, 0, 0}
};
#if !(defined(PHY_TYPE_N) && defined(PHY_TYPE_LP))
#define PHY_TYPE_N 4 /* N-Phy value */
#define PHY_TYPE_LP 5 /* LP-Phy value */
#endif /* !(defined(PHY_TYPE_N) && defined(PHY_TYPE_LP)) */
#if !defined(PHY_TYPE_NULL)
#define PHY_TYPE_NULL 0xf /* Invalid Phy value */
#endif /* !defined(PHY_TYPE_NULL) */
typedef struct {
uint16 phy_type;
uint16 bandrange;
uint16 chain;
const char *vars;
} pavars_t;
static const pavars_t pavars[] = {
/* NPHY */
{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"},
{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"},
{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 0,
"pa5glw0a0 pa5glw1a0 pa5glw2a0"},
{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 1,
"pa5glw0a1 pa5glw1a1 pa5glw2a1"},
{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"},
{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"},
{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 0,
"pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 1,
"pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
/* LPPHY */
{PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_2G, 0, "pa0b0 pa0b1 pa0b2"},
{PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GL, 0, "pa1lob0 pa1lob1 pa1lob2"},
{PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GM, 0, "pa1b0 pa1b1 pa1b2"},
{PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GH, 0, "pa1hib0 pa1hib1 pa1hib2"},
{PHY_TYPE_NULL, 0, 0, ""}
};
typedef struct {
uint16 phy_type;
uint16 bandrange;
const char *vars;
} povars_t;
static const povars_t povars[] = {
/* NPHY */
{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G,
"mcs2gpo0 mcs2gpo1 mcs2gpo2 mcs2gpo3 "
"mcs2gpo4 mcs2gpo5 mcs2gpo6 mcs2gpo7"},
{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL,
"mcs5glpo0 mcs5glpo1 mcs5glpo2 mcs5glpo3 "
"mcs5glpo4 mcs5glpo5 mcs5glpo6 mcs5glpo7"},
{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM,
"mcs5gpo0 mcs5gpo1 mcs5gpo2 mcs5gpo3 "
"mcs5gpo4 mcs5gpo5 mcs5gpo6 mcs5gpo7"},
{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH,
"mcs5ghpo0 mcs5ghpo1 mcs5ghpo2 mcs5ghpo3 "
"mcs5ghpo4 mcs5ghpo5 mcs5ghpo6 mcs5ghpo7"},
{PHY_TYPE_NULL, 0, ""}
};
typedef struct {
uint8 tag; /* Broadcom subtag name */
uint8 len; /* Length field of the tuple, note that it includes the
* subtag name (1 byte): 1 + tuple content length
*/
const char *params;
} cis_tuple_t;
#define OTP_RAW (0xff - 1) /* Reserved tuple number for wrvar Raw input */
#define OTP_VERS_1 (0xff - 2) /* CISTPL_VERS_1 */
#define OTP_MANFID (0xff - 3) /* CISTPL_MANFID */
#define OTP_RAW1 (0xff - 4) /* Like RAW, but comes first */
static const cis_tuple_t cis_hnbuvars[] = {
{OTP_RAW1, 0, ""}, /* special case */
{OTP_VERS_1, 0, "smanf sproductname"}, /* special case (non BRCM tuple) */
{OTP_MANFID, 4, "2manfid 2prodid"}, /* special case (non BRCM tuple) */
{HNBU_SROMREV, 2, "1sromrev"},
/* NOTE: subdevid is also written to boardtype.
* Need to write HNBU_BOARDTYPE to change it if it is different.
*/
{HNBU_CHIPID, 11, "2vendid 2devid 2chiprev 2subvendid 2subdevid"},
{HNBU_BOARDREV, 3, "2boardrev"},
{HNBU_PAPARMS, 10, "2pa0b0 2pa0b1 2pa0b2 1pa0itssit 1pa0maxpwr 1opo"},
{HNBU_AA, 3, "1aa2g 1aa5g"},
{HNBU_AA, 3, "1aa0 1aa1"}, /* backward compatibility */
{HNBU_AG, 5, "1ag0 1ag1 1ag2 1ag3"},
{HNBU_BOARDFLAGS, 9, "4boardflags 4boardflags2"},
{HNBU_LEDS, 5, "1ledbh0 1ledbh1 1ledbh2 1ledbh3"},
{HNBU_CCODE, 4, "2ccode 1cctl"},
{HNBU_CCKPO, 3, "2cckpo"},
{HNBU_OFDMPO, 5, "4ofdmpo"},
{HNBU_RDLID, 3, "2rdlid"},
{HNBU_RSSISMBXA2G, 3, "0rssismf2g 0rssismc2g 0rssisav2g 0bxa2g"}, /* special case */
{HNBU_RSSISMBXA5G, 3, "0rssismf5g 0rssismc5g 0rssisav5g 0bxa5g"}, /* special case */
{HNBU_XTALFREQ, 5, "4xtalfreq"},
{HNBU_TRI2G, 2, "1tri2g"},
{HNBU_TRI5G, 4, "1tri5gl 1tri5g 1tri5gh"},
{HNBU_RXPO2G, 2, "1rxpo2g"},
{HNBU_RXPO5G, 2, "1rxpo5g"},
{HNBU_BOARDNUM, 3, "2boardnum"},
{HNBU_MACADDR, 7, "6macaddr"}, /* special case */
{HNBU_RDLSN, 3, "2rdlsn"},
{HNBU_BOARDTYPE, 3, "2boardtype"},
{HNBU_LEDDC, 3, "2leddc"},
{HNBU_RDLRNDIS, 2, "1rdlndis"},
{HNBU_CHAINSWITCH, 5, "1txchain 1rxchain 2antswitch"},
{HNBU_REGREV, 2, "1regrev"},
{HNBU_FEM, 5, "0antswctl2g, 0triso2g, 0pdetrange2g, 0extpagain2g, 0tssipos2g" "0antswctl5g, 0triso5g, 0pdetrange5g, 0extpagain5g, 0tssipos5g"}, /* special case */
{HNBU_PAPARMS_C0, 31, "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 "
"2pa2gw2a0 1maxp5ga0 1itt5ga0 1maxp5gha0 1maxp5gla0 2pa5gw0a0 "
"2pa5gw1a0 2pa5gw2a0 2pa5glw0a0 2pa5glw1a0 2pa5glw2a0 2pa5ghw0a0 "
"2pa5ghw1a0 2pa5ghw2a0"},
{HNBU_PAPARMS_C1, 31, "1maxp2ga1 1itt2ga1 2pa2gw0a1 2pa2gw1a1 "
"2pa2gw2a1 1maxp5ga1 1itt5ga1 1maxp5gha1 1maxp5gla1 2pa5gw0a1 "
"2pa5gw1a1 2pa5gw2a1 2pa5glw0a1 2pa5glw1a1 2pa5glw2a1 2pa5ghw0a1 "
"2pa5ghw1a1 2pa5ghw2a1"},
{HNBU_PO_CCKOFDM, 19, "2cck2gpo 4ofdm2gpo 4ofdm5gpo 4ofdm5glpo "
"4ofdm5ghpo"},
{HNBU_PO_MCS2G, 17, "2mcs2gpo0 2mcs2gpo1 2mcs2gpo2 2mcs2gpo3 "
"2mcs2gpo4 2mcs2gpo5 2mcs2gpo6 2mcs2gpo7"},
{HNBU_PO_MCS5GM, 17, "2mcs5gpo0 2mcs5gpo1 2mcs5gpo2 2mcs5gpo3 "
"2mcs5gpo4 2mcs5gpo5 2mcs5gpo6 2mcs5gpo7"},
{HNBU_PO_MCS5GLH, 33, "2mcs5glpo0 2mcs5glpo1 2mcs5glpo2 2mcs5glpo3 "
"2mcs5glpo4 2mcs5glpo5 2mcs5glpo6 2mcs5glpo7 "
"2mcs5ghpo0 2mcs5ghpo1 2mcs5ghpo2 2mcs5ghpo3 "
"2mcs5ghpo4 2mcs5ghpo5 2mcs5ghpo6 2mcs5ghpo7"},
{HNBU_CCKFILTTYPE, 2, "1cckdigfilttype"},
{HNBU_PO_CDD, 3, "2cddpo"},
{HNBU_PO_STBC, 3, "2stbcpo"},
{HNBU_PO_40M, 3, "2bw40po"},
{HNBU_PO_40MDUP, 3, "2bwduppo"},
{HNBU_RDLRWU, 2, "1rdlrwu"},
{HNBU_WPS, 3, "1wpsgpio 1wpsled"},
{HNBU_USBFS, 2, "1usbfs"},
{HNBU_CUSTOM1, 5, "4customvar1"},
{OTP_RAW, 0, ""}, /* special case */
{HNBU_OFDMPO5G, 13, "4ofdm5gpo 4ofdm5glpo 4ofdm5ghpo"},
{HNBU_USBEPNUM, 3, "2usbepnum"},
{0xFF, 0, ""}
};
#endif /* _bcmsrom_tbl_h_ */

606
drivers/staging/brcm80211/include/bcmutils.h Normal file
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@ -0,0 +1,606 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmutils_h_
#define _bcmutils_h_
#ifdef __cplusplus
extern "C" {
#endif
/* ctype replacement */
#define _BCM_U 0x01 /* upper */
#define _BCM_L 0x02 /* lower */
#define _BCM_D 0x04 /* digit */
#define _BCM_C 0x08 /* cntrl */
#define _BCM_P 0x10 /* punct */
#define _BCM_S 0x20 /* white space (space/lf/tab) */
#define _BCM_X 0x40 /* hex digit */
#define _BCM_SP 0x80 /* hard space (0x20) */
extern const unsigned char bcm_ctype[];
#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
#define bcm_tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c))
#define bcm_toupper(c) (bcm_islower((c)) ? ((c) + 'A' - 'a') : (c))
/* Buffer structure for collecting string-formatted data
* using bcm_bprintf() API.
* Use bcm_binit() to initialize before use
*/
struct bcmstrbuf {
char *buf; /* pointer to current position in origbuf */
unsigned int size; /* current (residual) size in bytes */
char *origbuf; /* unmodified pointer to orignal buffer */
unsigned int origsize; /* unmodified orignal buffer size in bytes */
};
/* ** driver-only section ** */
#include <osl.h>
#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
/*
* Spin at most 'us' microseconds while 'exp' is true.
* Caller should explicitly test 'exp' when this completes
* and take appropriate error action if 'exp' is still true.
*/
#define SPINWAIT(exp, us) { \
uint countdown = (us) + 9; \
while ((exp) && (countdown >= 10)) {\
OSL_DELAY(10); \
countdown -= 10; \
} \
}
/* osl multi-precedence packet queue */
#ifndef PKTQ_LEN_DEFAULT
#define PKTQ_LEN_DEFAULT 128 /* Max 128 packets */
#endif
#ifndef PKTQ_MAX_PREC
#define PKTQ_MAX_PREC 16 /* Maximum precedence levels */
#endif
typedef struct pktq_prec {
void *head; /* first packet to dequeue */
void *tail; /* last packet to dequeue */
uint16 len; /* number of queued packets */
uint16 max; /* maximum number of queued packets */
} pktq_prec_t;
/* multi-priority pkt queue */
struct pktq {
uint16 num_prec; /* number of precedences in use */
uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */
uint16 max; /* total max packets */
uint16 len; /* total number of packets */
/* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */
struct pktq_prec q[PKTQ_MAX_PREC];
};
/* simple, non-priority pkt queue */
struct spktq {
uint16 num_prec; /* number of precedences in use (always 1) */
uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */
uint16 max; /* total max packets */
uint16 len; /* total number of packets */
/* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */
struct pktq_prec q[1];
};
#define PKTQ_PREC_ITER(pq, prec) for (prec = (pq)->num_prec - 1; prec >= 0; prec--)
/* fn(pkt, arg). return true if pkt belongs to if */
typedef bool(*ifpkt_cb_t) (void *, int);
/* forward definition of ether_addr structure used by some function prototypes */
struct ether_addr;
extern int ether_isbcast(const void *ea);
extern int ether_isnulladdr(const void *ea);
/* operations on a specific precedence in packet queue */
#define pktq_psetmax(pq, prec, _max) ((pq)->q[prec].max = (_max))
#define pktq_plen(pq, prec) ((pq)->q[prec].len)
#define pktq_pavail(pq, prec) ((pq)->q[prec].max - (pq)->q[prec].len)
#define pktq_pfull(pq, prec) ((pq)->q[prec].len >= (pq)->q[prec].max)
#define pktq_pempty(pq, prec) ((pq)->q[prec].len == 0)
#define pktq_ppeek(pq, prec) ((pq)->q[prec].head)
#define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail)
extern void *pktq_penq(struct pktq *pq, int prec, void *p);
extern void *pktq_penq_head(struct pktq *pq, int prec, void *p);
extern void *pktq_pdeq(struct pktq *pq, int prec);
extern void *pktq_pdeq_tail(struct pktq *pq, int prec);
/* Empty the queue at particular precedence level */
extern void pktq_pflush(osl_t * osh, struct pktq *pq, int prec,
bool dir, ifpkt_cb_t fn, int arg);
/* Remove a specified packet from its queue */
extern bool pktq_pdel(struct pktq *pq, void *p, int prec);
/* operations on a set of precedences in packet queue */
extern int pktq_mlen(struct pktq *pq, uint prec_bmp);
extern void *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
/* operations on packet queue as a whole */
#define pktq_len(pq) ((int)(pq)->len)
#define pktq_max(pq) ((int)(pq)->max)
#define pktq_avail(pq) ((int)((pq)->max - (pq)->len))
#define pktq_full(pq) ((pq)->len >= (pq)->max)
#define pktq_empty(pq) ((pq)->len == 0)
/* operations for single precedence queues */
#define pktenq(pq, p) pktq_penq(((struct pktq *)pq), 0, (p))
#define pktenq_head(pq, p) pktq_penq_head(((struct pktq *)pq), 0, (p))
#define pktdeq(pq) pktq_pdeq(((struct pktq *)pq), 0)
#define pktdeq_tail(pq) pktq_pdeq_tail(((struct pktq *)pq), 0)
#define pktqinit(pq, len) pktq_init(((struct pktq *)pq), 1, len)
extern void pktq_init(struct pktq *pq, int num_prec, int max_len);
/* prec_out may be NULL if caller is not interested in return value */
extern void *pktq_deq(struct pktq *pq, int *prec_out);
extern void *pktq_deq_tail(struct pktq *pq, int *prec_out);
extern void *pktq_peek(struct pktq *pq, int *prec_out);
extern void *pktq_peek_tail(struct pktq *pq, int *prec_out);
extern void pktq_flush(osl_t * osh, struct pktq *pq, bool dir,
ifpkt_cb_t fn, int arg);
/* externs */
/* packet */
extern uint pktcopy(osl_t * osh, void *p, uint offset, int len,
uchar * buf);
extern uint pktfrombuf(osl_t * osh, void *p, uint offset, int len,
uchar * buf);
extern uint pkttotlen(osl_t * osh, void *p);
extern void *pktlast(osl_t * osh, void *p);
extern uint pktsegcnt(osl_t * osh, void *p);
/* Get priority from a packet and pass it back in scb (or equiv) */
extern uint pktsetprio(void *pkt, bool update_vtag);
#define PKTPRIO_VDSCP 0x100 /* DSCP prio found after VLAN tag */
#define PKTPRIO_VLAN 0x200 /* VLAN prio found */
#define PKTPRIO_UPD 0x400 /* DSCP used to update VLAN prio */
#define PKTPRIO_DSCP 0x800 /* DSCP prio found */
/* string */
extern int BCMROMFN(bcm_atoi) (char *s);
extern ulong BCMROMFN(bcm_strtoul) (char *cp, char **endp, uint base);
extern char *BCMROMFN(bcmstrstr) (char *haystack, char *needle);
extern char *BCMROMFN(bcmstrcat) (char *dest, const char *src);
extern char *BCMROMFN(bcmstrncat) (char *dest, const char *src,
uint size);
extern ulong wchar2ascii(char *abuf, ushort * wbuf, ushort wbuflen,
ulong abuflen);
char *bcmstrtok(char **string, const char *delimiters, char *tokdelim);
int bcmstricmp(const char *s1, const char *s2);
int bcmstrnicmp(const char *s1, const char *s2, int cnt);
/* ethernet address */
extern char *bcm_ether_ntoa(const struct ether_addr *ea, char *buf);
extern int BCMROMFN(bcm_ether_atoe) (char *p, struct ether_addr * ea);
/* ip address */
struct ipv4_addr;
extern char *bcm_ip_ntoa(struct ipv4_addr *ia, char *buf);
/* delay */
extern void bcm_mdelay(uint ms);
/* variable access */
extern char *getvar(char *vars, const char *name);
extern int getintvar(char *vars, const char *name);
extern int getintvararray(char *vars, const char *name, uint8 index);
extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
#ifdef BCMDBG
extern void prpkt(const char *msg, osl_t * osh, void *p0);
#endif /* BCMDBG */
#define bcm_perf_enable()
#define bcmstats(fmt)
#define bcmlog(fmt, a1, a2)
#define bcmdumplog(buf, size) *buf = '\0'
#define bcmdumplogent(buf, idx) -1
#define bcmtslog(tstamp, fmt, a1, a2)
#define bcmprinttslogs()
#define bcmprinttstamp(us)
extern char *bcm_nvram_vars(uint * length);
extern int bcm_nvram_cache(void *sih);
/* Support for sharing code across in-driver iovar implementations.
* The intent is that a driver use this structure to map iovar names
* to its (private) iovar identifiers, and the lookup function to
* find the entry. Macros are provided to map ids and get/set actions
* into a single number space for a switch statement.
*/
/* iovar structure */
typedef struct bcm_iovar {
const char *name; /* name for lookup and display */
uint16 varid; /* id for switch */
uint16 flags; /* driver-specific flag bits */
uint16 type; /* base type of argument */
uint16 minlen; /* min length for buffer vars */
} bcm_iovar_t;
/* varid definitions are per-driver, may use these get/set bits */
/* IOVar action bits for id mapping */
#define IOV_GET 0 /* Get an iovar */
#define IOV_SET 1 /* Set an iovar */
/* Varid to actionid mapping */
#define IOV_GVAL(id) ((id)*2)
#define IOV_SVAL(id) (((id)*2)+IOV_SET)
#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
#define IOV_ID(actionid) (actionid >> 1)
/* flags are per-driver based on driver attributes */
extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t * table,
const char *name);
extern int bcm_iovar_lencheck(const bcm_iovar_t * table, void *arg,
int len, bool set);
#if defined(BCMDBG)
extern int bcm_format_ssid(char *buf, const uchar ssid[],
uint ssid_len);
#endif
/* Base type definitions */
#define IOVT_VOID 0 /* no value (implictly set only) */
#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
#define IOVT_INT8 2 /* integer values are range-checked */
#define IOVT_UINT8 3 /* unsigned int 8 bits */
#define IOVT_INT16 4 /* int 16 bits */
#define IOVT_UINT16 5 /* unsigned int 16 bits */
#define IOVT_INT32 6 /* int 32 bits */
#define IOVT_UINT32 7 /* unsigned int 32 bits */
#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
#define BCM_IOVT_VALID(type) (((unsigned int)(type)) <= IOVT_BUFFER)
/* Initializer for IOV type strings */
#define BCM_IOV_TYPE_INIT { \
"void", \
"bool", \
"int8", \
"uint8", \
"int16", \
"uint16", \
"int32", \
"uint32", \
"buffer", \
"" }
#define BCM_IOVT_IS_INT(type) (\
(type == IOVT_BOOL) || \
(type == IOVT_INT8) || \
(type == IOVT_UINT8) || \
(type == IOVT_INT16) || \
(type == IOVT_UINT16) || \
(type == IOVT_INT32) || \
(type == IOVT_UINT32))
/* ** driver/apps-shared section ** */
#define BCME_STRLEN 64 /* Max string length for BCM errors */
#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
/*
* error codes could be added but the defined ones shouldn't be changed/deleted
* these error codes are exposed to the user code
* when ever a new error code is added to this list
* please update errorstring table with the related error string and
* update osl files with os specific errorcode map
*/
#define BCME_OK 0 /* Success */
#define BCME_ERROR -1 /* Error generic */
#define BCME_BADARG -2 /* Bad Argument */
#define BCME_BADOPTION -3 /* Bad option */
#define BCME_NOTUP -4 /* Not up */
#define BCME_NOTDOWN -5 /* Not down */
#define BCME_NOTAP -6 /* Not AP */
#define BCME_NOTSTA -7 /* Not STA */
#define BCME_BADKEYIDX -8 /* BAD Key Index */
#define BCME_RADIOOFF -9 /* Radio Off */
#define BCME_NOTBANDLOCKED -10 /* Not band locked */
#define BCME_NOCLK -11 /* No Clock */
#define BCME_BADRATESET -12 /* BAD Rate valueset */
#define BCME_BADBAND -13 /* BAD Band */
#define BCME_BUFTOOSHORT -14 /* Buffer too short */
#define BCME_BUFTOOLONG -15 /* Buffer too long */
#define BCME_BUSY -16 /* Busy */
#define BCME_NOTASSOCIATED -17 /* Not Associated */
#define BCME_BADSSIDLEN -18 /* Bad SSID len */
#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
#define BCME_BADCHAN -20 /* Bad Channel */
#define BCME_BADADDR -21 /* Bad Address */
#define BCME_NORESOURCE -22 /* Not Enough Resources */
#define BCME_UNSUPPORTED -23 /* Unsupported */
#define BCME_BADLEN -24 /* Bad length */
#define BCME_NOTREADY -25 /* Not Ready */
#define BCME_EPERM -26 /* Not Permitted */
#define BCME_NOMEM -27 /* No Memory */
#define BCME_ASSOCIATED -28 /* Associated */
#define BCME_RANGE -29 /* Not In Range */
#define BCME_NOTFOUND -30 /* Not Found */
#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
#define BCME_VERSION -37 /* Incorrect version */
#define BCME_TXFAIL -38 /* TX failure */
#define BCME_RXFAIL -39 /* RX failure */
#define BCME_NODEVICE -40 /* Device not present */
#define BCME_NMODE_DISABLED -41 /* NMODE disabled */
#define BCME_NONRESIDENT -42 /* access to nonresident overlay */
#define BCME_LAST BCME_NONRESIDENT
/* These are collection of BCME Error strings */
#define BCMERRSTRINGTABLE { \
"OK", \
"Undefined error", \
"Bad Argument", \
"Bad Option", \
"Not up", \
"Not down", \
"Not AP", \
"Not STA", \
"Bad Key Index", \
"Radio Off", \
"Not band locked", \
"No clock", \
"Bad Rate valueset", \
"Bad Band", \
"Buffer too short", \
"Buffer too long", \
"Busy", \
"Not Associated", \
"Bad SSID len", \
"Out of Range Channel", \
"Bad Channel", \
"Bad Address", \
"Not Enough Resources", \
"Unsupported", \
"Bad length", \
"Not Ready", \
"Not Permitted", \
"No Memory", \
"Associated", \
"Not In Range", \
"Not Found", \
"WME Not Enabled", \
"TSPEC Not Found", \
"ACM Not Supported", \
"Not WME Association", \
"SDIO Bus Error", \
"Dongle Not Accessible", \
"Incorrect version", \
"TX Failure", \
"RX Failure", \
"Device Not Present", \
"NMODE Disabled", \
"Nonresident overlay access", \
}
#ifndef ABS
#define ABS(a) (((a) < 0)?-(a):(a))
#endif /* ABS */
#ifndef MIN
#define MIN(a, b) (((a) < (b))?(a):(b))
#endif /* MIN */
#ifndef MAX
#define MAX(a, b) (((a) > (b))?(a):(b))
#endif /* MAX */
#define CEIL(x, y) (((x) + ((y)-1)) / (y))
#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
#define ALIGN_ADDR(addr, boundary) (void *)(((uintptr)(addr) + (boundary) - 1) \
& ~((boundary) - 1))
#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
#define VALID_MASK(mask) !((mask) & ((mask) + 1))
#ifndef OFFSETOF
#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
#endif /* OFFSETOF */
#ifndef ARRAYSIZE
#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
#endif
/* bit map related macros */
#ifndef setbit
#ifndef NBBY /* the BSD family defines NBBY */
#define NBBY 8 /* 8 bits per byte */
#endif /* #ifndef NBBY */
#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
#define isset(a, i) (((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
#define isclr(a, i) ((((const uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
#endif /* setbit */
#define NBITS(type) (sizeof(type) * 8)
#define NBITVAL(nbits) (1 << (nbits))
#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
#define NBITMASK(nbits) MAXBITVAL(nbits)
#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
/* basic mux operation - can be optimized on several architectures */
#define MUX(pred, true, false) ((pred) ? (true) : (false))
/* modulo inc/dec - assumes x E [0, bound - 1] */
#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
/* modulo inc/dec, bound = 2^k */
#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
/* modulo add/sub - assumes x, y E [0, bound - 1] */
#define MODADD(x, y, bound) \
MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
#define MODSUB(x, y, bound) \
MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
/* module add/sub, bound = 2^k */
#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
/* crc defines */
#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
/* bcm_format_flags() bit description structure */
typedef struct bcm_bit_desc {
uint32 bit;
const char *name;
} bcm_bit_desc_t;
/* tag_ID/length/value_buffer tuple */
typedef struct bcm_tlv {
uint8 id;
uint8 len;
uint8 data[1];
} bcm_tlv_t;
/* Check that bcm_tlv_t fits into the given buflen */
#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
/* buffer length for ethernet address from bcm_ether_ntoa() */
#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
/* crypto utility function */
/* 128-bit xor: *dst = *src1 xor *src2. dst1, src1 and src2 may have any alignment */
static INLINE void
xor_128bit_block(const uint8 * src1, const uint8 * src2, uint8 * dst) {
if (
#ifdef __i386__
1 ||
#endif
(((uintptr) src1 | (uintptr) src2 | (uintptr) dst) &
3) == 0) {
/* ARM CM3 rel time: 1229 (727 if alignment check could be omitted) */
/* x86 supports unaligned. This version runs 6x-9x faster on x86. */
((uint32 *) dst)[0] =
((const uint32 *)src1)[0] ^ ((const uint32 *)
src2)[0];
((uint32 *) dst)[1] =
((const uint32 *)src1)[1] ^ ((const uint32 *)
src2)[1];
((uint32 *) dst)[2] =
((const uint32 *)src1)[2] ^ ((const uint32 *)
src2)[2];
((uint32 *) dst)[3] =
((const uint32 *)src1)[3] ^ ((const uint32 *)
src2)[3];
} else {
/* ARM CM3 rel time: 4668 (4191 if alignment check could be omitted) */
int k;
for (k = 0; k < 16; k++)
dst[k] = src1[k] ^ src2[k];
}
}
/* externs */
/* crc */
extern uint8 BCMROMFN(hndcrc8) (uint8 * p, uint nbytes, uint8 crc);
extern uint16 BCMROMFN(hndcrc16) (uint8 * p, uint nbytes, uint16 crc);
/* format/print */
#if defined(BCMDBG)
extern int bcm_format_flags(const bcm_bit_desc_t * bd, uint32 flags,
char *buf, int len);
extern int bcm_format_hex(char *str, const void *bytes, int len);
#endif
#ifdef BCMDBG
extern void deadbeef(void *p, uint len);
#endif
extern const char *bcm_crypto_algo_name(uint algo);
extern char *bcm_chipname(uint chipid, char *buf, uint len);
extern char *bcm_brev_str(uint32 brev, char *buf);
extern void printbig(char *buf);
extern void prhex(const char *msg, uchar * buf, uint len);
/* IE parsing */
extern bcm_tlv_t *BCMROMFN(bcm_next_tlv) (bcm_tlv_t * elt, int *buflen);
extern bcm_tlv_t *BCMROMFN(bcm_parse_tlvs) (void *buf, int buflen,
uint key);
extern bcm_tlv_t *BCMROMFN(bcm_parse_ordered_tlvs) (void *buf,
int buflen,
uint key);
/* bcmerror */
extern const char *bcmerrorstr(int bcmerror);
/* multi-bool data type: set of bools, mbool is true if any is set */
typedef uint32 mbool;
#define mboolset(mb, bit) ((mb) |= (bit)) /* set one bool */
#define mboolclr(mb, bit) ((mb) &= ~(bit)) /* clear one bool */
#define mboolisset(mb, bit) (((mb) & (bit)) != 0) /* TRUE if one bool is set */
#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
/* power conversion */
extern uint16 BCMROMFN(bcm_qdbm_to_mw) (uint8 qdbm);
extern uint8 BCMROMFN(bcm_mw_to_qdbm) (uint16 mw);
/* generic datastruct to help dump routines */
struct fielddesc {
const char *nameandfmt;
uint32 offset;
uint32 len;
};
extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
extern void bcm_inc_bytes(uchar * num, int num_bytes, uint8 amount);
extern int bcm_cmp_bytes(uchar * arg1, uchar * arg2, uint8 nbytes);
extern void bcm_print_bytes(char *name, const uchar * cdata, int len);
typedef uint32(*bcmutl_rdreg_rtn) (void *arg0, uint arg1,
uint32 offset);
extern uint bcmdumpfields(bcmutl_rdreg_rtn func_ptr, void *arg0,
uint arg1, struct fielddesc *str, char *buf,
uint32 bufsize);
extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf,
uint len);
extern uint BCMROMFN(bcm_bitcount) (uint8 * bitmap, uint bytelength);
#ifdef __cplusplus
}
#endif
#endif /* _bcmutils_h_ */

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drivers/staging/brcm80211/include/bcmwifi.h Normal file
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _bcmwifi_h_
#define _bcmwifi_h_
/* A chanspec holds the channel number, band, bandwidth and control sideband */
typedef uint16 chanspec_t;
/* channel defines */
#define CH_UPPER_SB 0x01
#define CH_LOWER_SB 0x02
#define CH_EWA_VALID 0x04
#define CH_20MHZ_APART 4
#define CH_10MHZ_APART 2
#define CH_5MHZ_APART 1 /* 2G band channels are 5 Mhz apart */
#define CH_MAX_2G_CHANNEL 14 /* Max channel in 2G band */
#define WLC_MAX_2G_CHANNEL CH_MAX_2G_CHANNEL /* legacy define */
#define MAXCHANNEL 224 /* max # supported channels. The max channel no is 216,
* this is that + 1 rounded up to a multiple of NBBY (8).
* DO NOT MAKE it > 255: channels are uint8's all over
*/
#define WL_CHANSPEC_CHAN_MASK 0x00ff
#define WL_CHANSPEC_CHAN_SHIFT 0
#define WL_CHANSPEC_CTL_SB_MASK 0x0300
#define WL_CHANSPEC_CTL_SB_SHIFT 8
#define WL_CHANSPEC_CTL_SB_LOWER 0x0100
#define WL_CHANSPEC_CTL_SB_UPPER 0x0200
#define WL_CHANSPEC_CTL_SB_NONE 0x0300
#define WL_CHANSPEC_BW_MASK 0x0C00
#define WL_CHANSPEC_BW_SHIFT 10
#define WL_CHANSPEC_BW_10 0x0400
#define WL_CHANSPEC_BW_20 0x0800
#define WL_CHANSPEC_BW_40 0x0C00
#define WL_CHANSPEC_BAND_MASK 0xf000
#define WL_CHANSPEC_BAND_SHIFT 12
#define WL_CHANSPEC_BAND_5G 0x1000
#define WL_CHANSPEC_BAND_2G 0x2000
#define INVCHANSPEC 255
/* used to calculate the chan_freq = chan_factor * 500Mhz + 5 * chan_number */
#define WF_CHAN_FACTOR_2_4_G 4814 /* 2.4 GHz band, 2407 MHz */
#define WF_CHAN_FACTOR_5_G 10000 /* 5 GHz band, 5000 MHz */
#define WF_CHAN_FACTOR_4_G 8000 /* 4.9 GHz band for Japan */
/* channel defines */
#define LOWER_20_SB(channel) (((channel) > CH_10MHZ_APART) ? ((channel) - CH_10MHZ_APART) : 0)
#define UPPER_20_SB(channel) (((channel) < (MAXCHANNEL - CH_10MHZ_APART)) ? \
((channel) + CH_10MHZ_APART) : 0)
#define CHSPEC_WLCBANDUNIT(chspec) (CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : BAND_2G_INDEX)
#define CH20MHZ_CHSPEC(channel) (chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_20 | \
WL_CHANSPEC_CTL_SB_NONE | (((channel) <= CH_MAX_2G_CHANNEL) ? \
WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
#define NEXT_20MHZ_CHAN(channel) (((channel) < (MAXCHANNEL - CH_20MHZ_APART)) ? \
((channel) + CH_20MHZ_APART) : 0)
#define CH40MHZ_CHSPEC(channel, ctlsb) (chanspec_t) \
((channel) | (ctlsb) | WL_CHANSPEC_BW_40 | \
((channel) <= CH_MAX_2G_CHANNEL ? WL_CHANSPEC_BAND_2G : \
WL_CHANSPEC_BAND_5G))
#define CHSPEC_CHANNEL(chspec) ((uint8)((chspec) & WL_CHANSPEC_CHAN_MASK))
#define CHSPEC_BAND(chspec) ((chspec) & WL_CHANSPEC_BAND_MASK)
#ifdef WL11N_20MHZONLY
#define CHSPEC_CTL_SB(chspec) WL_CHANSPEC_CTL_SB_NONE
#define CHSPEC_BW(chspec) WL_CHANSPEC_BW_20
#define CHSPEC_IS10(chspec) 0
#define CHSPEC_IS20(chspec) 1
#ifndef CHSPEC_IS40
#define CHSPEC_IS40(chspec) 0
#endif
#else /* !WL11N_20MHZONLY */
#define CHSPEC_CTL_SB(chspec) ((chspec) & WL_CHANSPEC_CTL_SB_MASK)
#define CHSPEC_BW(chspec) ((chspec) & WL_CHANSPEC_BW_MASK)
#define CHSPEC_IS10(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
#define CHSPEC_IS20(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20)
#ifndef CHSPEC_IS40
#define CHSPEC_IS40(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40)
#endif
#endif /* !WL11N_20MHZONLY */
#define CHSPEC_IS5G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G)
#define CHSPEC_IS2G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G)
#define CHSPEC_SB_NONE(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_NONE)
#define CHSPEC_SB_UPPER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER)
#define CHSPEC_SB_LOWER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER)
#define CHSPEC_CTL_CHAN(chspec) ((CHSPEC_SB_LOWER(chspec)) ? \
(LOWER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))) : \
(UPPER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))))
#define CHSPEC2WLC_BAND(chspec) (CHSPEC_IS5G(chspec) ? WLC_BAND_5G : WLC_BAND_2G)
#define CHANSPEC_STR_LEN 8
/* defined rate in 500kbps */
#define WLC_MAXRATE 108 /* in 500kbps units */
#define WLC_RATE_1M 2 /* in 500kbps units */
#define WLC_RATE_2M 4 /* in 500kbps units */
#define WLC_RATE_5M5 11 /* in 500kbps units */
#define WLC_RATE_11M 22 /* in 500kbps units */
#define WLC_RATE_6M 12 /* in 500kbps units */
#define WLC_RATE_9M 18 /* in 500kbps units */
#define WLC_RATE_12M 24 /* in 500kbps units */
#define WLC_RATE_18M 36 /* in 500kbps units */
#define WLC_RATE_24M 48 /* in 500kbps units */
#define WLC_RATE_36M 72 /* in 500kbps units */
#define WLC_RATE_48M 96 /* in 500kbps units */
#define WLC_RATE_54M 108 /* in 500kbps units */
#define WLC_2G_25MHZ_OFFSET 5 /* 2.4GHz band channel offset */
/*
* Convert chanspec to ascii string
* @param chspec chanspec format
* @param buf ascii string of chanspec
* @return pointer to buf with room for at least CHANSPEC_STR_LEN bytes
*/
extern char *wf_chspec_ntoa(chanspec_t chspec, char *buf);
/*
* Convert ascii string to chanspec
* @param a pointer to input string
* @return >= 0 if successful or 0 otherwise
*/
extern chanspec_t wf_chspec_aton(char *a);
/*
* Verify the chanspec is using a legal set of parameters, i.e. that the
* chanspec specified a band, bw, ctl_sb and channel and that the
* combination could be legal given any set of circumstances.
* RETURNS: TRUE is the chanspec is malformed, false if it looks good.
*/
extern bool wf_chspec_malformed(chanspec_t chanspec);
/*
* This function returns the channel number that control traffic is being sent on, for legacy
* channels this is just the channel number, for 40MHZ channels it is the upper or lowre 20MHZ
* sideband depending on the chanspec selected
*/
extern uint8 wf_chspec_ctlchan(chanspec_t chspec);
/*
* This function returns the chanspec that control traffic is being sent on, for legacy
* channels this is just the chanspec, for 40MHZ channels it is the upper or lowre 20MHZ
* sideband depending on the chanspec selected
*/
extern chanspec_t wf_chspec_ctlchspec(chanspec_t chspec);
/*
* Return the channel number for a given frequency and base frequency.
* The returned channel number is relative to the given base frequency.
* If the given base frequency is zero, a base frequency of 5 GHz is assumed for
* frequencies from 5 - 6 GHz, and 2.407 GHz is assumed for 2.4 - 2.5 GHz.
*
* Frequency is specified in MHz.
* The base frequency is specified as (start_factor * 500 kHz).
* Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
* 2.4 GHz and 5 GHz bands.
*
* The returned channel will be in the range [1, 14] in the 2.4 GHz band
* and [0, 200] otherwise.
* -1 is returned if the start_factor is WF_CHAN_FACTOR_2_4_G and the
* frequency is not a 2.4 GHz channel, or if the frequency is not and even
* multiple of 5 MHz from the base frequency to the base plus 1 GHz.
*
* Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
*/
extern int wf_mhz2channel(uint freq, uint start_factor);
/*
* Return the center frequency in MHz of the given channel and base frequency.
* The channel number is interpreted relative to the given base frequency.
*
* The valid channel range is [1, 14] in the 2.4 GHz band and [0, 200] otherwise.
* The base frequency is specified as (start_factor * 500 kHz).
* Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
* 2.4 GHz and 5 GHz bands.
* The channel range of [1, 14] is only checked for a start_factor of
* WF_CHAN_FACTOR_2_4_G (4814).
* Odd start_factors produce channels on .5 MHz boundaries, in which case
* the answer is rounded down to an integral MHz.
* -1 is returned for an out of range channel.
*
* Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
*/
extern int wf_channel2mhz(uint channel, uint start_factor);
#endif /* _bcmwifi_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BCMWPA_H_
#define _BCMWPA_H_
#include <proto/wpa.h>
#include <proto/802.11.h>
#include <wlioctl.h>
/* Field sizes for WPA key hierarchy */
#define WPA_MIC_KEY_LEN 16
#define WPA_ENCR_KEY_LEN 16
#define WPA_TEMP_ENCR_KEY_LEN 16
#define WPA_TEMP_TX_KEY_LEN 8
#define WPA_TEMP_RX_KEY_LEN 8
#define PMK_LEN 32
#define TKIP_PTK_LEN 64
#define TKIP_TK_LEN 32
#define AES_PTK_LEN 48
#define AES_TK_LEN 16
/* limits for pre-shared key lengths */
#define WPA_MIN_PSK_LEN 8
#define WPA_MAX_PSK_LEN 64
#define WLC_SW_KEYS(wlc, bsscfg) ((((wlc)->wsec_swkeys) || \
((bsscfg)->wsec & WSEC_SWFLAG)))
#define WSEC_WEP_ENABLED(wsec) ((wsec) & WEP_ENABLED)
#define WSEC_TKIP_ENABLED(wsec) ((wsec) & TKIP_ENABLED)
#define WSEC_AES_ENABLED(wsec) ((wsec) & AES_ENABLED)
#define WSEC_ENABLED(wsec) ((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))
#define WSEC_SES_OW_ENABLED(wsec) ((wsec) & SES_OW_ENABLED)
#define IS_WPA_AUTH(auth) ((auth) == WPA_AUTH_NONE || \
(auth) == WPA_AUTH_UNSPECIFIED || \
(auth) == WPA_AUTH_PSK)
#define INCLUDES_WPA_AUTH(auth) \
((auth) & (WPA_AUTH_NONE | WPA_AUTH_UNSPECIFIED | WPA_AUTH_PSK))
#define IS_WPA2_AUTH(auth) ((auth) == WPA2_AUTH_UNSPECIFIED || \
(auth) == WPA2_AUTH_PSK)(
#define INCLUDES_WPA2_AUTH(auth) \
((auth) & (WPA2_AUTH_UNSPECIFIED | \
WPA2_AUTH_PSK))
#define IS_WPA_AKM(akm) ((akm) == RSN_AKM_NONE || \
(akm) == RSN_AKM_UNSPECIFIED || \
(akm) == RSN_AKM_PSK)
#define IS_WPA2_AKM(akm) ((akm) == RSN_AKM_UNSPECIFIED || \
(akm) == RSN_AKM_PSK)
#define MAX_ARRAY 1
#define MIN_ARRAY 0
/* convert wsec to WPA mcast cipher. algo is needed only when WEP is enabled. */
#define WPA_MCAST_CIPHER(wsec, algo) (WSEC_WEP_ENABLED(wsec) ? \
((algo) == CRYPTO_ALGO_WEP128 ? WPA_CIPHER_WEP_104 : WPA_CIPHER_WEP_40) : \
WSEC_TKIP_ENABLED(wsec) ? WPA_CIPHER_TKIP : \
WSEC_AES_ENABLED(wsec) ? WPA_CIPHER_AES_CCM : \
WPA_CIPHER_NONE)
/* Look for a WPA IE; return it's address if found, NULL otherwise */
extern wpa_ie_fixed_t *BCMROMFN(bcm_find_wpaie) (uint8 * parse, uint len);
/* Check whether the given IE looks like WFA IE with the specific type. */
extern bool bcm_is_wfa_ie(uint8 * ie, uint8 ** tlvs, uint * tlvs_len,
uint8 type);
/* Check whether pointed-to IE looks like WPA. */
#define bcm_is_wpa_ie(ie, tlvs, len) bcm_is_wfa_ie(ie, tlvs, len, WFA_OUI_TYPE_WPA)
#endif /* _BCMWPA_H_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BITFUNCS_H
#define _BITFUNCS_H
#include <typedefs.h>
/* local prototypes */
static INLINE uint32 find_msbit(uint32 x);
/*
* find_msbit: returns index of most significant set bit in x, with index
* range defined as 0-31. NOTE: returns zero if input is zero.
*/
#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
/*
* Implementation for Pentium processors and gcc. Note that this
* instruction is actually very slow on some processors (e.g., family 5,
* model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
* implementation instead.
*/
static INLINE uint32 find_msbit(uint32 x)
{
uint msbit;
__asm__("bsrl %1,%0":"=r"(msbit)
: "r"(x));
return msbit;
}
#else /* !USE_PENTIUM_BSR || !__GNUC__ */
/*
* Generic Implementation
*/
#define DB_POW_MASK16 0xffff0000
#define DB_POW_MASK8 0x0000ff00
#define DB_POW_MASK4 0x000000f0
#define DB_POW_MASK2 0x0000000c
#define DB_POW_MASK1 0x00000002
static INLINE uint32 find_msbit(uint32 x)
{
uint32 temp_x = x;
uint msbit = 0;
if (temp_x & DB_POW_MASK16) {
temp_x >>= 16;
msbit = 16;
}
if (temp_x & DB_POW_MASK8) {
temp_x >>= 8;
msbit += 8;
}
if (temp_x & DB_POW_MASK4) {
temp_x >>= 4;
msbit += 4;
}
if (temp_x & DB_POW_MASK2) {
temp_x >>= 2;
msbit += 2;
}
if (temp_x & DB_POW_MASK1) {
msbit += 1;
}
return (msbit);
}
#endif /* USE_PENTIUM_BSR && __GNUC__ */
#endif /* _BITFUNCS_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __DBUS_H__
#define __DBUS_H__
#include "typedefs.h"
#ifdef BCMDBG
#define DBUSERR(args) do { if (net_ratelimit()) printf args; } while (0)
#define DBUSTRACE(args)
#define DBUSDBGLOCK(args)
#else
#define DBUSTRACE(args)
#define DBUSERR(args)
#define DBUSDBGLOCK(args)
#endif
enum {
DBUS_OK = 0,
DBUS_ERR = -200,
DBUS_ERR_TIMEOUT,
DBUS_ERR_DISCONNECT,
DBUS_ERR_NODEVICE,
DBUS_ERR_UNSUPPORTED,
DBUS_ERR_PENDING,
DBUS_ERR_NOMEM,
DBUS_ERR_TXFAIL,
DBUS_ERR_TXTIMEOUT,
DBUS_ERR_TXDROP,
DBUS_ERR_RXFAIL,
DBUS_ERR_RXDROP,
DBUS_ERR_TXCTLFAIL,
DBUS_ERR_RXCTLFAIL,
DBUS_ERR_REG_PARAM,
DBUS_STATUS_CANCELLED
};
#define ERR_CBMASK_TXFAIL 0x00000001
#define ERR_CBMASK_RXFAIL 0x00000002
#define ERR_CBMASK_ALL 0xFFFFFFFF
#define DBUS_CBCTL_WRITE 0
#define DBUS_CBCTL_READ 1
#define DBUS_TX_RETRY_LIMIT 3 /* retries for failed txirb */
#define DBUS_TX_TIMEOUT_INTERVAL 250 /* timeout for txirb complete, in ms */
#define DBUS_BUFFER_SIZE_TX 5000
#define DBUS_BUFFER_SIZE_RX 5000
#define DBUS_BUFFER_SIZE_TX_NOAGG 2048
#define DBUS_BUFFER_SIZE_RX_NOAGG 2048
/* DBUS types */
enum {
DBUS_USB,
DBUS_SDIO,
DBUS_SPI,
DBUS_UNKNOWN
};
enum dbus_state {
DBUS_STATE_DL_PENDING,
DBUS_STATE_DL_DONE,
DBUS_STATE_UP,
DBUS_STATE_DOWN,
DBUS_STATE_PNP_FWDL,
DBUS_STATE_DISCONNECT
};
enum dbus_pnp_state {
DBUS_PNP_DISCONNECT,
DBUS_PNP_SLEEP,
DBUS_PNP_RESUME
};
typedef enum _DEVICE_SPEED {
INVALID_SPEED = -1,
LOW_SPEED = 1, /* USB 1.1: 1.5 Mbps */
FULL_SPEED, /* USB 1.1: 12 Mbps */
HIGH_SPEED, /* USB 2.0: 480 Mbps */
SUPER_SPEED, /* USB 3.0: 4.8 Gbps */
} DEVICE_SPEED;
typedef struct {
int bustype;
int vid;
int pid;
int devid;
int chiprev; /* chip revsion number */
int mtu;
int nchan; /* Data Channels */
} dbus_attrib_t;
/* FIX: Account for errors related to DBUS;
* Let upper layer account for packets/bytes
*/
typedef struct {
uint32 rx_errors;
uint32 tx_errors;
uint32 rx_dropped;
uint32 tx_dropped;
} dbus_stats_t;
/*
* Configurable BUS parameters
*/
typedef struct {
bool rxctl_deferrespok;
} dbus_config_t;
struct dbus_callbacks;
struct exec_parms;
typedef void *(*probe_cb_t) (void *arg, const char *desc, uint32 bustype,
uint32 hdrlen);
typedef void (*disconnect_cb_t) (void *arg);
typedef void *(*exec_cb_t) (struct exec_parms * args);
/* Client callbacks registered during dbus_attach() */
typedef struct dbus_callbacks {
void (*send_complete) (void *cbarg, void *info, int status);
void (*recv_buf) (void *cbarg, uint8 * buf, int len);
void (*recv_pkt) (void *cbarg, void *pkt);
void (*txflowcontrol) (void *cbarg, bool onoff);
void (*errhandler) (void *cbarg, int err);
void (*ctl_complete) (void *cbarg, int type, int status);
void (*state_change) (void *cbarg, int state);
void *(*pktget) (void *cbarg, uint len, bool send);
void (*pktfree) (void *cbarg, void *p, bool send);
} dbus_callbacks_t;
struct dbus_pub;
struct bcmstrbuf;
struct dbus_irb;
struct dbus_irb_rx;
struct dbus_irb_tx;
struct dbus_intf_callbacks;
typedef struct {
void *(*attach) (struct dbus_pub * pub, void *cbarg,
struct dbus_intf_callbacks * cbs);
void (*detach) (struct dbus_pub * pub, void *bus);
int (*up) (void *bus);
int (*down) (void *bus);
int (*send_irb) (void *bus, struct dbus_irb_tx * txirb);
int (*recv_irb) (void *bus, struct dbus_irb_rx * rxirb);
int (*cancel_irb) (void *bus, struct dbus_irb_tx * txirb);
int (*send_ctl) (void *bus, uint8 * buf, int len);
int (*recv_ctl) (void *bus, uint8 * buf, int len);
int (*get_stats) (void *bus, dbus_stats_t * stats);
int (*get_attrib) (void *bus, dbus_attrib_t * attrib);
int (*pnp) (void *bus, int event);
int (*remove) (void *bus);
int (*resume) (void *bus);
int (*suspend) (void *bus);
int (*stop) (void *bus);
int (*reset) (void *bus);
/* Access to bus buffers directly */
void *(*pktget) (void *bus, int len);
void (*pktfree) (void *bus, void *pkt);
int (*iovar_op) (void *bus, const char *name, void *params, int plen,
void *arg, int len, bool set);
void (*dump) (void *bus, struct bcmstrbuf * strbuf);
int (*set_config) (void *bus, dbus_config_t * config);
int (*get_config) (void *bus, dbus_config_t * config);
bool(*device_exists) (void *bus);
bool(*dlneeded) (void *bus);
int (*dlstart) (void *bus, uint8 * fw, int len);
int (*dlrun) (void *bus);
bool(*recv_needed) (void *bus);
void *(*exec_rxlock) (void *bus, exec_cb_t func,
struct exec_parms * args);
void *(*exec_txlock) (void *bus, exec_cb_t func,
struct exec_parms * args);
int (*tx_timer_init) (void *bus);
int (*tx_timer_start) (void *bus, uint timeout);
int (*tx_timer_stop) (void *bus);
int (*sched_dpc) (void *bus);
int (*lock) (void *bus);
int (*unlock) (void *bus);
int (*sched_probe_cb) (void *bus);
int (*shutdown) (void *bus);
int (*recv_stop) (void *bus);
int (*recv_resume) (void *bus);
/* Add from the bottom */
} dbus_intf_t;
typedef struct dbus_pub {
struct osl_info *osh;
dbus_stats_t stats;
dbus_attrib_t attrib;
enum dbus_state busstate;
DEVICE_SPEED device_speed;
int ntxq, nrxq, rxsize;
void *bus;
struct shared_info *sh;
} dbus_pub_t;
#define BUS_INFO(bus, type) (((type *) bus)->pub->bus)
/*
* Public Bus Function Interface
*/
extern int dbus_register(int vid, int pid, probe_cb_t prcb,
disconnect_cb_t discb, void *prarg, void *param1,
void *param2);
extern int dbus_deregister(void);
extern const dbus_pub_t *dbus_attach(struct osl_info *osh, int rxsize, int nrxq,
int ntxq, void *cbarg,
dbus_callbacks_t * cbs,
struct shared_info *sh);
extern void dbus_detach(const dbus_pub_t * pub);
extern int dbus_up(const dbus_pub_t * pub);
extern int dbus_down(const dbus_pub_t * pub);
extern int dbus_stop(const dbus_pub_t * pub);
extern int dbus_shutdown(const dbus_pub_t * pub);
extern void dbus_flowctrl_rx(const dbus_pub_t * pub, bool on);
extern int dbus_send_buf(const dbus_pub_t * pub, uint8 * buf, int len,
void *info);
extern int dbus_send_pkt(const dbus_pub_t * pub, void *pkt, void *info);
extern int dbus_send_ctl(const dbus_pub_t * pub, uint8 * buf, int len);
extern int dbus_recv_ctl(const dbus_pub_t * pub, uint8 * buf, int len);
extern int dbus_get_stats(const dbus_pub_t * pub, dbus_stats_t * stats);
extern int dbus_get_attrib(const dbus_pub_t * pub, dbus_attrib_t * attrib);
extern int dbus_get_device_speed(const dbus_pub_t * pub);
extern int dbus_set_config(const dbus_pub_t * pub, dbus_config_t * config);
extern int dbus_get_config(const dbus_pub_t * pub, dbus_config_t * config);
extern void *dbus_pktget(const dbus_pub_t * pub, int len);
extern void dbus_pktfree(const dbus_pub_t * pub, void *pkt);
extern int dbus_set_errmask(const dbus_pub_t * pub, uint32 mask);
extern int dbus_pnp_sleep(const dbus_pub_t * pub);
extern int dbus_pnp_resume(const dbus_pub_t * pub, int *fw_reload);
extern int dbus_pnp_disconnect(const dbus_pub_t * pub);
extern int dbus_iovar_op(const dbus_pub_t * pub, const char *name,
void *params, int plen, void *arg, int len, bool set);
#ifdef BCMDBG
extern void dbus_hist_dump(const dbus_pub_t * pub, struct bcmstrbuf *b);
#endif /* BCMDBG */
/*
* Private Common Bus Interface
*/
/* IO Request Block (IRB) */
typedef struct dbus_irb {
struct dbus_irb *next; /* it's casted from dbus_irb_tx or dbus_irb_rx struct */
} dbus_irb_t;
typedef struct dbus_irb_rx {
struct dbus_irb irb; /* Must be first */
uint8 *buf;
int buf_len;
int actual_len;
void *pkt;
void *info;
void *arg;
} dbus_irb_rx_t;
typedef struct dbus_irb_tx {
struct dbus_irb irb; /* Must be first */
uint8 *buf;
int len;
void *pkt;
int retry_count;
void *info;
void *arg;
} dbus_irb_tx_t;
/* DBUS interface callbacks are different from user callbacks
* so, internally, different info can be passed to upper layer
*/
typedef struct dbus_intf_callbacks {
void (*send_irb_timeout) (void *cbarg, dbus_irb_tx_t * txirb);
void (*send_irb_complete) (void *cbarg, dbus_irb_tx_t * txirb,
int status);
void (*recv_irb_complete) (void *cbarg, dbus_irb_rx_t * rxirb,
int status);
void (*errhandler) (void *cbarg, int err);
void (*ctl_complete) (void *cbarg, int type, int status);
void (*state_change) (void *cbarg, int state);
bool(*isr) (void *cbarg, bool * wantdpc);
bool(*dpc) (void *cbarg, bool bounded);
void (*watchdog) (void *cbarg);
void *(*pktget) (void *cbarg, uint len, bool send);
void (*pktfree) (void *cbarg, void *p, bool send);
struct dbus_irb *(*getirb) (void *cbarg, bool send);
void (*rxerr_indicate) (void *cbarg, bool on);
} dbus_intf_callbacks_t;
/*
* Porting: To support new bus, port these functions below
*/
/*
* Bus specific Interface
* Implemented by dbus_usb.c/dbus_sdio.c
*/
extern int dbus_bus_register(int vid, int pid, probe_cb_t prcb,
disconnect_cb_t discb, void *prarg,
dbus_intf_t ** intf, void *param1, void *param2);
extern int dbus_bus_deregister(void);
/*
* Bus-specific and OS-specific Interface
* Implemented by dbus_usb_[linux/ndis].c/dbus_sdio_[linux/ndis].c
*/
extern int dbus_bus_osl_register(int vid, int pid, probe_cb_t prcb,
disconnect_cb_t discb, void *prarg,
dbus_intf_t ** intf, void *param1,
void *param2);
extern int dbus_bus_osl_deregister(void);
/*
* Bus-specific, OS-specific, HW-specific Interface
* Mainly for SDIO Host HW controller
*/
extern int dbus_bus_osl_hw_register(int vid, int pid, probe_cb_t prcb,
disconnect_cb_t discb, void *prarg,
dbus_intf_t ** intf);
extern int dbus_bus_osl_hw_deregister(void);
#endif /* __DBUS_H__ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _epivers_h_
#define _epivers_h_
#define EPI_MAJOR_VERSION 5
#define EPI_MINOR_VERSION 75
#define EPI_RC_NUMBER 11
#define EPI_INCREMENTAL_NUMBER 0
#define EPI_BUILD_NUMBER 1
#define EPI_VERSION 5, 75, 11, 0
#ifdef BCMSDIO
/* EPI_VERSION_NUM must match FW version */
#define EPI_VERSION_NUM 0x054b0c00
#else
#define EPI_VERSION_NUM 0x054b0b00
#endif
#define EPI_VERSION_DEV 5.75.11
/* Driver Version String, ASCII, 32 chars max */
#define EPI_VERSION_STR "5.75.11"
#endif /* _epivers_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _hnddma_h_
#define _hnddma_h_
#ifndef _hnddma_pub_
#define _hnddma_pub_
typedef const struct hnddma_pub hnddma_t;
#endif /* _hnddma_pub_ */
/* range param for dma_getnexttxp() and dma_txreclaim */
typedef enum txd_range {
HNDDMA_RANGE_ALL = 1,
HNDDMA_RANGE_TRANSMITTED,
HNDDMA_RANGE_TRANSFERED
} txd_range_t;
/* dma function type */
typedef void (*di_detach_t) (hnddma_t * dmah);
typedef bool(*di_txreset_t) (hnddma_t * dmah);
typedef bool(*di_rxreset_t) (hnddma_t * dmah);
typedef bool(*di_rxidle_t) (hnddma_t * dmah);
typedef void (*di_txinit_t) (hnddma_t * dmah);
typedef bool(*di_txenabled_t) (hnddma_t * dmah);
typedef void (*di_rxinit_t) (hnddma_t * dmah);
typedef void (*di_txsuspend_t) (hnddma_t * dmah);
typedef void (*di_txresume_t) (hnddma_t * dmah);
typedef bool(*di_txsuspended_t) (hnddma_t * dmah);
typedef bool(*di_txsuspendedidle_t) (hnddma_t * dmah);
typedef int (*di_txfast_t) (hnddma_t * dmah, void *p, bool commit);
typedef int (*di_txunframed_t) (hnddma_t * dmah, void *p, uint len,
bool commit);
typedef void *(*di_getpos_t) (hnddma_t * di, bool direction);
typedef void (*di_fifoloopbackenable_t) (hnddma_t * dmah);
typedef bool(*di_txstopped_t) (hnddma_t * dmah);
typedef bool(*di_rxstopped_t) (hnddma_t * dmah);
typedef bool(*di_rxenable_t) (hnddma_t * dmah);
typedef bool(*di_rxenabled_t) (hnddma_t * dmah);
typedef void *(*di_rx_t) (hnddma_t * dmah);
typedef bool(*di_rxfill_t) (hnddma_t * dmah);
typedef void (*di_txreclaim_t) (hnddma_t * dmah, txd_range_t range);
typedef void (*di_rxreclaim_t) (hnddma_t * dmah);
typedef uintptr(*di_getvar_t) (hnddma_t * dmah, const char *name);
typedef void *(*di_getnexttxp_t) (hnddma_t * dmah, txd_range_t range);
typedef void *(*di_getnextrxp_t) (hnddma_t * dmah, bool forceall);
typedef void *(*di_peeknexttxp_t) (hnddma_t * dmah);
typedef void *(*di_peeknextrxp_t) (hnddma_t * dmah);
typedef void (*di_rxparam_get_t) (hnddma_t * dmah, uint16 * rxoffset,
uint16 * rxbufsize);
typedef void (*di_txblock_t) (hnddma_t * dmah);
typedef void (*di_txunblock_t) (hnddma_t * dmah);
typedef uint(*di_txactive_t) (hnddma_t * dmah);
typedef void (*di_txrotate_t) (hnddma_t * dmah);
typedef void (*di_counterreset_t) (hnddma_t * dmah);
typedef uint(*di_ctrlflags_t) (hnddma_t * dmah, uint mask, uint flags);
typedef char *(*di_dump_t) (hnddma_t * dmah, struct bcmstrbuf * b,
bool dumpring);
typedef char *(*di_dumptx_t) (hnddma_t * dmah, struct bcmstrbuf * b,
bool dumpring);
typedef char *(*di_dumprx_t) (hnddma_t * dmah, struct bcmstrbuf * b,
bool dumpring);
typedef uint(*di_rxactive_t) (hnddma_t * dmah);
typedef uint(*di_txpending_t) (hnddma_t * dmah);
typedef uint(*di_txcommitted_t) (hnddma_t * dmah);
/* dma opsvec */
typedef struct di_fcn_s {
di_detach_t detach;
di_txinit_t txinit;
di_txreset_t txreset;
di_txenabled_t txenabled;
di_txsuspend_t txsuspend;
di_txresume_t txresume;
di_txsuspended_t txsuspended;
di_txsuspendedidle_t txsuspendedidle;
di_txfast_t txfast;
di_txunframed_t txunframed;
di_getpos_t getpos;
di_txstopped_t txstopped;
di_txreclaim_t txreclaim;
di_getnexttxp_t getnexttxp;
di_peeknexttxp_t peeknexttxp;
di_txblock_t txblock;
di_txunblock_t txunblock;
di_txactive_t txactive;
di_txrotate_t txrotate;
di_rxinit_t rxinit;
di_rxreset_t rxreset;
di_rxidle_t rxidle;
di_rxstopped_t rxstopped;
di_rxenable_t rxenable;
di_rxenabled_t rxenabled;
di_rx_t rx;
di_rxfill_t rxfill;
di_rxreclaim_t rxreclaim;
di_getnextrxp_t getnextrxp;
di_peeknextrxp_t peeknextrxp;
di_rxparam_get_t rxparam_get;
di_fifoloopbackenable_t fifoloopbackenable;
di_getvar_t d_getvar;
di_counterreset_t counterreset;
di_ctrlflags_t ctrlflags;
di_dump_t dump;
di_dumptx_t dumptx;
di_dumprx_t dumprx;
di_rxactive_t rxactive;
di_txpending_t txpending;
di_txcommitted_t txcommitted;
uint endnum;
} di_fcn_t;
/*
* Exported data structure (read-only)
*/
/* export structure */
struct hnddma_pub {
const di_fcn_t *di_fn; /* DMA function pointers */
uint txavail; /* # free tx descriptors */
uint dmactrlflags; /* dma control flags */
/* rx error counters */
uint rxgiants; /* rx giant frames */
uint rxnobuf; /* rx out of dma descriptors */
/* tx error counters */
uint txnobuf; /* tx out of dma descriptors */
};
extern hnddma_t *dma_attach(osl_t * osh, char *name, si_t * sih,
void *dmaregstx, void *dmaregsrx, uint ntxd,
uint nrxd, uint rxbufsize, int rxextheadroom,
uint nrxpost, uint rxoffset, uint * msg_level);
#ifdef BCMDMA32
#define dma_detach(di) ((di)->di_fn->detach(di))
#define dma_txreset(di) ((di)->di_fn->txreset(di))
#define dma_rxreset(di) ((di)->di_fn->rxreset(di))
#define dma_rxidle(di) ((di)->di_fn->rxidle(di))
#define dma_txinit(di) ((di)->di_fn->txinit(di))
#define dma_txenabled(di) ((di)->di_fn->txenabled(di))
#define dma_rxinit(di) ((di)->di_fn->rxinit(di))
#define dma_txsuspend(di) ((di)->di_fn->txsuspend(di))
#define dma_txresume(di) ((di)->di_fn->txresume(di))
#define dma_txsuspended(di) ((di)->di_fn->txsuspended(di))
#define dma_txsuspendedidle(di) ((di)->di_fn->txsuspendedidle(di))
#define dma_txfast(di, p, commit) ((di)->di_fn->txfast(di, p, commit))
#define dma_fifoloopbackenable(di) ((di)->di_fn->fifoloopbackenable(di))
#define dma_txstopped(di) ((di)->di_fn->txstopped(di))
#define dma_rxstopped(di) ((di)->di_fn->rxstopped(di))
#define dma_rxenable(di) ((di)->di_fn->rxenable(di))
#define dma_rxenabled(di) ((di)->di_fn->rxenabled(di))
#define dma_rx(di) ((di)->di_fn->rx(di))
#define dma_rxfill(di) ((di)->di_fn->rxfill(di))
#define dma_txreclaim(di, range) ((di)->di_fn->txreclaim(di, range))
#define dma_rxreclaim(di) ((di)->di_fn->rxreclaim(di))
#define dma_getvar(di, name) ((di)->di_fn->d_getvar(di, name))
#define dma_getnexttxp(di, range) ((di)->di_fn->getnexttxp(di, range))
#define dma_getnextrxp(di, forceall) ((di)->di_fn->getnextrxp(di, forceall))
#define dma_peeknexttxp(di) ((di)->di_fn->peeknexttxp(di))
#define dma_peeknextrxp(di) ((di)->di_fn->peeknextrxp(di))
#define dma_rxparam_get(di, off, bufs) ((di)->di_fn->rxparam_get(di, off, bufs))
#define dma_txblock(di) ((di)->di_fn->txblock(di))
#define dma_txunblock(di) ((di)->di_fn->txunblock(di))
#define dma_txactive(di) ((di)->di_fn->txactive(di))
#define dma_rxactive(di) ((di)->di_fn->rxactive(di))
#define dma_txrotate(di) ((di)->di_fn->txrotate(di))
#define dma_counterreset(di) ((di)->di_fn->counterreset(di))
#define dma_ctrlflags(di, mask, flags) ((di)->di_fn->ctrlflags((di), (mask), (flags)))
#define dma_txpending(di) ((di)->di_fn->txpending(di))
#define dma_txcommitted(di) ((di)->di_fn->txcommitted(di))
#else /* BCMDMA32 */
extern const di_fcn_t dma64proc;
#define dma_detach(di) (dma64proc.detach(di))
#define dma_txreset(di) (dma64proc.txreset(di))
#define dma_rxreset(di) (dma64proc.rxreset(di))
#define dma_rxidle(di) (dma64proc.rxidle(di))
#define dma_txinit(di) (dma64proc.txinit(di))
#define dma_txenabled(di) (dma64proc.txenabled(di))
#define dma_rxinit(di) (dma64proc.rxinit(di))
#define dma_txsuspend(di) (dma64proc.txsuspend(di))
#define dma_txresume(di) (dma64proc.txresume(di))
#define dma_txsuspended(di) (dma64proc.txsuspended(di))
#define dma_txsuspendedidle(di) (dma64proc.txsuspendedidle(di))
#define dma_txfast(di, p, commit) (dma64proc.txfast(di, p, commit))
#define dma_txunframed(di, p, l, commit)(dma64proc.txunframed(di, p, l, commit))
#define dma_getpos(di, dir) (dma64proc.getpos(di, dir))
#define dma_fifoloopbackenable(di) (dma64proc.fifoloopbackenable(di))
#define dma_txstopped(di) (dma64proc.txstopped(di))
#define dma_rxstopped(di) (dma64proc.rxstopped(di))
#define dma_rxenable(di) (dma64proc.rxenable(di))
#define dma_rxenabled(di) (dma64proc.rxenabled(di))
#define dma_rx(di) (dma64proc.rx(di))
#define dma_rxfill(di) (dma64proc.rxfill(di))
#define dma_txreclaim(di, range) (dma64proc.txreclaim(di, range))
#define dma_rxreclaim(di) (dma64proc.rxreclaim(di))
#define dma_getvar(di, name) (dma64proc.d_getvar(di, name))
#define dma_getnexttxp(di, range) (dma64proc.getnexttxp(di, range))
#define dma_getnextrxp(di, forceall) (dma64proc.getnextrxp(di, forceall))
#define dma_peeknexttxp(di) (dma64proc.peeknexttxp(di))
#define dma_peeknextrxp(di) (dma64proc.peeknextrxp(di))
#define dma_rxparam_get(di, off, bufs) (dma64proc.rxparam_get(di, off, bufs))
#define dma_txblock(di) (dma64proc.txblock(di))
#define dma_txunblock(di) (dma64proc.txunblock(di))
#define dma_txactive(di) (dma64proc.txactive(di))
#define dma_rxactive(di) (dma64proc.rxactive(di))
#define dma_txrotate(di) (dma64proc.txrotate(di))
#define dma_counterreset(di) (dma64proc.counterreset(di))
#define dma_ctrlflags(di, mask, flags) (dma64proc.ctrlflags((di), (mask), (flags)))
#define dma_txpending(di) (dma64proc.txpending(di))
#define dma_txcommitted(di) (dma64proc.txcommitted(di))
#endif /* BCMDMA32 */
/* return addresswidth allowed
* This needs to be done after SB attach but before dma attach.
* SB attach provides ability to probe backplane and dma core capabilities
* This info is needed by DMA_ALLOC_CONSISTENT in dma attach
*/
extern uint dma_addrwidth(si_t * sih, void *dmaregs);
/* pio helpers */
extern void dma_txpioloopback(osl_t * osh, dma32regs_t *);
#endif /* _hnddma_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _hndpmu_h_
#define _hndpmu_h_
#define SET_LDO_VOLTAGE_LDO1 1
#define SET_LDO_VOLTAGE_LDO2 2
#define SET_LDO_VOLTAGE_LDO3 3
#define SET_LDO_VOLTAGE_PAREF 4
#define SET_LDO_VOLTAGE_CLDO_PWM 5
#define SET_LDO_VOLTAGE_CLDO_BURST 6
#define SET_LDO_VOLTAGE_CBUCK_PWM 7
#define SET_LDO_VOLTAGE_CBUCK_BURST 8
#define SET_LDO_VOLTAGE_LNLDO1 9
#define SET_LDO_VOLTAGE_LNLDO2_SEL 10
extern void si_pmu_init(si_t * sih, osl_t * osh);
extern void si_pmu_chip_init(si_t * sih, osl_t * osh);
extern void si_pmu_pll_init(si_t * sih, osl_t * osh, uint32 xtalfreq);
extern void si_pmu_res_init(si_t * sih, osl_t * osh);
extern void si_pmu_swreg_init(si_t * sih, osl_t * osh);
extern uint32 si_pmu_force_ilp(si_t * sih, osl_t * osh, bool force);
extern uint32 si_pmu_si_clock(si_t * sih, osl_t * osh);
extern uint32 si_pmu_cpu_clock(si_t * sih, osl_t * osh);
extern uint32 si_pmu_mem_clock(si_t * sih, osl_t * osh);
extern uint32 si_pmu_alp_clock(si_t * sih, osl_t * osh);
extern uint32 si_pmu_ilp_clock(si_t * sih, osl_t * osh);
extern void si_pmu_set_switcher_voltage(si_t * sih, osl_t * osh,
uint8 bb_voltage, uint8 rf_voltage);
extern void si_pmu_set_ldo_voltage(si_t * sih, osl_t * osh, uint8 ldo,
uint8 voltage);
extern uint16 si_pmu_fast_pwrup_delay(si_t * sih, osl_t * osh);
extern void si_pmu_rcal(si_t * sih, osl_t * osh);
extern void si_pmu_pllupd(si_t * sih);
extern void si_pmu_spuravoid(si_t * sih, osl_t * osh, uint8 spuravoid);
extern bool si_pmu_is_otp_powered(si_t * sih, osl_t * osh);
extern uint32 si_pmu_measure_alpclk(si_t * sih, osl_t * osh);
extern uint32 si_pmu_chipcontrol(si_t * sih, uint reg, uint32 mask, uint32 val);
extern uint32 si_pmu_regcontrol(si_t * sih, uint reg, uint32 mask, uint32 val);
extern uint32 si_pmu_pllcontrol(si_t * sih, uint reg, uint32 mask, uint32 val);
extern void si_pmu_pllupd(si_t * sih);
extern void si_pmu_sprom_enable(si_t * sih, osl_t * osh, bool enable);
extern void si_pmu_radio_enable(si_t * sih, bool enable);
extern uint32 si_pmu_waitforclk_on_backplane(si_t * sih, osl_t * osh,
uint32 clk, uint32 delay);
extern void si_pmu_otp_power(si_t * sih, osl_t * osh, bool on);
extern void si_sdiod_drive_strength_init(si_t * sih, osl_t * osh,
uint32 drivestrength);
#endif /* _hndpmu_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HNDSOC_H
#define _HNDSOC_H
/* Include the soci specific files */
#include <sbconfig.h>
#include <aidmp.h>
/*
* SOC Interconnect Address Map.
* All regions may not exist on all chips.
*/
#define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */
#define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
#define SI_PCI_MEM_SZ (64 * 1024 * 1024)
#define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
#define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
#define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */
#ifdef SI_ENUM_BASE_VARIABLE
#define SI_ENUM_BASE (sii->pub.si_enum_base)
#else
#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
#endif /* SI_ENUM_BASE_VARIABLE */
#define SI_WRAP_BASE 0x18100000 /* Wrapper space base */
#define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
#define SI_MAXCORES 16 /* Max cores (this is arbitrary, for software
* convenience and could be changed if we
* make any larger chips
*/
#define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
#define SI_FASTRAM_SWAPPED 0x19800000
#define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
#define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
#define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
#define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
#define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
#define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
#define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
#define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */
#define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
#define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
#define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
#define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */
#define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
#define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
* (2 ZettaBytes), low 32 bits
*/
#define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
* (2 ZettaBytes), high 32 bits
*/
/* core codes */
#define NODEV_CORE_ID 0x700 /* Invalid coreid */
#define CC_CORE_ID 0x800 /* chipcommon core */
#define ILINE20_CORE_ID 0x801 /* iline20 core */
#define SRAM_CORE_ID 0x802 /* sram core */
#define SDRAM_CORE_ID 0x803 /* sdram core */
#define PCI_CORE_ID 0x804 /* pci core */
#define MIPS_CORE_ID 0x805 /* mips core */
#define ENET_CORE_ID 0x806 /* enet mac core */
#define CODEC_CORE_ID 0x807 /* v90 codec core */
#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
#define ADSL_CORE_ID 0x809 /* ADSL core */
#define ILINE100_CORE_ID 0x80a /* iline100 core */
#define IPSEC_CORE_ID 0x80b /* ipsec core */
#define UTOPIA_CORE_ID 0x80c /* utopia core */
#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
#define SOCRAM_CORE_ID 0x80e /* internal memory core */
#define MEMC_CORE_ID 0x80f /* memc sdram core */
#define OFDM_CORE_ID 0x810 /* OFDM phy core */
#define EXTIF_CORE_ID 0x811 /* external interface core */
#define D11_CORE_ID 0x812 /* 802.11 MAC core */
#define APHY_CORE_ID 0x813 /* 802.11a phy core */
#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
#define MIPS33_CORE_ID 0x816 /* mips3302 core */
#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
#define SDIOH_CORE_ID 0x81b /* sdio host core */
#define ROBO_CORE_ID 0x81c /* roboswitch core */
#define ATA100_CORE_ID 0x81d /* parallel ATA core */
#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
#define PCIE_CORE_ID 0x820 /* pci express core */
#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
#define PMU_CORE_ID 0x827 /* PMU core */
#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
#define SDIOD_CORE_ID 0x829 /* SDIO device core */
#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
#define SC_CORE_ID 0x831 /* shared common core */
#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
#define SPIH_CORE_ID 0x833 /* SPI host core */
#define I2S_CORE_ID 0x834 /* I2S core */
#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
#define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all
* unused address ranges
*/
/* There are TWO constants on all HND chips: SI_ENUM_BASE above,
* and chipcommon being the first core:
*/
#define SI_CC_IDX 0
/* SOC Interconnect types (aka chip types) */
#define SOCI_AI 1
/* Common core control flags */
#define SICF_BIST_EN 0x8000
#define SICF_PME_EN 0x4000
#define SICF_CORE_BITS 0x3ffc
#define SICF_FGC 0x0002
#define SICF_CLOCK_EN 0x0001
/* Common core status flags */
#define SISF_BIST_DONE 0x8000
#define SISF_BIST_ERROR 0x4000
#define SISF_GATED_CLK 0x2000
#define SISF_DMA64 0x1000
#define SISF_CORE_BITS 0x0fff
/* A register that is common to all cores to
* communicate w/PMU regarding clock control.
*/
#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
/* clk_ctl_st register */
#define CCS_FORCEALP 0x00000001 /* force ALP request */
#define CCS_FORCEHT 0x00000002 /* force HT request */
#define CCS_FORCEILP 0x00000004 /* force ILP request */
#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
#define CCS_ERSRC_REQ_SHIFT 8
#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
#define CCS_HTAVAIL 0x00020000 /* HT is available */
#define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */
#define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */
#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
#define CCS_ERSRC_STS_SHIFT 24
#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */
#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */
/* Not really related to SOC Interconnect, but a couple of software
* conventions for the use the flash space:
*/
/* Minumum amount of flash we support */
#define FLASH_MIN 0x00020000 /* Minimum flash size */
/* A boot/binary may have an embedded block that describes its size */
#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
#define BISZ_TXTST_IDX 1 /* 1: text start */
#define BISZ_TXTEND_IDX 2 /* 2: text end */
#define BISZ_DATAST_IDX 3 /* 3: data start */
#define BISZ_DATAEND_IDX 4 /* 4: data end */
#define BISZ_BSSST_IDX 5 /* 5: bss start */
#define BISZ_BSSEND_IDX 6 /* 6: bss end */
#define BISZ_SIZE 7 /* descriptor size in 32-bit integers */
#endif /* _HNDSOC_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _hndtcam_h_
#define _hndtcam_h_
/*
* 0 - 1
* 1 - 2 Consecutive locations are patched
* 2 - 4 Consecutive locations are patched
* 3 - 8 Consecutive locations are patched
* 4 - 16 Consecutive locations are patched
* Define default to patch 2 locations
*/
#define PATCHCOUNT 0
#define SRPC_PATCHCOUNT PATCHCOUNT
/* N Consecutive location to patch */
#define SRPC_PATCHNLOC (1 << (SRPC_PATCHCOUNT))
/* patch values and address structure */
typedef struct patchaddrvalue {
uint32 addr;
uint32 value;
} patchaddrvalue_t;
extern void hnd_patch_init(void *srp);
extern void hnd_tcam_write(void *srp, uint16 index, uint32 data);
extern void hnd_tcam_read(void *srp, uint16 index, uint32 * content);
void *hnd_tcam_init(void *srp, uint no_addrs);
extern void hnd_tcam_disablepatch(void *srp);
extern void hnd_tcam_enablepatch(void *srp);
extern void hnd_tcam_load(void *srp, const patchaddrvalue_t * patchtbl);
#endif /* _hndtcam_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _linux_osl_h_
#define _linux_osl_h_
#include <typedefs.h>
/* Linux Kernel: File Operations: start */
extern void *osl_os_open_image(char *filename);
extern int osl_os_get_image_block(char *buf, int len, void *image);
extern void osl_os_close_image(void *image);
/* Linux Kernel: File Operations: end */
extern osl_t *osl_attach(void *pdev, uint bustype, bool pkttag);
extern void osl_detach(osl_t * osh);
extern uint32 g_assert_type;
#if defined(BCMDBG_ASSERT)
#define ASSERT(exp) \
do { if (!(exp)) osl_assert(#exp, __FILE__, __LINE__); } while (0)
extern void osl_assert(char *exp, char *file, int line);
#else
#ifdef __GNUC__
#define GCC_VERSION \
(__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
#if GCC_VERSION > 30100
#define ASSERT(exp) do {} while (0)
#else
/* ASSERT could cause segmentation fault on GCC3.1, use empty instead */
#define ASSERT(exp)
#endif /* GCC_VERSION > 30100 */
#endif /* __GNUC__ */
#endif /* defined(BCMDBG_ASSERT) */
#define OSL_DELAY(usec) osl_delay(usec)
extern void osl_delay(uint usec);
#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
osl_pcmcia_read_attr((osh), (offset), (buf), (size))
#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
osl_pcmcia_write_attr((osh), (offset), (buf), (size))
extern void osl_pcmcia_read_attr(osl_t * osh, uint offset, void *buf, int size);
extern void osl_pcmcia_write_attr(osl_t * osh, uint offset, void *buf,
int size);
/* PCI configuration space access macros */
#define OSL_PCI_READ_CONFIG(osh, offset, size) \
osl_pci_read_config((osh), (offset), (size))
#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
osl_pci_write_config((osh), (offset), (size), (val))
extern uint32 osl_pci_read_config(osl_t * osh, uint offset, uint size);
extern void osl_pci_write_config(osl_t * osh, uint offset, uint size, uint val);
/* PCI device bus # and slot # */
#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
extern uint osl_pci_bus(osl_t * osh);
extern uint osl_pci_slot(osl_t * osh);
/* Pkttag flag should be part of public information */
typedef struct {
bool pkttag;
uint pktalloced; /* Number of allocated packet buffers */
bool mmbus; /* Bus supports memory-mapped register accesses */
pktfree_cb_fn_t tx_fn; /* Callback function for PKTFREE */
void *tx_ctx; /* Context to the callback function */
#ifdef BCMSDIO
osl_rreg_fn_t rreg_fn; /* Read Register function */
osl_wreg_fn_t wreg_fn; /* Write Register function */
void *reg_ctx; /* Context to the reg callback functions */
#endif
} osl_pubinfo_t;
#define PKTFREESETCB(osh, _tx_fn, _tx_ctx) \
do { \
((osl_pubinfo_t*)osh)->tx_fn = _tx_fn; \
((osl_pubinfo_t*)osh)->tx_ctx = _tx_ctx; \
} while (0)
#ifdef BCMSDIO
#define REGOPSSET(osh, rreg, wreg, ctx) \
do { \
((osl_pubinfo_t*)osh)->rreg_fn = rreg; \
((osl_pubinfo_t*)osh)->wreg_fn = wreg; \
((osl_pubinfo_t*)osh)->reg_ctx = ctx; \
} while (0)
#endif
#define BUS_SWAP32(v) (v)
#define MALLOC(osh, size) osl_malloc((osh), (size))
#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
#define MALLOCED(osh) osl_malloced((osh))
extern void *osl_malloc(osl_t * osh, uint size);
extern void osl_mfree(osl_t * osh, void *addr, uint size);
extern uint osl_malloced(osl_t * osh);
#define NATIVE_MALLOC(osh, size) kmalloc(size, GFP_ATOMIC)
#define NATIVE_MFREE(osh, addr, size) kfree(addr)
#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
extern uint osl_malloc_failed(osl_t * osh);
/* allocate/free shared (dma-able) consistent memory */
#define DMA_CONSISTENT_ALIGN osl_dma_consistent_align()
#define DMA_ALLOC_CONSISTENT(osh, size, align, tot, pap, dmah) \
osl_dma_alloc_consistent((osh), (size), (align), (tot), (pap))
#define DMA_FREE_CONSISTENT(osh, va, size, pa, dmah) \
osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
extern uint osl_dma_consistent_align(void);
extern void *osl_dma_alloc_consistent(osl_t * osh, uint size, uint16 align,
uint * tot, ulong * pap);
extern void osl_dma_free_consistent(osl_t * osh, void *va, uint size, ulong pa);
/* map/unmap direction */
#define DMA_TX 1 /* TX direction for DMA */
#define DMA_RX 2 /* RX direction for DMA */
/* map/unmap shared (dma-able) memory */
#define DMA_MAP(osh, va, size, direction, p, dmah) \
osl_dma_map((osh), (va), (size), (direction))
#define DMA_UNMAP(osh, pa, size, direction, p, dmah) \
osl_dma_unmap((osh), (pa), (size), (direction))
extern uint osl_dma_map(osl_t * osh, void *va, uint size, int direction);
extern void osl_dma_unmap(osl_t * osh, uint pa, uint size, int direction);
/* API for DMA addressing capability */
#define OSL_DMADDRWIDTH(osh, addrwidth) do {} while (0)
/* register access macros */
#if defined(BCMSDIO)
#include <bcmsdh.h>
#define OSL_WRITE_REG(osh, r, v) (bcmsdh_reg_write(NULL, (uintptr)(r), sizeof(*(r)), (v)))
#define OSL_READ_REG(osh, r) (bcmsdh_reg_read(NULL, (uintptr)(r), sizeof(*(r))))
#endif
#if defined(BCMSDIO)
#define SELECT_BUS_WRITE(osh, mmap_op, bus_op) if (((osl_pubinfo_t*)(osh))->mmbus) \
mmap_op else bus_op
#define SELECT_BUS_READ(osh, mmap_op, bus_op) (((osl_pubinfo_t*)(osh))->mmbus) ? \
mmap_op : bus_op
#else
#define SELECT_BUS_WRITE(osh, mmap_op, bus_op) mmap_op
#define SELECT_BUS_READ(osh, mmap_op, bus_op) mmap_op
#endif
#define OSL_ERROR(bcmerror) osl_error(bcmerror)
extern int osl_error(int bcmerror);
/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
#define PKTBUFSZ 2048 /* largest reasonable packet buffer, driver uses for ethernet MTU */
#define OSL_SYSUPTIME() ((uint32)jiffies * (1000 / HZ))
#define printf(fmt, args...) printk(fmt , ## args)
#include <linux/kernel.h> /* for vsn/printf's */
#include <linux/string.h> /* for mem*, str* */
/* bcopy's: Linux kernel doesn't provide these (anymore) */
#define bcopy(src, dst, len) memcpy((dst), (src), (len))
#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
#define bzero(b, len) memset((b), '\0', (len))
/* register access macros */
#if defined(OSLREGOPS)
#else
#ifndef IL_BIGENDIAN
#ifndef __mips__
#define R_REG(osh, r) (\
SELECT_BUS_READ(osh, sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
readl((volatile uint32*)(r)), OSL_READ_REG(osh, r)) \
)
#else /* __mips__ */
#define R_REG(osh, r) (\
SELECT_BUS_READ(osh, \
({ \
__typeof(*(r)) __osl_v; \
__asm__ __volatile__("sync"); \
switch (sizeof(*(r))) { \
case sizeof(uint8): __osl_v = \
readb((volatile uint8*)(r)); break; \
case sizeof(uint16): __osl_v = \
readw((volatile uint16*)(r)); break; \
case sizeof(uint32): __osl_v = \
readl((volatile uint32*)(r)); break; \
} \
__asm__ __volatile__("sync"); \
__osl_v; \
}), \
({ \
__typeof(*(r)) __osl_v; \
__asm__ __volatile__("sync"); \
__osl_v = OSL_READ_REG(osh, r); \
__asm__ __volatile__("sync"); \
__osl_v; \
})) \
)
#endif /* __mips__ */
#define W_REG(osh, r, v) do { \
SELECT_BUS_WRITE(osh, \
switch (sizeof(*(r))) { \
case sizeof(uint8): \
writeb((uint8)(v), (volatile uint8*)(r)); break; \
case sizeof(uint16): \
writew((uint16)(v), (volatile uint16*)(r)); break; \
case sizeof(uint32): \
writel((uint32)(v), (volatile uint32*)(r)); break; \
}, \
(OSL_WRITE_REG(osh, r, v))); \
} while (0)
#else /* IL_BIGENDIAN */
#define R_REG(osh, r) (\
SELECT_BUS_READ(osh, \
({ \
__typeof(*(r)) __osl_v; \
switch (sizeof(*(r))) { \
case sizeof(uint8): __osl_v = \
readb((volatile uint8*)((uintptr)(r)^3)); break; \
case sizeof(uint16): __osl_v = \
readw((volatile uint16*)((uintptr)(r)^2)); break; \
case sizeof(uint32): __osl_v = \
readl((volatile uint32*)(r)); break; \
} \
__osl_v; \
}), \
OSL_READ_REG(osh, r)) \
)
#define W_REG(osh, r, v) do { \
SELECT_BUS_WRITE(osh, \
switch (sizeof(*(r))) { \
case sizeof(uint8): \
writeb((uint8)(v), \
(volatile uint8*)((uintptr)(r)^3)); break; \
case sizeof(uint16): \
writew((uint16)(v), \
(volatile uint16*)((uintptr)(r)^2)); break; \
case sizeof(uint32): \
writel((uint32)(v), \
(volatile uint32*)(r)); break; \
}, \
(OSL_WRITE_REG(osh, r, v))); \
} while (0)
#endif /* IL_BIGENDIAN */
#endif /* OSLREGOPS */
#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
/* bcopy, bcmp, and bzero functions */
#define bcopy(src, dst, len) memcpy((dst), (src), (len))
#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
#define bzero(b, len) memset((b), '\0', (len))
/* uncached/cached virtual address */
#ifdef __mips__
#include <asm/addrspace.h>
#define OSL_UNCACHED(va) ((void *)KSEG1ADDR((va)))
#define OSL_CACHED(va) ((void *)KSEG0ADDR((va)))
#else
#define OSL_UNCACHED(va) ((void *)va)
#define OSL_CACHED(va) ((void *)va)
#endif /* mips */
#if defined(mips)
#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
#elif defined(__i386__)
#define OSL_GETCYCLES(x) rdtscl((x))
#else
#define OSL_GETCYCLES(x) ((x) = 0)
#endif /* defined(mips) */
/* dereference an address that may cause a bus exception */
#ifdef mips
#define BUSPROBE(val, addr) get_dbe((val), (addr))
#include <asm/paccess.h>
#else
#define BUSPROBE(val, addr) ({ (val) = R_REG(NULL, (addr)); 0; })
#endif /* mips */
/* map/unmap physical to virtual I/O */
#if !defined(CONFIG_MMC_MSM7X00A)
#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
#else
#define REG_MAP(pa, size) (void *)(0)
#endif /* !defined(CONFIG_MMC_MSM7X00A */
#define REG_UNMAP(va) iounmap((va))
#define R_SM(r) *(r)
#define W_SM(r, v) (*(r) = (v))
#define BZERO_SM(r, len) memset((r), '\0', (len))
#include <linuxver.h> /* use current 2.4.x calling conventions */
/* packet primitives */
#define PKTGET(osh, len, send) osl_pktget((osh), (len))
#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
#define PKTFREE(osh, skb, send) osl_pktfree((osh), (skb), (send))
#define PKTDATA(skb) (((struct sk_buff*)(skb))->data)
#define PKTLEN(skb) (((struct sk_buff*)(skb))->len)
#define PKTHEADROOM(skb) (PKTDATA(skb)-(((struct sk_buff*)(skb))->head))
#define PKTTAILROOM(skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
#define PKTNEXT(skb) (((struct sk_buff*)(skb))->next)
#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
#define PKTSETLEN(skb, len) __skb_trim((struct sk_buff*)(skb), (len))
#define PKTPUSH(skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
#define PKTPULL(skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
#define PKTTAG(skb) ((void*)(((struct sk_buff*)(skb))->cb))
#define PKTALLOCED(osh) ((osl_pubinfo_t *)(osh))->pktalloced
#define PKTSETPOOL(osh, skb, x, y) do {} while (0)
#define PKTPOOL(osh, skb) FALSE
#define PKTUNALLOC(osh) ((osl_pubinfo_t *)(osh))->pktalloced--
#define PKTSETSKIPCT(osh, skb)
#define PKTCLRSKIPCT(osh, skb)
#define PKTSKIPCT(osh, skb)
extern void osl_pktfree(osl_t * osh, void *skb, bool send);
extern void *osl_pktget(osl_t * osh, uint len);
extern void *osl_pktdup(osl_t * osh, void *skb);
#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
#define PKTSUMNEEDED(skb) (((struct sk_buff*)(skb))->ip_summed == CHECKSUM_HW)
#define PKTSETSUMGOOD(skb, x) (((struct sk_buff*)(skb))->ip_summed = \
((x) ? CHECKSUM_UNNECESSARY : CHECKSUM_NONE))
/* PKTSETSUMNEEDED and PKTSUMGOOD are not possible because skb->ip_summed is overloaded */
#define PKTSHARED(skb) (((struct sk_buff*)(skb))->cloned)
#ifdef BCMSDIO
#define RPC_READ_REG(osh, r) (\
sizeof(*(r)) == sizeof(uint8) ? osl_readb((osh), (volatile uint8*)(r)) : \
sizeof(*(r)) == sizeof(uint16) ? osl_readw((osh), (volatile uint16*)(r)) : \
osl_readl((osh), (volatile uint32*)(r)) \
)
#define RPC_WRITE_REG(osh, r, v) do { \
switch (sizeof(*(r))) { \
case sizeof(uint8): osl_writeb((osh), (volatile uint8*)(r), (uint8)(v)); break; \
case sizeof(uint16): osl_writew((osh), (volatile uint16*)(r), (uint16)(v)); break; \
case sizeof(uint32): osl_writel((osh), (volatile uint32*)(r), (uint32)(v)); break; \
} \
} while (0)
extern uint8 osl_readb(osl_t * osh, volatile uint8 * r);
extern uint16 osl_readw(osl_t * osh, volatile uint16 * r);
extern uint32 osl_readl(osl_t * osh, volatile uint32 * r);
extern void osl_writeb(osl_t * osh, volatile uint8 * r, uint8 v);
extern void osl_writew(osl_t * osh, volatile uint16 * r, uint16 v);
extern void osl_writel(osl_t * osh, volatile uint32 * r, uint32 v);
#endif /* BCMSDIO */
#endif /* _linux_osl_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _linuxver_h_
#define _linuxver_h_
#include <linux/version.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#undef IP_TOS
#include <asm/io.h>
#include <linux/workqueue.h>
#define MY_INIT_WORK(_work, _func) INIT_WORK(_work, _func)
typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs * ptregs);
#include <linux/sched.h>
#include <linux/ieee80211.h>
#ifndef __exit
#define __exit
#endif
#ifndef __devexit
#define __devexit
#endif
#ifndef __devinit
#define __devinit __init
#endif
#ifndef __devinitdata
#define __devinitdata
#endif
#ifndef __devexit_p
#define __devexit_p(x) x
#endif
#define pci_module_init pci_register_driver
#define netif_down(dev)
/* Power management related macro & routines */
#define PCI_SAVE_STATE(a, b) pci_save_state(a)
#define PCI_RESTORE_STATE(a, b) pci_restore_state(a)
/* Module refcount handled internally in 2.6.x */
#ifndef SET_MODULE_OWNER
#define SET_MODULE_OWNER(dev) do {} while (0)
#endif
#ifndef MOD_INC_USE_COUNT
#define MOD_INC_USE_COUNT do {} while (0)
#endif
#ifndef MOD_DEC_USE_COUNT
#define MOD_DEC_USE_COUNT do {} while (0)
#endif
#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
#ifndef SET_NETDEV_DEV
#define SET_NETDEV_DEV(net, pdev) do {} while (0)
#endif
#ifndef HAVE_FREE_NETDEV
#define free_netdev(dev) kfree(dev)
#endif
/* suspend args */
#define DRV_SUSPEND_STATE_TYPE pm_message_t
#define CHECKSUM_HW CHECKSUM_PARTIAL
#include <linux/time.h>
#include <linux/wait.h>
#define KILL_PROC(nr, sig) \
do { \
struct task_struct *tsk; \
struct pid *pid; \
pid = find_get_pid((pid_t)nr); \
tsk = pid_task(pid, PIDTYPE_PID); \
if (tsk) send_sig(sig, tsk, 1); \
} while (0)
#define WL_DEV_IF(dev) ((wl_if_t*)netdev_priv(dev))
#endif /* _linuxver_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _NICPCI_H
#define _NICPCI_H
#if defined(BCMSDIO) || (defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS))
#define pcicore_find_pci_capability(a, b, c, d) (0)
#define pcie_readreg(a, b, c, d) (0)
#define pcie_writereg(a, b, c, d, e) (0)
#define pcie_clkreq(a, b, c) (0)
#define pcie_lcreg(a, b, c) (0)
#define pcicore_init(a, b, c) (0x0dadbeef)
#define pcicore_deinit(a) do { } while (0)
#define pcicore_attach(a, b, c) do { } while (0)
#define pcicore_hwup(a) do { } while (0)
#define pcicore_up(a, b) do { } while (0)
#define pcicore_sleep(a) do { } while (0)
#define pcicore_down(a, b) do { } while (0)
#define pcie_war_ovr_aspm_update(a, b) do { } while (0)
#define pcicore_pcieserdesreg(a, b, c, d, e) (0)
#define pcicore_pciereg(a, b, c, d, e) (0)
#define pcicore_pmecap_fast(a) (FALSE)
#define pcicore_pmeen(a) do { } while (0)
#define pcicore_pmeclr(a) do { } while (0)
#define pcicore_pmestat(a) (FALSE)
#else
struct sbpcieregs;
extern uint8 pcicore_find_pci_capability(osl_t * osh, uint8 req_cap_id,
uchar * buf, uint32 * buflen);
extern uint pcie_readreg(osl_t * osh, struct sbpcieregs *pcieregs,
uint addrtype, uint offset);
extern uint pcie_writereg(osl_t * osh, struct sbpcieregs *pcieregs,
uint addrtype, uint offset, uint val);
extern uint8 pcie_clkreq(void *pch, uint32 mask, uint32 val);
extern uint32 pcie_lcreg(void *pch, uint32 mask, uint32 val);
extern void *pcicore_init(si_t * sih, osl_t * osh, void *regs);
extern void pcicore_deinit(void *pch);
extern void pcicore_attach(void *pch, char *pvars, int state);
extern void pcicore_hwup(void *pch);
extern void pcicore_up(void *pch, int state);
extern void pcicore_sleep(void *pch);
extern void pcicore_down(void *pch, int state);
extern void pcie_war_ovr_aspm_update(void *pch, uint8 aspm);
extern uint32 pcicore_pcieserdesreg(void *pch, uint32 mdioslave, uint32 offset,
uint32 mask, uint32 val);
extern uint32 pcicore_pciereg(void *pch, uint32 offset, uint32 mask,
uint32 val, uint type);
extern bool pcicore_pmecap_fast(osl_t * osh);
extern void pcicore_pmeen(void *pch);
extern void pcicore_pmeclr(void *pch);
extern bool pcicore_pmestat(void *pch);
#endif /* defined(BCMSDIO) || (defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)) */
#endif /* _NICPCI_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _osl_h_
#define _osl_h_
/* osl handle type forward declaration */
typedef struct osl_info osl_t;
typedef struct osl_dmainfo osldma_t;
#define OSL_PKTTAG_SZ 32 /* Size of PktTag */
/* Drivers use PKTFREESETCB to register a callback function when a packet is freed by OSL */
typedef void (*pktfree_cb_fn_t) (void *ctx, void *pkt, unsigned int status);
#ifdef BCMSDIO
/* Drivers use REGOPSSET() to register register read/write funcitons */
typedef unsigned int (*osl_rreg_fn_t) (void *ctx, void *reg, unsigned int size);
typedef void (*osl_wreg_fn_t) (void *ctx, void *reg, unsigned int val,
unsigned int size);
#endif
#include <linux_osl.h>
/* --------------------------------------------------------------------------
** Register manipulation macros.
*/
#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
#ifndef AND_REG
#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
#endif /* !AND_REG */
#ifndef OR_REG
#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
#endif /* !OR_REG */
#if !defined(OSL_SYSUPTIME)
#define OSL_SYSUPTIME() (0)
#define OSL_SYSUPTIME_SUPPORT FALSE
#else
#define OSL_SYSUPTIME_SUPPORT TRUE
#endif /* OSL_SYSUPTIME */
#endif /* _osl_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/* Error check - BWL_PACKED_SECTION is defined in packed_section_start.h
* and undefined in packed_section_end.h. If it is NOT defined at this
* point, then there is a missing include of packed_section_start.h.
*/
#ifdef BWL_PACKED_SECTION
#undef BWL_PACKED_SECTION
#else
#error "BWL_PACKED_SECTION is NOT defined!"
#endif
/* Compiler-specific directives for structure packing are declared in
* packed_section_start.h. This marks the end of the structure packing section,
* so, undef them here.
*/
#undef BWL_PRE_PACKED_STRUCT
#undef BWL_POST_PACKED_STRUCT

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/* Error check - BWL_PACKED_SECTION is defined in packed_section_start.h
* and undefined in packed_section_end.h. If it is already defined at this
* point, then there is a missing include of packed_section_end.h.
*/
#ifdef BWL_PACKED_SECTION
#error "BWL_PACKED_SECTION is already defined!"
#else
#define BWL_PACKED_SECTION
#endif
/* Declare compiler-specific directives for structure packing. */
#if defined(__GNUC__)
#define BWL_PRE_PACKED_STRUCT
#define BWL_POST_PACKED_STRUCT __attribute__((packed))
#elif defined(__CC_ARM)
#define BWL_PRE_PACKED_STRUCT __packed
#define BWL_POST_PACKED_STRUCT
#else
#error "Unknown compiler!"
#endif

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PCI_CORE_H_
#define _PCI_CORE_H_
#ifndef _LANGUAGE_ASSEMBLY
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif
/* Sonics side: PCI core and host control registers */
typedef struct sbpciregs {
uint32 control; /* PCI control */
uint32 PAD[3];
uint32 arbcontrol; /* PCI arbiter control */
uint32 clkrun; /* Clkrun Control (>=rev11) */
uint32 PAD[2];
uint32 intstatus; /* Interrupt status */
uint32 intmask; /* Interrupt mask */
uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
uint32 PAD[9];
uint32 bcastaddr; /* Sonics broadcast address */
uint32 bcastdata; /* Sonics broadcast data */
uint32 PAD[2];
uint32 gpioin; /* ro: gpio input (>=rev2) */
uint32 gpioout; /* rw: gpio output (>=rev2) */
uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
uint32 PAD[36];
uint32 sbtopci0; /* Sonics to PCI translation 0 */
uint32 sbtopci1; /* Sonics to PCI translation 1 */
uint32 sbtopci2; /* Sonics to PCI translation 2 */
uint32 PAD[189];
uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
uint16 sprom[36]; /* SPROM shadow Area */
uint32 PAD[46];
} sbpciregs_t;
#endif /* _LANGUAGE_ASSEMBLY */
/* PCI control */
#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
#define PCI_RST 0x02 /* Value driven out to pin */
#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
/* PCI arbiter control */
#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
/* ParkID - for PCI corerev >= 8 */
#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
#define PCI_PARKID_SHIFT 2
#define PCI_PARKID_EXT0 0 /* External master 0 */
#define PCI_PARKID_EXT1 1 /* External master 1 */
#define PCI_PARKID_EXT2 2 /* External master 2 */
#define PCI_PARKID_EXT3 3 /* External master 3 (rev >= 11) */
#define PCI_PARKID_INT 3 /* Internal master (rev < 11) */
#define PCI11_PARKID_INT 4 /* Internal master (rev >= 11) */
#define PCI_PARKID_LAST 4 /* Last active master (rev < 11) */
#define PCI11_PARKID_LAST 5 /* Last active master (rev >= 11) */
#define PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */
/* Interrupt status/mask */
#define PCI_INTA 0x01 /* PCI INTA# is asserted */
#define PCI_INTB 0x02 /* PCI INTB# is asserted */
#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
#define PCI_PME 0x10 /* PCI PME# is asserted */
/* (General) PCI/SB mailbox interrupts, two bits per pci function */
#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
/* Sonics broadcast address */
#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
/* Sonics to PCI translation types */
#define SBTOPCI0_MASK 0xfc000000
#define SBTOPCI1_MASK 0xfc000000
#define SBTOPCI2_MASK 0xc0000000
#define SBTOPCI_MEM 0
#define SBTOPCI_IO 1
#define SBTOPCI_CFG0 2
#define SBTOPCI_CFG1 3
#define SBTOPCI_PREF 0x4 /* prefetch enable */
#define SBTOPCI_BURST 0x8 /* burst enable */
#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
#define SBTOPCI_RC_READ 0x00 /* memory read */
#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
/* PCI core index in SROM shadow area */
#define SRSH_PI_OFFSET 0 /* first word */
#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
#define SRSH_PI_SHIFT 12 /* bit 15:12 */
#endif /* _PCI_CORE_H_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _h_pcicfg_
#define _h_pcicfg_
/* The following inside ifndef's so we don't collide with NTDDK.H */
#ifndef PCI_MAX_BUS
#define PCI_MAX_BUS 0x100
#endif
#ifndef PCI_MAX_DEVICES
#define PCI_MAX_DEVICES 0x20
#endif
#ifndef PCI_MAX_FUNCTION
#define PCI_MAX_FUNCTION 0x8
#endif
#ifndef PCI_INVALID_VENDORID
#define PCI_INVALID_VENDORID 0xffff
#endif
#ifndef PCI_INVALID_DEVICEID
#define PCI_INVALID_DEVICEID 0xffff
#endif
/* Convert between bus-slot-function-register and config addresses */
#define PCICFG_BUS_SHIFT 16 /* Bus shift */
#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
#define PCICFG_FUN_SHIFT 8 /* Function shift */
#define PCICFG_OFF_SHIFT 0 /* Register shift */
#define PCICFG_BUS_MASK 0xff /* Bus mask */
#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
#define PCICFG_FUN_MASK 7 /* Function mask */
#define PCICFG_OFF_MASK 0xff /* Bus mask */
#define PCI_CONFIG_ADDR(b, s, f, o) \
((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
| (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
| (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
| (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
/* PCIE Config space accessing MACROS */
#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
#define PCIECFG_FUN_SHIFT 16 /* Function shift */
#define PCIECFG_OFF_SHIFT 0 /* Register shift */
#define PCIECFG_BUS_MASK 0xff /* Bus mask */
#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
#define PCIECFG_FUN_MASK 7 /* Function mask */
#define PCIECFG_OFF_MASK 0xfff /* Register mask */
#define PCIE_CONFIG_ADDR(b, s, f, o) \
((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
| (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
| (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
| (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
/* The actual config space */
#define PCI_BAR_MAX 6
#define PCI_ROM_BAR 8
#define PCR_RSVDA_MAX 2
/* Bits in PCI bars' flags */
#define PCIBAR_FLAGS 0xf
#define PCIBAR_IO 0x1
#define PCIBAR_MEM1M 0x2
#define PCIBAR_MEM64 0x4
#define PCIBAR_PREFETCH 0x8
#define PCIBAR_MEM32_MASK 0xFFFFFF80
/* pci config status reg has a bit to indicate that capability ptr is present */
#define PCI_CAPPTR_PRESENT 0x0010
typedef struct _pci_config_regs {
uint16 vendor;
uint16 device;
uint16 command;
uint16 status;
uint8 rev_id;
uint8 prog_if;
uint8 sub_class;
uint8 base_class;
uint8 cache_line_size;
uint8 latency_timer;
uint8 header_type;
uint8 bist;
uint32 base[PCI_BAR_MAX];
uint32 cardbus_cis;
uint16 subsys_vendor;
uint16 subsys_id;
uint32 baserom;
uint32 rsvd_a[PCR_RSVDA_MAX];
uint8 int_line;
uint8 int_pin;
uint8 min_gnt;
uint8 max_lat;
uint8 dev_dep[192];
} pci_config_regs;
#define SZPCR (sizeof (pci_config_regs))
#define MINSZPCR 64 /* offsetof (dev_dep[0] */
/* A structure for the config registers is nice, but in most
* systems the config space is not memory mapped, so we need
* field offsetts. :-(
*/
#define PCI_CFG_VID 0
#define PCI_CFG_DID 2
#define PCI_CFG_CMD 4
#define PCI_CFG_STAT 6
#define PCI_CFG_REV 8
#define PCI_CFG_PROGIF 9
#define PCI_CFG_SUBCL 0xa
#define PCI_CFG_BASECL 0xb
#define PCI_CFG_CLSZ 0xc
#define PCI_CFG_LATTIM 0xd
#define PCI_CFG_HDR 0xe
#define PCI_CFG_BIST 0xf
#define PCI_CFG_BAR0 0x10
#define PCI_CFG_BAR1 0x14
#define PCI_CFG_BAR2 0x18
#define PCI_CFG_BAR3 0x1c
#define PCI_CFG_BAR4 0x20
#define PCI_CFG_BAR5 0x24
#define PCI_CFG_CIS 0x28
#define PCI_CFG_SVID 0x2c
#define PCI_CFG_SSID 0x2e
#define PCI_CFG_ROMBAR 0x30
#define PCI_CFG_CAPPTR 0x34
#define PCI_CFG_INT 0x3c
#define PCI_CFG_PIN 0x3d
#define PCI_CFG_MINGNT 0x3e
#define PCI_CFG_MAXLAT 0x3f
/* Classes and subclasses */
typedef enum {
PCI_CLASS_OLD = 0,
PCI_CLASS_DASDI,
PCI_CLASS_NET,
PCI_CLASS_DISPLAY,
PCI_CLASS_MMEDIA,
PCI_CLASS_MEMORY,
PCI_CLASS_BRIDGE,
PCI_CLASS_COMM,
PCI_CLASS_BASE,
PCI_CLASS_INPUT,
PCI_CLASS_DOCK,
PCI_CLASS_CPU,
PCI_CLASS_SERIAL,
PCI_CLASS_INTELLIGENT = 0xe,
PCI_CLASS_SATELLITE,
PCI_CLASS_CRYPT,
PCI_CLASS_DSP,
PCI_CLASS_XOR = 0xfe
} pci_classes;
typedef enum {
PCI_DASDI_SCSI,
PCI_DASDI_IDE,
PCI_DASDI_FLOPPY,
PCI_DASDI_IPI,
PCI_DASDI_RAID,
PCI_DASDI_OTHER = 0x80
} pci_dasdi_subclasses;
typedef enum {
PCI_NET_ETHER,
PCI_NET_TOKEN,
PCI_NET_FDDI,
PCI_NET_ATM,
PCI_NET_OTHER = 0x80
} pci_net_subclasses;
typedef enum {
PCI_DISPLAY_VGA,
PCI_DISPLAY_XGA,
PCI_DISPLAY_3D,
PCI_DISPLAY_OTHER = 0x80
} pci_display_subclasses;
typedef enum {
PCI_MMEDIA_VIDEO,
PCI_MMEDIA_AUDIO,
PCI_MMEDIA_PHONE,
PCI_MEDIA_OTHER = 0x80
} pci_mmedia_subclasses;
typedef enum {
PCI_MEMORY_RAM,
PCI_MEMORY_FLASH,
PCI_MEMORY_OTHER = 0x80
} pci_memory_subclasses;
typedef enum {
PCI_BRIDGE_HOST,
PCI_BRIDGE_ISA,
PCI_BRIDGE_EISA,
PCI_BRIDGE_MC,
PCI_BRIDGE_PCI,
PCI_BRIDGE_PCMCIA,
PCI_BRIDGE_NUBUS,
PCI_BRIDGE_CARDBUS,
PCI_BRIDGE_RACEWAY,
PCI_BRIDGE_OTHER = 0x80
} pci_bridge_subclasses;
typedef enum {
PCI_COMM_UART,
PCI_COMM_PARALLEL,
PCI_COMM_MULTIUART,
PCI_COMM_MODEM,
PCI_COMM_OTHER = 0x80
} pci_comm_subclasses;
typedef enum {
PCI_BASE_PIC,
PCI_BASE_DMA,
PCI_BASE_TIMER,
PCI_BASE_RTC,
PCI_BASE_PCI_HOTPLUG,
PCI_BASE_OTHER = 0x80
} pci_base_subclasses;
typedef enum {
PCI_INPUT_KBD,
PCI_INPUT_PEN,
PCI_INPUT_MOUSE,
PCI_INPUT_SCANNER,
PCI_INPUT_GAMEPORT,
PCI_INPUT_OTHER = 0x80
} pci_input_subclasses;
typedef enum {
PCI_DOCK_GENERIC,
PCI_DOCK_OTHER = 0x80
} pci_dock_subclasses;
typedef enum {
PCI_CPU_386,
PCI_CPU_486,
PCI_CPU_PENTIUM,
PCI_CPU_ALPHA = 0x10,
PCI_CPU_POWERPC = 0x20,
PCI_CPU_MIPS = 0x30,
PCI_CPU_COPROC = 0x40,
PCI_CPU_OTHER = 0x80
} pci_cpu_subclasses;
typedef enum {
PCI_SERIAL_IEEE1394,
PCI_SERIAL_ACCESS,
PCI_SERIAL_SSA,
PCI_SERIAL_USB,
PCI_SERIAL_FIBER,
PCI_SERIAL_SMBUS,
PCI_SERIAL_OTHER = 0x80
} pci_serial_subclasses;
typedef enum {
PCI_INTELLIGENT_I2O
} pci_intelligent_subclasses;
typedef enum {
PCI_SATELLITE_TV,
PCI_SATELLITE_AUDIO,
PCI_SATELLITE_VOICE,
PCI_SATELLITE_DATA,
PCI_SATELLITE_OTHER = 0x80
} pci_satellite_subclasses;
typedef enum {
PCI_CRYPT_NETWORK,
PCI_CRYPT_ENTERTAINMENT,
PCI_CRYPT_OTHER = 0x80
} pci_crypt_subclasses;
typedef enum {
PCI_DSP_DPIO,
PCI_DSP_OTHER = 0x80
} pci_dsp_subclasses;
typedef enum {
PCI_XOR_QDMA,
PCI_XOR_OTHER = 0x80
} pci_xor_subclasses;
/* Header types */
#define PCI_HEADER_MULTI 0x80
#define PCI_HEADER_MASK 0x7f
typedef enum {
PCI_HEADER_NORMAL,
PCI_HEADER_BRIDGE,
PCI_HEADER_CARDBUS
} pci_header_types;
/* Overlay for a PCI-to-PCI bridge */
#define PPB_RSVDA_MAX 2
#define PPB_RSVDD_MAX 8
typedef struct _ppb_config_regs {
uint16 vendor;
uint16 device;
uint16 command;
uint16 status;
uint8 rev_id;
uint8 prog_if;
uint8 sub_class;
uint8 base_class;
uint8 cache_line_size;
uint8 latency_timer;
uint8 header_type;
uint8 bist;
uint32 rsvd_a[PPB_RSVDA_MAX];
uint8 prim_bus;
uint8 sec_bus;
uint8 sub_bus;
uint8 sec_lat;
uint8 io_base;
uint8 io_lim;
uint16 sec_status;
uint16 mem_base;
uint16 mem_lim;
uint16 pf_mem_base;
uint16 pf_mem_lim;
uint32 pf_mem_base_hi;
uint32 pf_mem_lim_hi;
uint16 io_base_hi;
uint16 io_lim_hi;
uint16 subsys_vendor;
uint16 subsys_id;
uint32 rsvd_b;
uint8 rsvd_c;
uint8 int_pin;
uint16 bridge_ctrl;
uint8 chip_ctrl;
uint8 diag_ctrl;
uint16 arb_ctrl;
uint32 rsvd_d[PPB_RSVDD_MAX];
uint8 dev_dep[192];
} ppb_config_regs;
/* PCI CAPABILITY DEFINES */
#define PCI_CAP_POWERMGMTCAP_ID 0x01
#define PCI_CAP_MSICAP_ID 0x05
#define PCI_CAP_VENDSPEC_ID 0x09
#define PCI_CAP_PCIECAP_ID 0x10
/* Data structure to define the Message Signalled Interrupt facility
* Valid for PCI and PCIE configurations
*/
typedef struct _pciconfig_cap_msi {
uint8 capID;
uint8 nextptr;
uint16 msgctrl;
uint32 msgaddr;
} pciconfig_cap_msi;
/* Data structure to define the Power managment facility
* Valid for PCI and PCIE configurations
*/
typedef struct _pciconfig_cap_pwrmgmt {
uint8 capID;
uint8 nextptr;
uint16 pme_cap;
uint16 pme_sts_ctrl;
uint8 pme_bridge_ext;
uint8 data;
} pciconfig_cap_pwrmgmt;
#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */
#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */
#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */
#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */
/* Data structure to define the PCIE capability */
typedef struct _pciconfig_cap_pcie {
uint8 capID;
uint8 nextptr;
uint16 pcie_cap;
uint32 dev_cap;
uint16 dev_ctrl;
uint16 dev_status;
uint32 link_cap;
uint16 link_ctrl;
uint16 link_status;
uint32 slot_cap;
uint16 slot_ctrl;
uint16 slot_status;
uint16 root_ctrl;
uint16 root_cap;
uint32 root_status;
} pciconfig_cap_pcie;
/* PCIE Enhanced CAPABILITY DEFINES */
#define PCIE_EXTCFG_OFFSET 0x100
#define PCIE_ADVERRREP_CAPID 0x0001
#define PCIE_VC_CAPID 0x0002
#define PCIE_DEVSNUM_CAPID 0x0003
#define PCIE_PWRBUDGET_CAPID 0x0004
/* PCIE Extended configuration */
#define PCIE_ADV_CORR_ERR_MASK 0x114
#define CORR_ERR_RE (1 << 0) /* Receiver */
#define CORR_ERR_BT (1 << 6) /* Bad TLP */
#define CORR_ERR_BD (1 << 7) /* Bad DLLP */
#define CORR_ERR_RR (1 << 8) /* REPLAY_NUM rollover */
#define CORR_ERR_RT (1 << 12) /* Reply timer timeout */
#define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \
CORR_ERR_RR | CORR_ERR_RT)
/* PCIE Root Control Register bits (Host mode only) */
#define PCIE_RC_CORR_SERR_EN 0x0001
#define PCIE_RC_NONFATAL_SERR_EN 0x0002
#define PCIE_RC_FATAL_SERR_EN 0x0004
#define PCIE_RC_PME_INT_EN 0x0008
#define PCIE_RC_CRS_EN 0x0010
/* PCIE Root Capability Register bits (Host mode only) */
#define PCIE_RC_CRS_VISIBILITY 0x0001
/* Header to define the PCIE specific capabilities in the extended config space */
typedef struct _pcie_enhanced_caphdr {
uint16 capID;
uint16 cap_ver:4;
uint16 next_ptr:12;
} pcie_enhanced_caphdr;
/* Everything below is BRCM HND proprietary */
/* Brcm PCI configuration registers */
#define cap_list rsvd_a[0]
#define bar0_window dev_dep[0x80 - 0x40]
#define bar1_window dev_dep[0x84 - 0x40]
#define sprom_control dev_dep[0x88 - 0x40]
#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
#define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */
#define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */
#define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */
#define PCI_BAR0_WIN2 0xac /* backplane addres space accessed by second 4KB of BAR0 */
#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
* 8KB window, so their address is the "regular"
* address plus 4K
*/
#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
/* On AI chips we have a second window to map DMP regs are mapped: */
#define PCI_16KB0_WIN2_OFFSET (4 * 1024) /* bar0 + 4K is "Window 2" */
/* PCI_INT_STATUS */
#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
/* PCI_INT_MASK */
#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
/* PCI_SPROM_CONTROL */
#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
#define SPROM_LOCKED 0x08 /* SPROM Locked */
#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
#define SPROM_WRITEEN 0x10 /* SPROM write enable */
#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
#define SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */
#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
/* Bits in PCI command and status regs */
#define PCI_CMD_IO 0x00000001 /* I/O enable */
#define PCI_CMD_MEMORY 0x00000002 /* Memory enable */
#define PCI_CMD_MASTER 0x00000004 /* Master enable */
#define PCI_CMD_SPECIAL 0x00000008 /* Special cycles enable */
#define PCI_CMD_INVALIDATE 0x00000010 /* Invalidate? */
#define PCI_CMD_VGA_PAL 0x00000040 /* VGA Palate */
#define PCI_STAT_TA 0x08000000 /* target abort status */
#endif /* _h_pcicfg_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _PCIE_CORE_H
#define _PCIE_CORE_H
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif
/* PCIE Enumeration space offsets */
#define PCIE_CORE_CONFIG_OFFSET 0x0
#define PCIE_FUNC0_CONFIG_OFFSET 0x400
#define PCIE_FUNC1_CONFIG_OFFSET 0x500
#define PCIE_FUNC2_CONFIG_OFFSET 0x600
#define PCIE_FUNC3_CONFIG_OFFSET 0x700
#define PCIE_SPROM_SHADOW_OFFSET 0x800
#define PCIE_SBCONFIG_OFFSET 0xE00
/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
#define PCIE_DEV_BAR0_SIZE 0x4000
#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
/* different register spaces to access thr'u pcie indirect access */
#define PCIE_CONFIGREGS 1 /* Access to config space */
#define PCIE_PCIEREGS 2 /* Access to pcie registers */
/* SB side: PCIE core and host control registers */
typedef struct sbpcieregs {
uint32 control; /* host mode only */
uint32 PAD[2];
uint32 biststatus; /* bist Status: 0x00C */
uint32 gpiosel; /* PCIE gpio sel: 0x010 */
uint32 gpioouten; /* PCIE gpio outen: 0x14 */
uint32 PAD[2];
uint32 intstatus; /* Interrupt status: 0x20 */
uint32 intmask; /* Interrupt mask: 0x24 */
uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
uint32 PAD[53];
uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
uint32 PAD[5];
/* pcie core supports in direct access to config space */
uint32 configaddr; /* pcie config space access: Address field: 0x120 */
uint32 configdata; /* pcie config space access: Data field: 0x124 */
/* mdio access to serdes */
uint32 mdiocontrol; /* controls the mdio access: 0x128 */
uint32 mdiodata; /* Data to the mdio access: 0x12c */
/* pcie protocol phy/dllp/tlp register indirect access mechanism */
uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */
uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
uint32 PAD[177];
uint32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */
uint16 sprom[64]; /* SPROM shadow Area */
} sbpcieregs_t;
/* PCI control */
#define PCIE_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
#define PCIE_RST 0x02 /* Value driven out to pin */
#define PCIE_CFGADDR 0x120 /* offsetof(configaddr) */
#define PCIE_CFGDATA 0x124 /* offsetof(configdata) */
/* Interrupt status/mask */
#define PCIE_INTA 0x01 /* PCIE INTA message is received */
#define PCIE_INTB 0x02 /* PCIE INTB message is received */
#define PCIE_INTFATAL 0x04 /* PCIE INTFATAL message is received */
#define PCIE_INTNFATAL 0x08 /* PCIE INTNONFATAL message is received */
#define PCIE_INTCORR 0x10 /* PCIE INTCORR message is received */
#define PCIE_INTPME 0x20 /* PCIE INTPME message is received */
/* SB to PCIE translation masks */
#define SBTOPCIE0_MASK 0xfc000000
#define SBTOPCIE1_MASK 0xfc000000
#define SBTOPCIE2_MASK 0xc0000000
/* Access type bits (0:1) */
#define SBTOPCIE_MEM 0
#define SBTOPCIE_IO 1
#define SBTOPCIE_CFG0 2
#define SBTOPCIE_CFG1 3
/* Prefetch enable bit 2 */
#define SBTOPCIE_PF 4
/* Write Burst enable for memory write bit 3 */
#define SBTOPCIE_WR_BURST 8
/* config access */
#define CONFIGADDR_FUNC_MASK 0x7000
#define CONFIGADDR_FUNC_SHF 12
#define CONFIGADDR_REG_MASK 0x0FFF
#define CONFIGADDR_REG_SHF 0
#define PCIE_CONFIG_INDADDR(f, r) \
((((f) & CONFIGADDR_FUNC_MASK) << CONFIGADDR_FUNC_SHF) | \
(((r) & CONFIGADDR_REG_MASK) << CONFIGADDR_REG_SHF))
/* PCIE protocol regs Indirect Address */
#define PCIEADDR_PROT_MASK 0x300
#define PCIEADDR_PROT_SHF 8
#define PCIEADDR_PL_TLP 0
#define PCIEADDR_PL_DLLP 1
#define PCIEADDR_PL_PLP 2
/* PCIE protocol PHY diagnostic registers */
#define PCIE_PLP_MODEREG 0x200 /* Mode */
#define PCIE_PLP_STATUSREG 0x204 /* Status */
#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
#define PCIE_PLP_ATTNREG 0x218 /* Attention */
#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */
#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
/* PCIE protocol DLLP diagnostic registers */
#define PCIE_DLLP_LCREG 0x100 /* Link Control */
#define PCIE_DLLP_LSREG 0x104 /* Link Status */
#define PCIE_DLLP_LAREG 0x108 /* Link Attention */
#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
#define PCIE_DLLP_LRREG 0x120 /* Link Replay */
#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */
#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
#define PCIE_DLLP_TESTREG 0x14C /* Test */
#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
#define PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
#define PCIE_DLLP_LSREG_LINKUP (1 << 16)
/* PCIE protocol TLP diagnostic registers */
#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */
#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */
#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */
#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */
#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */
#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */
#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */
#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */
#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */
#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */
#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */
#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */
#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */
#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */
#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */
#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */
#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */
#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */
#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */
#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */
#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */
#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */
#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */
#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */
#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
/* MDIO control */
#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
#define MDIOCTL_DIVISOR_VAL 0x2
#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
/* MDIO Data */
#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
#define MDIODATA_TA 0x00020000 /* Turnaround */
#define MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
#define MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
#define MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
#define MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
#define MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
#define MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
#define MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
#define MDIODATA_WRITE 0x10000000 /* write Transaction */
#define MDIODATA_READ 0x20000000 /* Read Transaction */
#define MDIODATA_START 0x40000000 /* start of Transaction */
#define MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
#define MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
/* MDIO devices (SERDES modules)
* unlike old pcie cores (rev < 10), rev10 pcie serde organizes registers into a few blocks.
* two layers mapping (blockidx, register offset) is required
*/
#define MDIO_DEV_IEEE0 0x000
#define MDIO_DEV_IEEE1 0x001
#define MDIO_DEV_BLK0 0x800
#define MDIO_DEV_BLK1 0x801
#define MDIO_DEV_BLK2 0x802
#define MDIO_DEV_BLK3 0x803
#define MDIO_DEV_BLK4 0x804
#define MDIO_DEV_TXPLL 0x808 /* TXPLL register block idx */
#define MDIO_DEV_TXCTRL0 0x820
#define MDIO_DEV_SERDESID 0x831
#define MDIO_DEV_RXCTRL0 0x840
/* serdes regs (rev < 10) */
#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
/* SERDES RX registers */
#define SERDES_RX_CTRL 1 /* Rx cntrl */
#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
#define SERDES_RX_CDR 6 /* CDR */
#define SERDES_RX_CDRBW 7 /* CDR BW */
/* SERDES RX control register */
#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
/* SERDES PLL registers */
#define SERDES_PLL_CTRL 1 /* PLL control reg */
#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
/* Power management threshold */
#define PCIE_L0THRESHOLDTIME_MASK 0xFF00 /* bits 0 - 7 */
#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */
#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */
#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */
#define PCIE_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
/* SPROM offsets */
#define SRSH_ASPM_OFFSET 4 /* word 4 */
#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */
#define SRSH_ASPM_L1_ENB 0x10 /* bit 4 */
#define SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */
#define SRSH_PCIE_MISC_CONFIG 5 /* word 5 */
#define SRSH_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
#define SRSH_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
#define SRSH_CLKREQ_OFFSET_REV8 52 /* word 52 for srom rev 8 */
#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */
#define SRSH_BD_OFFSET 6 /* word 6 */
#define SRSH_AUTOINIT_OFFSET 18 /* auto initialization enable */
/* Linkcontrol reg offset in PCIE Cap */
#define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */
#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */
#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */
#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */
#define PCIE_ASPM_ENAB 3 /* ASPM L0s & L1 in linkctrl */
#define PCIE_ASPM_L1_ENAB 2 /* ASPM L0s & L1 in linkctrl */
#define PCIE_ASPM_L0s_ENAB 1 /* ASPM L0s & L1 in linkctrl */
#define PCIE_ASPM_DISAB 0 /* ASPM L0s & L1 in linkctrl */
/* Status reg PCIE_PLP_STATUSREG */
#define PCIE_PLP_POLARITYINV_STAT 0x10
#endif /* _PCIE_CORE_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _802_11e_H_
#define _802_11e_H_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
#include <packed_section_start.h>
#define WME_TSPEC_HDR_LEN 2
#define WME_TSPEC_BODY_OFF 2
#define WME_CATEGORY_CODE_OFFSET 0
#define WME_ACTION_CODE_OFFSET 1
#define WME_TOKEN_CODE_OFFSET 2
#define WME_STATUS_CODE_OFFSET 3
BWL_PRE_PACKED_STRUCT struct tsinfo {
uint8 octets[3];
} BWL_POST_PACKED_STRUCT;
typedef struct tsinfo tsinfo_t;
typedef BWL_PRE_PACKED_STRUCT struct tspec {
uint8 oui[DOT11_OUI_LEN];
uint8 type;
uint8 subtype;
uint8 version;
tsinfo_t tsinfo;
uint16 nom_msdu_size;
uint16 max_msdu_size;
uint32 min_srv_interval;
uint32 max_srv_interval;
uint32 inactivity_interval;
uint32 suspension_interval;
uint32 srv_start_time;
uint32 min_data_rate;
uint32 mean_data_rate;
uint32 peak_data_rate;
uint32 max_burst_size;
uint32 delay_bound;
uint32 min_phy_rate;
uint16 surplus_bw;
uint16 medium_time;
} BWL_POST_PACKED_STRUCT tspec_t;
#define WME_TSPEC_LEN (sizeof(tspec_t))
#define TS_INFO_TID_SHIFT 1
#define TS_INFO_TID_MASK (0xf << TS_INFO_TID_SHIFT)
#define TS_INFO_CONTENTION_SHIFT 7
#define TS_INFO_CONTENTION_MASK (0x1 << TS_INFO_CONTENTION_SHIFT)
#define TS_INFO_DIRECTION_SHIFT 5
#define TS_INFO_DIRECTION_MASK (0x3 << TS_INFO_DIRECTION_SHIFT)
#define TS_INFO_PSB_SHIFT 2
#define TS_INFO_PSB_MASK (1 << TS_INFO_PSB_SHIFT)
#define TS_INFO_UPLINK (0 << TS_INFO_DIRECTION_SHIFT)
#define TS_INFO_DOWNLINK (1 << TS_INFO_DIRECTION_SHIFT)
#define TS_INFO_BIDIRECTIONAL (3 << TS_INFO_DIRECTION_SHIFT)
#define TS_INFO_USER_PRIO_SHIFT 3
#define TS_INFO_USER_PRIO_MASK (0x7 << TS_INFO_USER_PRIO_SHIFT)
#define WLC_CAC_GET_TID(pt) ((((pt).octets[0]) & \
TS_INFO_TID_MASK) >> TS_INFO_TID_SHIFT)
#define WLC_CAC_GET_DIR(pt) ((((pt).octets[0]) & \
TS_INFO_DIRECTION_MASK) >> TS_INFO_DIRECTION_SHIFT)
#define WLC_CAC_GET_PSB(pt) ((((pt).octets[1]) & \
TS_INFO_PSB_MASK) >> TS_INFO_PSB_SHIFT)
#define WLC_CAC_GET_USER_PRIO(pt) ((((pt).octets[1]) & \
TS_INFO_USER_PRIO_MASK) >> TS_INFO_USER_PRIO_SHIFT)
#define WLC_CAC_SET_TID(pt, id) ((((pt).octets[0]) & (~TS_INFO_TID_MASK)) | \
((id) << TS_INFO_TID_SHIFT))
#define WLC_CAC_SET_USER_PRIO(pt, prio) ((((pt).octets[0]) & \
(~TS_INFO_USER_PRIO_MASK)) | ((prio) << TS_INFO_USER_PRIO_SHIFT))
#define QBSS_LOAD_IE_LEN 5
#define QBSS_LOAD_AAC_OFF 3
#define CAC_ADDTS_RESP_TIMEOUT 300
#define DOT11E_STATUS_ADMISSION_ACCEPTED 0
#define DOT11E_STATUS_ADDTS_INVALID_PARAM 1
#define DOT11E_STATUS_ADDTS_REFUSED_NSBW 3
#define DOT11E_STATUS_ADDTS_REFUSED_AWHILE 47
#define DOT11E_STATUS_QSTA_LEAVE_QBSS 36
#define DOT11E_STATUS_END_TS 37
#define DOT11E_STATUS_UNKNOWN_TS 38
#define DOT11E_STATUS_QSTA_REQ_TIMEOUT 39
#include <packed_section_end.h>
#endif /* _802_11e_H_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _802_1_D_
#define _802_1_D_
#define PRIO_8021D_NONE 2
#define PRIO_8021D_BK 1
#define PRIO_8021D_BE 0
#define PRIO_8021D_EE 3
#define PRIO_8021D_CL 4
#define PRIO_8021D_VI 5
#define PRIO_8021D_VO 6
#define PRIO_8021D_NC 7
#define MAXPRIO 7
#define NUMPRIO (MAXPRIO + 1)
#define ALLPRIO -1
#define PRIO2PREC(prio) \
(((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
((prio^2)) : (prio))
#endif /* _802_1_D_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _BCMEVENT_H_
#define _BCMEVENT_H_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
#include <packed_section_start.h>
#define BCM_EVENT_MSG_VERSION 1
#define BCM_MSG_IFNAME_MAX 16
#define WLC_EVENT_MSG_LINK 0x01
#define WLC_EVENT_MSG_FLUSHTXQ 0x02
#define WLC_EVENT_MSG_GROUP 0x04
typedef BWL_PRE_PACKED_STRUCT struct {
uint16 version;
uint16 flags;
uint32 event_type;
uint32 status;
uint32 reason;
uint32 auth_type;
uint32 datalen;
struct ether_addr addr;
char ifname[BCM_MSG_IFNAME_MAX];
} BWL_POST_PACKED_STRUCT wl_event_msg_t;
#define BCM_MSG_LEN (sizeof(bcm_event_t) - sizeof(bcmeth_hdr_t) - \
sizeof(struct ether_header))
#define WLC_E_SET_SSID 0
#define WLC_E_JOIN 1
#define WLC_E_START 2
#define WLC_E_AUTH 3
#define WLC_E_AUTH_IND 4
#define WLC_E_DEAUTH 5
#define WLC_E_DEAUTH_IND 6
#define WLC_E_ASSOC 7
#define WLC_E_ASSOC_IND 8
#define WLC_E_REASSOC 9
#define WLC_E_REASSOC_IND 10
#define WLC_E_DISASSOC 11
#define WLC_E_DISASSOC_IND 12
#define WLC_E_QUIET_START 13
#define WLC_E_QUIET_END 14
#define WLC_E_BEACON_RX 15
#define WLC_E_LINK 16
#define WLC_E_MIC_ERROR 17
#define WLC_E_NDIS_LINK 18
#define WLC_E_ROAM 19
#define WLC_E_TXFAIL 20
#define WLC_E_PMKID_CACHE 21
#define WLC_E_RETROGRADE_TSF 22
#define WLC_E_PRUNE 23
#define WLC_E_AUTOAUTH 24
#define WLC_E_EAPOL_MSG 25
#define WLC_E_SCAN_COMPLETE 26
#define WLC_E_ADDTS_IND 27
#define WLC_E_DELTS_IND 28
#define WLC_E_BCNSENT_IND 29
#define WLC_E_BCNRX_MSG 30
#define WLC_E_BCNLOST_MSG 31
#define WLC_E_ROAM_PREP 32
#define WLC_E_PFN_NET_FOUND 33
#define WLC_E_PFN_NET_LOST 34
#define WLC_E_RESET_COMPLETE 35
#define WLC_E_JOIN_START 36
#define WLC_E_ROAM_START 37
#define WLC_E_ASSOC_START 38
#define WLC_E_IBSS_ASSOC 39
#define WLC_E_RADIO 40
#define WLC_E_PSM_WATCHDOG 41
#define WLC_E_PROBREQ_MSG 44
#define WLC_E_SCAN_CONFIRM_IND 45
#define WLC_E_PSK_SUP 46
#define WLC_E_COUNTRY_CODE_CHANGED 47
#define WLC_E_EXCEEDED_MEDIUM_TIME 48
#define WLC_E_ICV_ERROR 49
#define WLC_E_UNICAST_DECODE_ERROR 50
#define WLC_E_MULTICAST_DECODE_ERROR 51
#define WLC_E_TRACE 52
#define WLC_E_IF 54
#define WLC_E_RSSI 56
#define WLC_E_PFN_SCAN_COMPLETE 57
#define WLC_E_EXTLOG_MSG 58
#define WLC_E_ACTION_FRAME 59
#define WLC_E_ACTION_FRAME_COMPLETE 60
#define WLC_E_PRE_ASSOC_IND 61
#define WLC_E_PRE_REASSOC_IND 62
#define WLC_E_CHANNEL_ADOPTED 63
#define WLC_E_AP_STARTED 64
#define WLC_E_DFS_AP_STOP 65
#define WLC_E_DFS_AP_RESUME 66
#define WLC_E_RESERVED1 67
#define WLC_E_RESERVED2 68
#define WLC_E_ESCAN_RESULT 69
#define WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE 70
#define WLC_E_DCS_REQUEST 73
#define WLC_E_FIFO_CREDIT_MAP 74
#define WLC_E_LAST 75
typedef struct {
uint event;
const char *name;
} bcmevent_name_t;
extern const bcmevent_name_t bcmevent_names[];
extern const int bcmevent_names_size;
#define WLC_E_STATUS_SUCCESS 0
#define WLC_E_STATUS_FAIL 1
#define WLC_E_STATUS_TIMEOUT 2
#define WLC_E_STATUS_NO_NETWORKS 3
#define WLC_E_STATUS_ABORT 4
#define WLC_E_STATUS_NO_ACK 5
#define WLC_E_STATUS_UNSOLICITED 6
#define WLC_E_STATUS_ATTEMPT 7
#define WLC_E_STATUS_PARTIAL 8
#define WLC_E_STATUS_NEWSCAN 9
#define WLC_E_STATUS_NEWASSOC 10
#define WLC_E_STATUS_11HQUIET 11
#define WLC_E_STATUS_SUPPRESS 12
#define WLC_E_STATUS_NOCHANS 13
#define WLC_E_STATUS_CS_ABORT 15
#define WLC_E_STATUS_ERROR 16
#define WLC_E_REASON_INITIAL_ASSOC 0
#define WLC_E_REASON_LOW_RSSI 1
#define WLC_E_REASON_DEAUTH 2
#define WLC_E_REASON_DISASSOC 3
#define WLC_E_REASON_BCNS_LOST 4
#define WLC_E_REASON_MINTXRATE 9
#define WLC_E_REASON_TXFAIL 10
#define WLC_E_REASON_FAST_ROAM_FAILED 5
#define WLC_E_REASON_DIRECTED_ROAM 6
#define WLC_E_REASON_TSPEC_REJECTED 7
#define WLC_E_REASON_BETTER_AP 8
#define WLC_E_PRUNE_ENCR_MISMATCH 1
#define WLC_E_PRUNE_BCAST_BSSID 2
#define WLC_E_PRUNE_MAC_DENY 3
#define WLC_E_PRUNE_MAC_NA 4
#define WLC_E_PRUNE_REG_PASSV 5
#define WLC_E_PRUNE_SPCT_MGMT 6
#define WLC_E_PRUNE_RADAR 7
#define WLC_E_RSN_MISMATCH 8
#define WLC_E_PRUNE_NO_COMMON_RATES 9
#define WLC_E_PRUNE_BASIC_RATES 10
#define WLC_E_PRUNE_CIPHER_NA 12
#define WLC_E_PRUNE_KNOWN_STA 13
#define WLC_E_PRUNE_WDS_PEER 15
#define WLC_E_PRUNE_QBSS_LOAD 16
#define WLC_E_PRUNE_HOME_AP 17
#define WLC_E_SUP_OTHER 0
#define WLC_E_SUP_DECRYPT_KEY_DATA 1
#define WLC_E_SUP_BAD_UCAST_WEP128 2
#define WLC_E_SUP_BAD_UCAST_WEP40 3
#define WLC_E_SUP_UNSUP_KEY_LEN 4
#define WLC_E_SUP_PW_KEY_CIPHER 5
#define WLC_E_SUP_MSG3_TOO_MANY_IE 6
#define WLC_E_SUP_MSG3_IE_MISMATCH 7
#define WLC_E_SUP_NO_INSTALL_FLAG 8
#define WLC_E_SUP_MSG3_NO_GTK 9
#define WLC_E_SUP_GRP_KEY_CIPHER 10
#define WLC_E_SUP_GRP_MSG1_NO_GTK 11
#define WLC_E_SUP_GTK_DECRYPT_FAIL 12
#define WLC_E_SUP_SEND_FAIL 13
#define WLC_E_SUP_DEAUTH 14
typedef struct wl_event_data_if {
uint8 ifidx;
uint8 opcode;
uint8 reserved;
uint8 bssidx;
uint8 role;
} wl_event_data_if_t;
#define WLC_E_IF_ADD 1
#define WLC_E_IF_DEL 2
#define WLC_E_IF_CHANGE 3
#define WLC_E_IF_ROLE_STA 0
#define WLC_E_IF_ROLE_AP 1
#define WLC_E_IF_ROLE_WDS 2
#define WLC_E_LINK_BCN_LOSS 1
#define WLC_E_LINK_DISASSOC 2
#define WLC_E_LINK_ASSOC_REC 3
#define WLC_E_LINK_BSSCFG_DIS 4
#include <packed_section_end.h>
#endif /* _BCMEVENT_H_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _NET_ETHERNET_H_
#define _NET_ETHERNET_H_
#ifndef _TYPEDEFS_H_
#include "typedefs.h"
#endif
#include <packed_section_start.h>
#define ETHER_ADDR_LEN 6
#define ETHER_TYPE_LEN 2
#define ETHER_CRC_LEN 4
#define ETHER_HDR_LEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
#define ETHER_MIN_LEN 64
#define ETHER_MIN_DATA 46
#define ETHER_MAX_LEN 1518
#define ETHER_MAX_DATA 1500
#define ETHER_TYPE_MIN 0x0600
#define ETHER_TYPE_IP 0x0800
#define ETHER_TYPE_ARP 0x0806
#define ETHER_TYPE_8021Q 0x8100
#define ETHER_TYPE_BRCM 0x886c
#define ETHER_TYPE_802_1X 0x888e
#define ETHER_TYPE_802_1X_PREAUTH 0x88c7
#define ETHER_DEST_OFFSET (0 * ETHER_ADDR_LEN)
#define ETHER_SRC_OFFSET (1 * ETHER_ADDR_LEN)
#define ETHER_TYPE_OFFSET (2 * ETHER_ADDR_LEN)
#define ETHER_IS_VALID_LEN(foo) \
((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
#define ETHER_FILL_MCAST_ADDR_FROM_IP(ea, mgrp_ip) { \
((uint8 *)ea)[0] = 0x01; \
((uint8 *)ea)[1] = 0x00; \
((uint8 *)ea)[2] = 0x5e; \
((uint8 *)ea)[3] = ((mgrp_ip) >> 16) & 0x7f; \
((uint8 *)ea)[4] = ((mgrp_ip) >> 8) & 0xff; \
((uint8 *)ea)[5] = ((mgrp_ip) >> 0) & 0xff; \
}
BWL_PRE_PACKED_STRUCT struct ether_header {
uint8 ether_dhost[ETHER_ADDR_LEN];
uint8 ether_shost[ETHER_ADDR_LEN];
uint16 ether_type;
} BWL_POST_PACKED_STRUCT;
BWL_PRE_PACKED_STRUCT struct ether_addr {
uint8 octet[ETHER_ADDR_LEN];
} BWL_POST_PACKED_STRUCT;
#define ETHER_SET_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] | 2))
#define ETHER_IS_LOCALADDR(ea) (((uint8 *)(ea))[0] & 2)
#define ETHER_CLR_LOCALADDR(ea) (((uint8 *)(ea))[0] = \
(((uint8 *)(ea))[0] & 0xd))
#define ETHER_TOGGLE_LOCALADDR(ea) (((uint8 *)(ea))[0] = \
(((uint8 *)(ea))[0] ^ 2))
#define ETHER_SET_UNICAST(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] & ~1))
#define ETHER_ISMULTI(ea) (((const uint8 *)(ea))[0] & 1)
#define ether_cmp(a, b) (!(((short*)a)[0] == ((short*)b)[0]) | \
!(((short*)a)[1] == ((short*)b)[1]) | \
!(((short*)a)[2] == ((short*)b)[2]))
#define ether_copy(s, d) { \
((short*)d)[0] = ((short*)s)[0]; \
((short*)d)[1] = ((short*)s)[1]; \
((short*)d)[2] = ((short*)s)[2]; }
static const struct ether_addr ether_bcast = { {255, 255, 255, 255, 255, 255} };
static const struct ether_addr ether_null = { {0, 0, 0, 0, 0, 0} };
#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
((uint8 *)(ea))[1] & \
((uint8 *)(ea))[2] & \
((uint8 *)(ea))[3] & \
((uint8 *)(ea))[4] & \
((uint8 *)(ea))[5]) == 0xff)
#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
((uint8 *)(ea))[1] | \
((uint8 *)(ea))[2] | \
((uint8 *)(ea))[3] | \
((uint8 *)(ea))[4] | \
((uint8 *)(ea))[5]) == 0)
#define ETHER_MOVE_HDR(d, s) \
do { \
struct ether_header t; \
t = *(struct ether_header *)(s); \
*(struct ether_header *)(d) = t; \
} while (0)
#include <packed_section_end.h>
#endif /* _NET_ETHERNET_H_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _proto_wpa_h_
#define _proto_wpa_h_
#include <typedefs.h>
#include <proto/ethernet.h>
#include <packed_section_start.h>
#define DOT11_RC_INVALID_WPA_IE 13
#define DOT11_RC_MIC_FAILURE 14
#define DOT11_RC_4WH_TIMEOUT 15
#define DOT11_RC_GTK_UPDATE_TIMEOUT 16
#define DOT11_RC_WPA_IE_MISMATCH 17
#define DOT11_RC_INVALID_MC_CIPHER 18
#define DOT11_RC_INVALID_UC_CIPHER 19
#define DOT11_RC_INVALID_AKMP 20
#define DOT11_RC_BAD_WPA_VERSION 21
#define DOT11_RC_INVALID_WPA_CAP 22
#define DOT11_RC_8021X_AUTH_FAIL 23
#define WPA2_PMKID_LEN 16
typedef BWL_PRE_PACKED_STRUCT struct {
uint8 tag;
uint8 length;
uint8 oui[3];
uint8 oui_type;
BWL_PRE_PACKED_STRUCT struct {
uint8 low;
uint8 high;
} BWL_POST_PACKED_STRUCT version;
} BWL_POST_PACKED_STRUCT wpa_ie_fixed_t;
#define WPA_IE_OUITYPE_LEN 4
#define WPA_IE_FIXED_LEN 8
#define WPA_IE_TAG_FIXED_LEN 6
typedef BWL_PRE_PACKED_STRUCT struct {
uint8 tag;
uint8 length;
BWL_PRE_PACKED_STRUCT struct {
uint8 low;
uint8 high;
} BWL_POST_PACKED_STRUCT version;
} BWL_POST_PACKED_STRUCT wpa_rsn_ie_fixed_t;
#define WPA_RSN_IE_FIXED_LEN 4
#define WPA_RSN_IE_TAG_FIXED_LEN 2
typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN];
typedef BWL_PRE_PACKED_STRUCT struct {
uint8 oui[3];
uint8 type;
} BWL_POST_PACKED_STRUCT wpa_suite_t, wpa_suite_mcast_t;
#define WPA_SUITE_LEN 4
typedef BWL_PRE_PACKED_STRUCT struct {
BWL_PRE_PACKED_STRUCT struct {
uint8 low;
uint8 high;
} BWL_POST_PACKED_STRUCT count;
wpa_suite_t list[1];
} BWL_POST_PACKED_STRUCT wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
#define WPA_IE_SUITE_COUNT_LEN 2
typedef BWL_PRE_PACKED_STRUCT struct {
BWL_PRE_PACKED_STRUCT struct {
uint8 low;
uint8 high;
} BWL_POST_PACKED_STRUCT count;
wpa_pmkid_t list[1];
} BWL_POST_PACKED_STRUCT wpa_pmkid_list_t;
#define WPA_CIPHER_NONE 0
#define WPA_CIPHER_WEP_40 1
#define WPA_CIPHER_TKIP 2
#define WPA_CIPHER_AES_OCB 3
#define WPA_CIPHER_AES_CCM 4
#define WPA_CIPHER_WEP_104 5
#define IS_WPA_CIPHER(cipher) ((cipher) == WPA_CIPHER_NONE || \
(cipher) == WPA_CIPHER_WEP_40 || \
(cipher) == WPA_CIPHER_WEP_104 || \
(cipher) == WPA_CIPHER_TKIP || \
(cipher) == WPA_CIPHER_AES_OCB || \
(cipher) == WPA_CIPHER_AES_CCM)
#define WPA_TKIP_CM_DETECT 60
#define WPA_TKIP_CM_BLOCK 60
#define RSN_CAP_LEN 2
#define RSN_CAP_PREAUTH 0x0001
#define RSN_CAP_NOPAIRWISE 0x0002
#define RSN_CAP_PTK_REPLAY_CNTR_MASK 0x000C
#define RSN_CAP_PTK_REPLAY_CNTR_SHIFT 2
#define RSN_CAP_GTK_REPLAY_CNTR_MASK 0x0030
#define RSN_CAP_GTK_REPLAY_CNTR_SHIFT 4
#define RSN_CAP_1_REPLAY_CNTR 0
#define RSN_CAP_2_REPLAY_CNTRS 1
#define RSN_CAP_4_REPLAY_CNTRS 2
#define RSN_CAP_16_REPLAY_CNTRS 3
#define WPA_CAP_4_REPLAY_CNTRS RSN_CAP_4_REPLAY_CNTRS
#define WPA_CAP_16_REPLAY_CNTRS RSN_CAP_16_REPLAY_CNTRS
#define WPA_CAP_REPLAY_CNTR_SHIFT RSN_CAP_PTK_REPLAY_CNTR_SHIFT
#define WPA_CAP_REPLAY_CNTR_MASK RSN_CAP_PTK_REPLAY_CNTR_MASK
#define WPA_CAP_LEN RSN_CAP_LEN
#define WPA_CAP_WPA2_PREAUTH RSN_CAP_PREAUTH
#include <packed_section_end.h>
#endif /* _proto_wpa_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __QMATH_H__
#define __QMATH_H__
#include <typedefs.h>
int16 qm_sat32(int32 op);
int32 qm_mul321616(int16 op1, int16 op2);
int16 qm_mul16(int16 op1, int16 op2);
int32 qm_muls321616(int16 op1, int16 op2);
uint16 qm_mulu16(uint16 op1, uint16 op2);
int16 qm_muls16(int16 op1, int16 op2);
int32 qm_add32(int32 op1, int32 op2);
int16 qm_add16(int16 op1, int16 op2);
int16 qm_sub16(int16 op1, int16 op2);
int32 qm_sub32(int32 op1, int32 op2);
int32 qm_mac321616(int32 acc, int16 op1, int16 op2);
int32 qm_shl32(int32 op, int shift);
int32 qm_shr32(int32 op, int shift);
int16 qm_shl16(int16 op, int shift);
int16 qm_shr16(int16 op, int shift);
int16 qm_norm16(int16 op);
int16 qm_norm32(int32 op);
int16 qm_div_s(int16 num, int16 denom);
int16 qm_abs16(int16 op);
int16 qm_div16(int16 num, int16 denom, int16 * qQuotient);
int32 qm_abs32(int32 op);
int16 qm_div163232(int32 num, int32 denom, int16 * qquotient);
int32 qm_mul323216(int32 op1, int16 op2);
int32 qm_mulsu321616(int16 op1, uint16 op2);
int32 qm_muls323216(int32 op1, int16 op2);
int32 qm_mul32(int32 a, int32 b);
int32 qm_muls32(int32 a, int32 b);
void qm_log10(int32 N, int16 qN, int16 * log10N, int16 * qLog10N);
void qm_1byN(int32 N, int16 qN, int32 * result, int16 * qResult);
#endif /* #ifndef __QMATH_H__ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _rpcosl_h_
#define _rpcosl_h_
typedef struct rpc_osl rpc_osl_t;
extern rpc_osl_t *rpc_osl_attach(osl_t * osh);
extern void rpc_osl_detach(rpc_osl_t * rpc_osh);
#define RPC_OSL_LOCK(rpc_osh) rpc_osl_lock((rpc_osh))
#define RPC_OSL_UNLOCK(rpc_osh) rpc_osl_unlock((rpc_osh))
#define RPC_OSL_WAIT(rpc_osh, to, ptimedout) rpc_osl_wait((rpc_osh), (to), (ptimedout))
#define RPC_OSL_WAKE(rpc_osh) rpc_osl_wake((rpc_osh))
extern void rpc_osl_lock(rpc_osl_t * rpc_osh);
extern void rpc_osl_unlock(rpc_osl_t * rpc_osh);
extern int rpc_osl_wait(rpc_osl_t * rpc_osh, uint ms, bool * ptimedout);
extern void rpc_osl_wake(rpc_osl_t * rpc_osh);
#endif /* _rpcosl_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SBCONFIG_H
#define _SBCONFIG_H
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif
/* enumeration in SB is based on the premise that cores are contiguos in the
* enumeration space.
*/
#define SB_BUS_SIZE 0x10000 /* Each bus gets 64Kbytes for cores */
#define SB_BUS_BASE(b) (SI_ENUM_BASE + (b) * SB_BUS_SIZE)
#define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE) /* Max cores per bus */
/*
* Sonics Configuration Space Registers.
*/
#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
#define SBIPSFLAG 0x08
#define SBTPSFLAG 0x18
#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
#define SBADMATCH3 0x60
#define SBADMATCH2 0x68
#define SBADMATCH1 0x70
#define SBIMSTATE 0x90
#define SBINTVEC 0x94
#define SBTMSTATELOW 0x98
#define SBTMSTATEHIGH 0x9c
#define SBBWA0 0xa0
#define SBIMCONFIGLOW 0xa8
#define SBIMCONFIGHIGH 0xac
#define SBADMATCH0 0xb0
#define SBTMCONFIGLOW 0xb8
#define SBTMCONFIGHIGH 0xbc
#define SBBCONFIG 0xc0
#define SBBSTATE 0xc8
#define SBACTCNFG 0xd8
#define SBFLAGST 0xe8
#define SBIDLOW 0xf8
#define SBIDHIGH 0xfc
/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
* a few registers *below* that line. I think it would be very confusing to try
* and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
*/
#define SBIMERRLOGA 0xea8
#define SBIMERRLOG 0xeb0
#define SBTMPORTCONNID0 0xed8
#define SBTMPORTLOCK0 0xef8
#ifndef _LANGUAGE_ASSEMBLY
typedef volatile struct _sbconfig {
uint32 PAD[2];
uint32 sbipsflag; /* initiator port ocp slave flag */
uint32 PAD[3];
uint32 sbtpsflag; /* target port ocp slave flag */
uint32 PAD[11];
uint32 sbtmerrloga; /* (sonics >= 2.3) */
uint32 PAD;
uint32 sbtmerrlog; /* (sonics >= 2.3) */
uint32 PAD[3];
uint32 sbadmatch3; /* address match3 */
uint32 PAD;
uint32 sbadmatch2; /* address match2 */
uint32 PAD;
uint32 sbadmatch1; /* address match1 */
uint32 PAD[7];
uint32 sbimstate; /* initiator agent state */
uint32 sbintvec; /* interrupt mask */
uint32 sbtmstatelow; /* target state */
uint32 sbtmstatehigh; /* target state */
uint32 sbbwa0; /* bandwidth allocation table0 */
uint32 PAD;
uint32 sbimconfiglow; /* initiator configuration */
uint32 sbimconfighigh; /* initiator configuration */
uint32 sbadmatch0; /* address match0 */
uint32 PAD;
uint32 sbtmconfiglow; /* target configuration */
uint32 sbtmconfighigh; /* target configuration */
uint32 sbbconfig; /* broadcast configuration */
uint32 PAD;
uint32 sbbstate; /* broadcast state */
uint32 PAD[3];
uint32 sbactcnfg; /* activate configuration */
uint32 PAD[3];
uint32 sbflagst; /* current sbflags */
uint32 PAD[3];
uint32 sbidlow; /* identification */
uint32 sbidhigh; /* identification */
} sbconfig_t;
#endif /* _LANGUAGE_ASSEMBLY */
/* sbipsflag */
#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
#define SBIPS_INT1_SHIFT 0
#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
#define SBIPS_INT2_SHIFT 8
#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
#define SBIPS_INT3_SHIFT 16
#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
#define SBIPS_INT4_SHIFT 24
/* sbtpsflag */
#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
/* sbtmerrlog */
#define SBTMEL_CM 0x00000007 /* command */
#define SBTMEL_CI 0x0000ff00 /* connection id */
#define SBTMEL_EC 0x0f000000 /* error code */
#define SBTMEL_ME 0x80000000 /* multiple error */
/* sbimstate */
#define SBIM_PC 0xf /* pipecount */
#define SBIM_AP_MASK 0x30 /* arbitration policy */
#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
#define SBIM_AP_TS 0x10 /* use timesliaces only */
#define SBIM_AP_TK 0x20 /* use token only */
#define SBIM_AP_RSV 0x30 /* reserved */
#define SBIM_IBE 0x20000 /* inbanderror */
#define SBIM_TO 0x40000 /* timeout */
#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
/* sbtmstatelow */
#define SBTML_RESET 0x0001 /* reset */
#define SBTML_REJ_MASK 0x0006 /* reject field */
#define SBTML_REJ 0x0002 /* reject */
#define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */
#define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */
/* sbtmstatehigh */
#define SBTMH_SERR 0x0001 /* serror */
#define SBTMH_INT 0x0002 /* interrupt */
#define SBTMH_BUSY 0x0004 /* busy */
#define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
#define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */
/* sbbwa0 */
#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
#define SBBWA_TAB1_SHIFT 16
/* sbimconfiglow */
#define SBIMCL_STO_MASK 0x7 /* service timeout */
#define SBIMCL_RTO_MASK 0x70 /* request timeout */
#define SBIMCL_RTO_SHIFT 4
#define SBIMCL_CID_MASK 0xff0000 /* connection id */
#define SBIMCL_CID_SHIFT 16
/* sbimconfighigh */
#define SBIMCH_IEM_MASK 0xc /* inband error mode */
#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
#define SBIMCH_TEM_SHIFT 4
#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
#define SBIMCH_BEM_SHIFT 6
/* sbadmatch0 */
#define SBAM_TYPE_MASK 0x3 /* address type */
#define SBAM_AD64 0x4 /* reserved */
#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
#define SBAM_ADINT0_SHIFT 3
#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
#define SBAM_ADINT1_SHIFT 3
#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
#define SBAM_ADINT2_SHIFT 3
#define SBAM_ADEN 0x400 /* enable */
#define SBAM_ADNEG 0x800 /* negative decode */
#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
#define SBAM_BASE0_SHIFT 8
#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
#define SBAM_BASE1_SHIFT 12
#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
#define SBAM_BASE2_SHIFT 16
/* sbtmconfiglow */
#define SBTMCL_CD_MASK 0xff /* clock divide */
#define SBTMCL_CO_MASK 0xf800 /* clock offset */
#define SBTMCL_CO_SHIFT 11
#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
#define SBTMCL_IF_SHIFT 18
#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
#define SBTMCL_IM_SHIFT 24
/* sbtmconfighigh */
#define SBTMCH_BM_MASK 0x3 /* busy mode */
#define SBTMCH_RM_MASK 0x3 /* retry mode */
#define SBTMCH_RM_SHIFT 2
#define SBTMCH_SM_MASK 0x30 /* stop mode */
#define SBTMCH_SM_SHIFT 4
#define SBTMCH_EM_MASK 0x300 /* sb error mode */
#define SBTMCH_EM_SHIFT 8
#define SBTMCH_IM_MASK 0xc00 /* int mode */
#define SBTMCH_IM_SHIFT 10
/* sbbconfig */
#define SBBC_LAT_MASK 0x3 /* sb latency */
#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
#define SBBC_MAX0_SHIFT 16
#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
#define SBBC_MAX1_SHIFT 20
/* sbbstate */
#define SBBS_SRD 0x1 /* st reg disable */
#define SBBS_HRD 0x2 /* hold reg disable */
/* sbidlow */
#define SBIDL_CS_MASK 0x3 /* config space */
#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
#define SBIDL_AR_SHIFT 3
#define SBIDL_SYNCH 0x40 /* sync */
#define SBIDL_INIT 0x80 /* initiator */
#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
#define SBIDL_MINLAT_SHIFT 8
#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
#define SBIDL_MAXLAT_SHIFT 12
#define SBIDL_FIRST 0x10000 /* this initiator is first */
#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
#define SBIDL_CW_SHIFT 18
#define SBIDL_TP_MASK 0xf00000 /* target ports */
#define SBIDL_TP_SHIFT 20
#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
#define SBIDL_IP_SHIFT 24
#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
#define SBIDL_RV_SHIFT 28
#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
/* sbidhigh */
#define SBIDH_RC_MASK 0x000f /* revision code */
#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
#define SBIDH_RCE_SHIFT 8
#define SBCOREREV(sbidh) \
((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
#define SBIDH_CC_MASK 0x8ff0 /* core code */
#define SBIDH_CC_SHIFT 4
#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
#define SBIDH_VC_SHIFT 16
#define SB_COMMIT 0xfd8 /* update buffered registers value */
/* vendor codes */
#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
#endif /* _SBCONFIG_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _sbhnddma_h_
#define _sbhnddma_h_
/* DMA structure:
* support two DMA engines: 32 bits address or 64 bit addressing
* basic DMA register set is per channel(transmit or receive)
* a pair of channels is defined for convenience
*/
/* 32 bits addressing */
/* dma registers per channel(xmt or rcv) */
typedef volatile struct {
uint32 control; /* enable, et al */
uint32 addr; /* descriptor ring base address (4K aligned) */
uint32 ptr; /* last descriptor posted to chip */
uint32 status; /* current active descriptor, et al */
} dma32regs_t;
typedef volatile struct {
dma32regs_t xmt; /* dma tx channel */
dma32regs_t rcv; /* dma rx channel */
} dma32regp_t;
typedef volatile struct { /* diag access */
uint32 fifoaddr; /* diag address */
uint32 fifodatalow; /* low 32bits of data */
uint32 fifodatahigh; /* high 32bits of data */
uint32 pad; /* reserved */
} dma32diag_t;
/*
* DMA Descriptor
* Descriptors are only read by the hardware, never written back.
*/
typedef volatile struct {
uint32 ctrl; /* misc control bits & bufcount */
uint32 addr; /* data buffer address */
} dma32dd_t;
/*
* Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page.
*/
#define D32RINGALIGN_BITS 12
#define D32MAXRINGSZ (1 << D32RINGALIGN_BITS)
#define D32RINGALIGN (1 << D32RINGALIGN_BITS)
#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
/* transmit channel control */
#define XC_XE ((uint32)1 << 0) /* transmit enable */
#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
#define XC_LE ((uint32)1 << 2) /* loopback enable */
#define XC_FL ((uint32)1 << 4) /* flush request */
#define XC_PD ((uint32)1 << 11) /* parity check disable */
#define XC_AE ((uint32)3 << 16) /* address extension bits */
#define XC_AE_SHIFT 16
/* transmit descriptor table pointer */
#define XP_LD_MASK 0xfff /* last valid descriptor */
/* transmit channel status */
#define XS_CD_MASK 0x0fff /* current descriptor pointer */
#define XS_XS_MASK 0xf000 /* transmit state */
#define XS_XS_SHIFT 12
#define XS_XS_DISABLED 0x0000 /* disabled */
#define XS_XS_ACTIVE 0x1000 /* active */
#define XS_XS_IDLE 0x2000 /* idle wait */
#define XS_XS_STOPPED 0x3000 /* stopped */
#define XS_XS_SUSP 0x4000 /* suspend pending */
#define XS_XE_MASK 0xf0000 /* transmit errors */
#define XS_XE_SHIFT 16
#define XS_XE_NOERR 0x00000 /* no error */
#define XS_XE_DPE 0x10000 /* descriptor protocol error */
#define XS_XE_DFU 0x20000 /* data fifo underrun */
#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
#define XS_AD_MASK 0xfff00000 /* active descriptor */
#define XS_AD_SHIFT 20
/* receive channel control */
#define RC_RE ((uint32)1 << 0) /* receive enable */
#define RC_RO_MASK 0xfe /* receive frame offset */
#define RC_RO_SHIFT 1
#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
#define RC_SH ((uint32)1 << 9) /* separate rx header descriptor enable */
#define RC_OC ((uint32)1 << 10) /* overflow continue */
#define RC_PD ((uint32)1 << 11) /* parity check disable */
#define RC_AE ((uint32)3 << 16) /* address extension bits */
#define RC_AE_SHIFT 16
/* receive descriptor table pointer */
#define RP_LD_MASK 0xfff /* last valid descriptor */
/* receive channel status */
#define RS_CD_MASK 0x0fff /* current descriptor pointer */
#define RS_RS_MASK 0xf000 /* receive state */
#define RS_RS_SHIFT 12
#define RS_RS_DISABLED 0x0000 /* disabled */
#define RS_RS_ACTIVE 0x1000 /* active */
#define RS_RS_IDLE 0x2000 /* idle wait */
#define RS_RS_STOPPED 0x3000 /* reserved */
#define RS_RE_MASK 0xf0000 /* receive errors */
#define RS_RE_SHIFT 16
#define RS_RE_NOERR 0x00000 /* no error */
#define RS_RE_DPE 0x10000 /* descriptor protocol error */
#define RS_RE_DFO 0x20000 /* data fifo overflow */
#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
#define RS_AD_MASK 0xfff00000 /* active descriptor */
#define RS_AD_SHIFT 20
/* fifoaddr */
#define FA_OFF_MASK 0xffff /* offset */
#define FA_SEL_MASK 0xf0000 /* select */
#define FA_SEL_SHIFT 16
#define FA_SEL_XDD 0x00000 /* transmit dma data */
#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
#define FA_SEL_RDD 0x40000 /* receive dma data */
#define FA_SEL_RDP 0x50000 /* receive dma pointers */
#define FA_SEL_XFD 0x80000 /* transmit fifo data */
#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
#define FA_SEL_RFD 0xc0000 /* receive fifo data */
#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
#define FA_SEL_RSD 0xe0000 /* receive frame status data */
#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */
/* descriptor control flags */
#define CTRL_BC_MASK 0x00001fff /* buffer byte count, real data len must <= 4KB */
#define CTRL_AE ((uint32)3 << 16) /* address extension bits */
#define CTRL_AE_SHIFT 16
#define CTRL_PARITY ((uint32)3 << 18) /* parity bit */
#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
/* control flags in the range [27:20] are core-specific and not defined here */
#define CTRL_CORE_MASK 0x0ff00000
/* 64 bits addressing */
/* dma registers per channel(xmt or rcv) */
typedef volatile struct {
uint32 control; /* enable, et al */
uint32 ptr; /* last descriptor posted to chip */
uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
uint32 status0; /* current descriptor, xmt state */
uint32 status1; /* active descriptor, xmt error */
} dma64regs_t;
typedef volatile struct {
dma64regs_t tx; /* dma64 tx channel */
dma64regs_t rx; /* dma64 rx channel */
} dma64regp_t;
typedef volatile struct { /* diag access */
uint32 fifoaddr; /* diag address */
uint32 fifodatalow; /* low 32bits of data */
uint32 fifodatahigh; /* high 32bits of data */
uint32 pad; /* reserved */
} dma64diag_t;
/*
* DMA Descriptor
* Descriptors are only read by the hardware, never written back.
*/
typedef volatile struct {
uint32 ctrl1; /* misc control bits & bufcount */
uint32 ctrl2; /* buffer count and address extension */
uint32 addrlow; /* memory address of the date buffer, bits 31:0 */
uint32 addrhigh; /* memory address of the date buffer, bits 63:32 */
} dma64dd_t;
/*
* Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
*/
#define D64RINGALIGN_BITS 13
#define D64MAXRINGSZ (1 << D64RINGALIGN_BITS)
#define D64RINGALIGN (1 << D64RINGALIGN_BITS)
#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
/* transmit channel control */
#define D64_XC_XE 0x00000001 /* transmit enable */
#define D64_XC_SE 0x00000002 /* transmit suspend request */
#define D64_XC_LE 0x00000004 /* loopback enable */
#define D64_XC_FL 0x00000010 /* flush request */
#define D64_XC_PD 0x00000800 /* parity check disable */
#define D64_XC_AE 0x00030000 /* address extension bits */
#define D64_XC_AE_SHIFT 16
/* transmit descriptor table pointer */
#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
/* transmit channel status */
#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
#define D64_XS0_XS_SHIFT 28
#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
#define D64_XS0_XS_ACTIVE 0x10000000 /* active */
#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
#define D64_XS1_AD_MASK 0x00001fff /* active descriptor */
#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
#define D64_XS1_XE_SHIFT 28
#define D64_XS1_XE_NOERR 0x00000000 /* no error */
#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
#define D64_XS1_XE_COREE 0x50000000 /* core error */
/* receive channel control */
#define D64_RC_RE 0x00000001 /* receive enable */
#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
#define D64_RC_RO_SHIFT 1
#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
#define D64_RC_SH 0x00000200 /* separate rx header descriptor enable */
#define D64_RC_OC 0x00000400 /* overflow continue */
#define D64_RC_PD 0x00000800 /* parity check disable */
#define D64_RC_AE 0x00030000 /* address extension bits */
#define D64_RC_AE_SHIFT 16
/* flags for dma controller */
#define DMA_CTRL_PEN (1 << 0) /* partity enable */
#define DMA_CTRL_ROC (1 << 1) /* rx overflow continue */
#define DMA_CTRL_RXMULTI (1 << 2) /* allow rx scatter to multiple descriptors */
#define DMA_CTRL_UNFRAMED (1 << 3) /* Unframed Rx/Tx data */
/* receive descriptor table pointer */
#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
/* receive channel status */
#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
#define D64_RS0_RS_MASK 0xf0000000 /* receive state */
#define D64_RS0_RS_SHIFT 28
#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
#define D64_RS0_RS_ACTIVE 0x10000000 /* active */
#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
#define D64_RS1_RE_SHIFT 28
#define D64_RS1_RE_NOERR 0x00000000 /* no error */
#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
#define D64_RS1_RE_COREE 0x50000000 /* core error */
/* fifoaddr */
#define D64_FA_OFF_MASK 0xffff /* offset */
#define D64_FA_SEL_MASK 0xf0000 /* select */
#define D64_FA_SEL_SHIFT 16
#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
#define D64_FA_SEL_RDD 0x40000 /* receive dma data */
#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
/* descriptor control flags 1 */
#define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */
#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */
#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */
#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */
#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */
/* descriptor control flags 2 */
#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count. real data len must <= 16KB */
#define D64_CTRL2_AE 0x00030000 /* address extension bits */
#define D64_CTRL2_AE_SHIFT 16
#define D64_CTRL2_PARITY 0x00040000 /* parity bit */
/* control flags in the range [27:20] are core-specific and not defined here */
#define D64_CTRL_CORE_MASK 0x0ff00000
#define D64_RX_FRM_STS_LEN 0x0000ffff /* frame length mask */
#define D64_RX_FRM_STS_OVFL 0x00800000 /* RxOverFlow */
#define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /* no. of descriptors used - 1, d11corerev >= 22 */
#define D64_RX_FRM_STS_DATATYPE 0xf0000000 /* core-dependent data type */
/* receive frame status */
typedef volatile struct {
uint16 len;
uint16 flags;
} dma_rxh_t;
#endif /* _sbhnddma_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _sbhndpio_h_
#define _sbhndpio_h_
/* PIO structure,
* support two PIO format: 2 bytes access and 4 bytes access
* basic FIFO register set is per channel(transmit or receive)
* a pair of channels is defined for convenience
*/
/* 2byte-wide pio register set per channel(xmt or rcv) */
typedef volatile struct {
uint16 fifocontrol;
uint16 fifodata;
uint16 fifofree; /* only valid in xmt channel, not in rcv channel */
uint16 PAD;
} pio2regs_t;
/* a pair of pio channels(tx and rx) */
typedef volatile struct {
pio2regs_t tx;
pio2regs_t rx;
} pio2regp_t;
/* 4byte-wide pio register set per channel(xmt or rcv) */
typedef volatile struct {
uint32 fifocontrol;
uint32 fifodata;
} pio4regs_t;
/* a pair of pio channels(tx and rx) */
typedef volatile struct {
pio4regs_t tx;
pio4regs_t rx;
} pio4regp_t;
#endif /* _sbhndpio_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SBPCMCIA_H
#define _SBPCMCIA_H
/* All the addresses that are offsets in attribute space are divided
* by two to account for the fact that odd bytes are invalid in
* attribute space and our read/write routines make the space appear
* as if they didn't exist. Still we want to show the original numbers
* as documented in the hnd_pcmcia core manual.
*/
/* PCMCIA Function Configuration Registers */
#define PCMCIA_FCR (0x700 / 2)
#define FCR0_OFF 0
#define FCR1_OFF (0x40 / 2)
#define FCR2_OFF (0x80 / 2)
#define FCR3_OFF (0xc0 / 2)
#define PCMCIA_FCR0 (0x700 / 2)
#define PCMCIA_FCR1 (0x740 / 2)
#define PCMCIA_FCR2 (0x780 / 2)
#define PCMCIA_FCR3 (0x7c0 / 2)
/* Standard PCMCIA FCR registers */
#define PCMCIA_COR 0
#define COR_RST 0x80
#define COR_LEV 0x40
#define COR_IRQEN 0x04
#define COR_BLREN 0x01
#define COR_FUNEN 0x01
#define PCICIA_FCSR (2 / 2)
#define PCICIA_PRR (4 / 2)
#define PCICIA_SCR (6 / 2)
#define PCICIA_ESR (8 / 2)
#define PCM_MEMOFF 0x0000
#define F0_MEMOFF 0x1000
#define F1_MEMOFF 0x2000
#define F2_MEMOFF 0x3000
#define F3_MEMOFF 0x4000
/* Memory base in the function fcr's */
#define MEM_ADDR0 (0x728 / 2)
#define MEM_ADDR1 (0x72a / 2)
#define MEM_ADDR2 (0x72c / 2)
/* PCMCIA base plus Srom access in fcr0: */
#define PCMCIA_ADDR0 (0x072e / 2)
#define PCMCIA_ADDR1 (0x0730 / 2)
#define PCMCIA_ADDR2 (0x0732 / 2)
#define MEM_SEG (0x0734 / 2)
#define SROM_CS (0x0736 / 2)
#define SROM_DATAL (0x0738 / 2)
#define SROM_DATAH (0x073a / 2)
#define SROM_ADDRL (0x073c / 2)
#define SROM_ADDRH (0x073e / 2)
#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */
#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */
/* Values for srom_cs: */
#define SROM_IDLE 0
#define SROM_WRITE 1
#define SROM_READ 2
#define SROM_WEN 4
#define SROM_WDS 7
#define SROM_DONE 8
/* Fields in srom_info: */
#define SRI_SZ_MASK 0x03
#define SRI_BLANK 0x04
#define SRI_OTP 0x80
#if !defined(ESTA_POSTMOGRIFY_REMOVAL)
/* CIS stuff */
/* The CIS stops where the FCRs start */
#define CIS_SIZE PCMCIA_FCR
/* CIS tuple length field max */
#define CIS_TUPLE_LEN_MAX 0xff
/* Standard tuples we know about */
#define CISTPL_NULL 0x00
#define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */
#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
#define CISTPL_FUNCID 0x21 /* Function identification */
#define CISTPL_FUNCE 0x22 /* Function extensions */
#define CISTPL_CFTABLE 0x1b /* Config table entry */
#define CISTPL_END 0xff /* End of the CIS tuple chain */
/* Function identifier provides context for the function extentions tuple */
#define CISTPL_FID_SDIO 0x0c /* Extensions defined by SDIO spec */
/* Function extensions for LANs (assumed for extensions other than SDIO) */
#define LAN_TECH 1 /* Technology type */
#define LAN_SPEED 2 /* Raw bit rate */
#define LAN_MEDIA 3 /* Transmission media */
#define LAN_NID 4 /* Node identification (aka MAC addr) */
#define LAN_CONN 5 /* Connector standard */
/* CFTable */
#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
* take one for HNBU, and use "extensions" (a la FUNCE) within it.
*/
#define CISTPL_BRCM_HNBU 0x80
/* Subtypes of BRCM_HNBU: */
#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
#define HNBU_BOARDREV 0x02 /* One byte board revision */
#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
* or 9 (sromrev > 1) bytes
*/
#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
#define HNBU_AA 0x06 /* Antennas available */
#define HNBU_AG 0x07 /* Antenna gain */
#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
#define HNBU_LEDS 0x09 /* LED set */
#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
* in rev 2
*/
#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
#define HNBU_PAPARMS5G 0x0e /* 5G PA params */
#define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */
#define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */
#define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch,
* 2 bytes, rev 3.
*/
#define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch,
* 2 bytes, rev 3.
*/
#define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */
#define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */
#define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */
#define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */
#define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */
#define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */
#define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */
#define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */
#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */
#define HNBU_LEDDC 0x1c /* 2 bytes; LED duty cycle */
#define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */
#define HNBU_PAPARMS_SSLPNPHY 0x1e /* SSLPNPHY PA params */
#define HNBU_RSSISMBXA2G_SSLPNPHY 0x1f /* SSLPNPHY RSSI mid pt sel & board switch arch */
#define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */
#define HNBU_CHAINSWITCH 0x21 /* 2 byte; txchain, rxchain */
#define HNBU_REGREV 0x22 /* 1 byte; */
#define HNBU_FEM 0x23 /* 2 or 4 byte: 11n frontend specification */
#define HNBU_PAPARMS_C0 0x24 /* 8 or 30 bytes: 11n pa paramater for chain 0 */
#define HNBU_PAPARMS_C1 0x25 /* 8 or 30 bytes: 11n pa paramater for chain 1 */
#define HNBU_PAPARMS_C2 0x26 /* 8 or 30 bytes: 11n pa paramater for chain 2 */
#define HNBU_PAPARMS_C3 0x27 /* 8 or 30 bytes: 11n pa paramater for chain 3 */
#define HNBU_PO_CCKOFDM 0x28 /* 6 or 18 bytes: cck2g/ofdm2g/ofdm5g power offset */
#define HNBU_PO_MCS2G 0x29 /* 8 bytes: mcs2g power offset */
#define HNBU_PO_MCS5GM 0x2a /* 8 bytes: mcs5g mid band power offset */
#define HNBU_PO_MCS5GLH 0x2b /* 16 bytes: mcs5g low-high band power offset */
#define HNBU_PO_CDD 0x2c /* 2 bytes: cdd2g/5g power offset */
#define HNBU_PO_STBC 0x2d /* 2 bytes: stbc2g/5g power offset */
#define HNBU_PO_40M 0x2e /* 2 bytes: 40Mhz channel 2g/5g power offset */
#define HNBU_PO_40MDUP 0x2f /* 2 bytes: 40Mhz channel dup 2g/5g power offset */
#define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */
#define HNBU_WPS 0x31 /* 1 byte; GPIO pin for WPS button */
#define HNBU_USBFS 0x32 /* 1 byte; 1 = USB advertises FS mode only */
#define HNBU_BRMIN 0x33 /* 4 byte bootloader min resource mask */
#define HNBU_BRMAX 0x34 /* 4 byte bootloader max resource mask */
#define HNBU_PATCH 0x35 /* bootloader patch addr(2b) & data(4b) pair */
#define HNBU_CCKFILTTYPE 0x36 /* CCK digital filter selection options */
#define HNBU_OFDMPO5G 0x37 /* 4 * 3 = 12 byte 11a ofdm power offsets in rev 3 */
#define HNBU_USBEPNUM 0x40 /* USB endpoint numbers */
#define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8
* plus extra info appended.
*/
#define HNBU_RESERVED 0x81 /* Reserved for non-BRCM post-mfg additions */
#define HNBU_CUSTOM1 0x82 /* 4 byte; For non-BRCM post-mfg additions */
#define HNBU_CUSTOM2 0x83 /* Reserved; For non-BRCM post-mfg additions */
#endif /* !defined(ESTA_POSTMOGRIFY_REMOVAL) */
/* sbtmstatelow */
#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
/* sbtmstatehigh */
#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
#endif /* _SBPCMCIA_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SBSDIO_H
#define _SBSDIO_H
#define SBSDIO_NUM_FUNCTION 3 /* as of sdiod rev 0, supports 3 functions */
/* function 1 miscellaneous registers */
#define SBSDIO_SPROM_CS 0x10000 /* sprom command and status */
#define SBSDIO_SPROM_INFO 0x10001 /* sprom info register */
#define SBSDIO_SPROM_DATA_LOW 0x10002 /* sprom indirect access data byte 0 */
#define SBSDIO_SPROM_DATA_HIGH 0x10003 /* sprom indirect access data byte 1 */
#define SBSDIO_SPROM_ADDR_LOW 0x10004 /* sprom indirect access addr byte 0 */
#define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* sprom indirect access addr byte 0 */
#define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu (gpio) output */
#define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu (gpio) enable */
#define SBSDIO_WATERMARK 0x10008 /* rev < 7, watermark for sdio device */
#define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */
/* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */
#define SBSDIO_FUNC1_SBADDRLOW 0x1000A /* SB Address Window Low (b15) */
#define SBSDIO_FUNC1_SBADDRMID 0x1000B /* SB Address Window Mid (b23:b16) */
#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C /* SB Address Window High (b31:b24) */
#define SBSDIO_FUNC1_FRAMECTRL 0x1000D /* Frame Control (frame term/abort) */
#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E /* ChipClockCSR (ALP/HT ctl/status) */
#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F /* SdioPullUp (on cmd, d0-d2) */
#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 /* Write Frame Byte Count Low */
#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A /* Write Frame Byte Count High */
#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B /* Read Frame Byte Count Low */
#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C /* Read Frame Byte Count High */
#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */
/* SBSDIO_SPROM_CS */
#define SBSDIO_SPROM_IDLE 0
#define SBSDIO_SPROM_WRITE 1
#define SBSDIO_SPROM_READ 2
#define SBSDIO_SPROM_WEN 4
#define SBSDIO_SPROM_WDS 7
#define SBSDIO_SPROM_DONE 8
/* SBSDIO_SPROM_INFO */
#define SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */
#define SROM_BLANK 0x04 /* depreciated in corerev 6 */
#define SROM_OTP 0x80 /* OTP present */
/* SBSDIO_CHIP_CTRL */
#define SBSDIO_CHIP_CTRL_XTAL 0x01 /* or'd with onchip xtal_pu,
* 1: power on oscillator
* (for 4318 only)
*/
/* SBSDIO_WATERMARK */
#define SBSDIO_WATERMARK_MASK 0x7f /* number of words - 1 for sd device
* to wait before sending data to host
*/
/* SBSDIO_DEVICE_CTL */
#define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when
* receiving CMD53
*/
#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is
* synchronous to the sdio clock
*/
#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host
* except the chipActive (rev 8)
*/
#define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put
* external pads in tri-state; requires
* sdio bus power cycle to clear (rev 9)
*/
#define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */
#define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */
#define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */
#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */
/* SBSDIO_FUNC1_CHIPCLKCSR */
#define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */
#define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */
#define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */
#define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */
#define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */
#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */
#define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */
#define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */
/* In rev8, actual avail bits followed original docs */
#define SBSDIO_Rev8_HT_AVAIL 0x40
#define SBSDIO_Rev8_ALP_AVAIL 0x80
#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
#define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \
(alponly ? 1 : SBSDIO_HTAV(regval)))
/* SBSDIO_FUNC1_SDIOPULLUP */
#define SBSDIO_PULLUP_D0 0x01 /* Enable D0/MISO pullup */
#define SBSDIO_PULLUP_D1 0x02 /* Enable D1/INT# pullup */
#define SBSDIO_PULLUP_D2 0x04 /* Enable D2 pullup */
#define SBSDIO_PULLUP_CMD 0x08 /* Enable CMD/MOSI pullup */
#define SBSDIO_PULLUP_ALL 0x0f /* All valid bits */
/* function 1 OCP space */
#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF /* sb offset addr is <= 15 bits, 32k */
#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 /* with b15, maps to 32-bit SB access */
/* some duplication with sbsdpcmdev.h here */
/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
#define SBSDIO_SBWINDOW_MASK 0xffff8000 /* Address bits from SBADDR regs */
/* direct(mapped) cis space */
#define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */
#define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */
#define SBSDIO_OTP_CIS_SIZE_LIMIT 0x078 /* maximum bytes OTP CIS */
#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */
#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple,
* link bytes
*/
/* indirect cis access (in sprom) */
#define SBSDIO_SPROM_CIS_OFFSET 0x8 /* 8 control bytes first, CIS starts from
* 8th byte
*/
#define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* sdio byte mode: maximum length of one
* data comamnd
*/
#define SBSDIO_CORE_ADDR_MASK 0x1FFFF /* sdio core function one address mask */
#endif /* _SBSDIO_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _sbsdpcmdev_h_
#define _sbsdpcmdev_h_
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif /* PAD */
typedef volatile struct {
dma64regs_t xmt; /* dma tx */
uint32 PAD[2];
dma64regs_t rcv; /* dma rx */
uint32 PAD[2];
} dma64p_t;
/* dma64 sdiod corerev >= 1 */
typedef volatile struct {
dma64p_t dma64regs[2];
dma64diag_t dmafifo; /* DMA Diagnostic Regs, 0x280-0x28c */
uint32 PAD[92];
} sdiodma64_t;
/* dma32 sdiod corerev == 0 */
typedef volatile struct {
dma32regp_t dma32regs[2]; /* dma tx & rx, 0x200-0x23c */
dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x240-0x24c */
uint32 PAD[108];
} sdiodma32_t;
/* dma32 regs for pcmcia core */
typedef volatile struct {
dma32regp_t dmaregs; /* DMA Regs, 0x200-0x21c, rev8 */
dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x220-0x22c */
uint32 PAD[116];
} pcmdma32_t;
/* core registers */
typedef volatile struct {
uint32 corecontrol; /* CoreControl, 0x000, rev8 */
uint32 corestatus; /* CoreStatus, 0x004, rev8 */
uint32 PAD[1];
uint32 biststatus; /* BistStatus, 0x00c, rev8 */
/* PCMCIA access */
uint16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */
uint16 PAD[1];
uint16 pcmciamesportalmask; /* PcmciaMesPortalMask, 0x014, rev8 */
uint16 PAD[1];
uint16 pcmciawrframebc; /* PcmciaWrFrameBC, 0x018, rev8 */
uint16 PAD[1];
uint16 pcmciaunderflowtimer; /* PcmciaUnderflowTimer, 0x01c, rev8 */
uint16 PAD[1];
/* interrupt */
uint32 intstatus; /* IntStatus, 0x020, rev8 */
uint32 hostintmask; /* IntHostMask, 0x024, rev8 */
uint32 intmask; /* IntSbMask, 0x028, rev8 */
uint32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */
uint32 sbintmask; /* SBIntMask, 0x030, rev8 */
uint32 funcintmask; /* SDIO Function Interrupt Mask, SDIO rev4 */
uint32 PAD[2];
uint32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */
uint32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */
uint32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */
uint32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */
/* synchronized access to registers in SDIO clock domain */
uint32 sdioaccess; /* SdioAccess, 0x050, rev8 */
uint32 PAD[3];
/* PCMCIA frame control */
uint8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */
uint8 PAD[3];
uint8 pcmciawatermark; /* pcmciaWaterMark, 0x064, rev8 */
uint8 PAD[155];
/* interrupt batching control */
uint32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */
uint32 PAD[3];
/* counters */
uint32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */
uint32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */
uint32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */
uint32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */
uint32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */
uint32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */
uint32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */
uint32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */
uint32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */
uint32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */
uint32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */
uint32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */
uint32 PAD[40];
uint32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */
uint32 PAD[7];
/* DMA engines */
volatile union {
pcmdma32_t pcm32;
sdiodma32_t sdiod32;
sdiodma64_t sdiod64;
} dma;
/* SDIO/PCMCIA CIS region */
char cis[512]; /* 512 byte CIS, 0x400-0x5ff, rev6 */
/* PCMCIA function control registers */
char pcmciafcr[256]; /* PCMCIA FCR, 0x600-6ff, rev6 */
uint16 PAD[55];
/* PCMCIA backplane access */
uint16 backplanecsr; /* BackplaneCSR, 0x76E, rev6 */
uint16 backplaneaddr0; /* BackplaneAddr0, 0x770, rev6 */
uint16 backplaneaddr1; /* BackplaneAddr1, 0x772, rev6 */
uint16 backplaneaddr2; /* BackplaneAddr2, 0x774, rev6 */
uint16 backplaneaddr3; /* BackplaneAddr3, 0x776, rev6 */
uint16 backplanedata0; /* BackplaneData0, 0x778, rev6 */
uint16 backplanedata1; /* BackplaneData1, 0x77a, rev6 */
uint16 backplanedata2; /* BackplaneData2, 0x77c, rev6 */
uint16 backplanedata3; /* BackplaneData3, 0x77e, rev6 */
uint16 PAD[31];
/* sprom "size" & "blank" info */
uint16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */
uint32 PAD[464];
/* Sonics SiliconBackplane registers */
sbconfig_t sbconfig; /* SbConfig Regs, 0xf00-0xfff, rev8 */
} sdpcmd_regs_t;
/* corecontrol */
#define CC_CISRDY (1 << 0) /* CIS Ready */
#define CC_BPRESEN (1 << 1) /* CCCR RES signal causes backplane reset */
#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation bit (rev 11) */
#define CC_XMTDATAAVAIL_MODE (1 << 4) /* data avail generates an interrupt */
#define CC_XMTDATAAVAIL_CTRL (1 << 5) /* data avail interrupt ctrl */
/* corestatus */
#define CS_PCMCIAMODE (1 << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */
#define CS_SMARTDEV (1 << 1) /* 1=smartDev enabled */
#define CS_F2ENABLED (1 << 2) /* 1=host has enabled the device */
#define PCMCIA_MES_PA_MASK 0x7fff /* PCMCIA Message Portal Address Mask */
#define PCMCIA_MES_PM_MASK 0x7fff /* PCMCIA Message Portal Mask Mask */
#define PCMCIA_WFBC_MASK 0xffff /* PCMCIA Write Frame Byte Count Mask */
#define PCMCIA_UT_MASK 0x07ff /* PCMCIA Underflow Timer Mask */
/* intstatus */
#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
#define I_PC (1 << 10) /* descriptor error */
#define I_PD (1 << 11) /* data error */
#define I_DE (1 << 12) /* Descriptor protocol Error */
#define I_RU (1 << 13) /* Receive descriptor Underflow */
#define I_RO (1 << 14) /* Receive fifo Overflow */
#define I_XU (1 << 15) /* Transmit fifo Underflow */
#define I_RI (1 << 16) /* Receive Interrupt */
#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
#define I_XI (1 << 24) /* Transmit Interrupt */
#define I_RF_TERM (1 << 25) /* Read Frame Terminate */
#define I_WF_TERM (1 << 26) /* Write Frame Terminate */
#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
#define I_SBINT (1 << 28) /* sbintstatus Interrupt */
#define I_CHIPACTIVE (1 << 29) /* chip transitioned from doze to active state */
#define I_SRESET (1 << 30) /* CCCR RES interrupt */
#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) /* DMA Errors */
#define I_DMA (I_RI | I_XI | I_ERRORS)
/* sbintstatus */
#define I_SB_SERR (1 << 8) /* Backplane SError (write) */
#define I_SB_RESPERR (1 << 9) /* Backplane Response Error (read) */
#define I_SB_SPROMERR (1 << 10) /* Error accessing the sprom */
/* sdioaccess */
#define SDA_DATA_MASK 0x000000ff /* Read/Write Data Mask */
#define SDA_ADDR_MASK 0x000fff00 /* Read/Write Address Mask */
#define SDA_ADDR_SHIFT 8 /* Read/Write Address Shift */
#define SDA_WRITE 0x01000000 /* Write bit */
#define SDA_READ 0x00000000 /* Write bit cleared for Read */
#define SDA_BUSY 0x80000000 /* Busy bit */
/* sdioaccess-accessible register address spaces */
#define SDA_CCCR_SPACE 0x000 /* sdioAccess CCCR register space */
#define SDA_F1_FBR_SPACE 0x100 /* sdioAccess F1 FBR register space */
#define SDA_F2_FBR_SPACE 0x200 /* sdioAccess F2 FBR register space */
#define SDA_F1_REG_SPACE 0x300 /* sdioAccess F1 core-specific register space */
/* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */
#define SDA_CHIPCONTROLDATA 0x006 /* ChipControlData */
#define SDA_CHIPCONTROLENAB 0x007 /* ChipControlEnable */
#define SDA_F2WATERMARK 0x008 /* Function 2 Watermark */
#define SDA_DEVICECONTROL 0x009 /* DeviceControl */
#define SDA_SBADDRLOW 0x00a /* SbAddrLow */
#define SDA_SBADDRMID 0x00b /* SbAddrMid */
#define SDA_SBADDRHIGH 0x00c /* SbAddrHigh */
#define SDA_FRAMECTRL 0x00d /* FrameCtrl */
#define SDA_CHIPCLOCKCSR 0x00e /* ChipClockCSR */
#define SDA_SDIOPULLUP 0x00f /* SdioPullUp */
#define SDA_SDIOWRFRAMEBCLOW 0x019 /* SdioWrFrameBCLow */
#define SDA_SDIOWRFRAMEBCHIGH 0x01a /* SdioWrFrameBCHigh */
#define SDA_SDIORDFRAMEBCLOW 0x01b /* SdioRdFrameBCLow */
#define SDA_SDIORDFRAMEBCHIGH 0x01c /* SdioRdFrameBCHigh */
/* SDA_F2WATERMARK */
#define SDA_F2WATERMARK_MASK 0x7f /* F2Watermark Mask */
/* SDA_SBADDRLOW */
#define SDA_SBADDRLOW_MASK 0x80 /* SbAddrLow Mask */
/* SDA_SBADDRMID */
#define SDA_SBADDRMID_MASK 0xff /* SbAddrMid Mask */
/* SDA_SBADDRHIGH */
#define SDA_SBADDRHIGH_MASK 0xff /* SbAddrHigh Mask */
/* SDA_FRAMECTRL */
#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
#define SFC_CRC4WOOS (1 << 2) /* HW reports CRC error for write out of sync */
#define SFC_ABORTALL (1 << 3) /* Abort cancels all in-progress frames */
/* pcmciaframectrl */
#define PFC_RF_TERM (1 << 0) /* Read Frame Terminate */
#define PFC_WF_TERM (1 << 1) /* Write Frame Terminate */
/* intrcvlazy */
#define IRL_TO_MASK 0x00ffffff /* timeout */
#define IRL_FC_MASK 0xff000000 /* frame count */
#define IRL_FC_SHIFT 24 /* frame count */
/* rx header */
typedef volatile struct {
uint16 len;
uint16 flags;
} sdpcmd_rxh_t;
/* rx header flags */
#define RXF_CRC 0x0001 /* CRC error detected */
#define RXF_WOOS 0x0002 /* write frame out of sync */
#define RXF_WF_TERM 0x0004 /* write frame terminated */
#define RXF_ABORT 0x0008 /* write frame aborted */
#define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT) /* bad frame */
/* HW frame tag */
#define SDPCM_FRAMETAG_LEN 4 /* HW frametag: 2 bytes len, 2 bytes check val */
#endif /* _sbsdpcmdev_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SBSOCRAM_H
#define _SBSOCRAM_H
#ifndef _LANGUAGE_ASSEMBLY
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif /* PAD */
/* Memcsocram core registers */
typedef volatile struct sbsocramregs {
uint32 coreinfo;
uint32 bwalloc;
uint32 extracoreinfo;
uint32 biststat;
uint32 bankidx;
uint32 standbyctrl;
uint32 errlogstatus; /* rev 6 */
uint32 errlogaddr; /* rev 6 */
/* used for patching rev 3 & 5 */
uint32 cambankidx;
uint32 cambankstandbyctrl;
uint32 cambankpatchctrl;
uint32 cambankpatchtblbaseaddr;
uint32 cambankcmdreg;
uint32 cambankdatareg;
uint32 cambankmaskreg;
uint32 PAD[1];
uint32 bankinfo; /* corev 8 */
uint32 PAD[15];
uint32 extmemconfig;
uint32 extmemparitycsr;
uint32 extmemparityerrdata;
uint32 extmemparityerrcnt;
uint32 extmemwrctrlandsize;
uint32 PAD[84];
uint32 workaround;
uint32 pwrctl; /* corerev >= 2 */
} sbsocramregs_t;
#endif /* _LANGUAGE_ASSEMBLY */
/* Register offsets */
#define SR_COREINFO 0x00
#define SR_BWALLOC 0x04
#define SR_BISTSTAT 0x0c
#define SR_BANKINDEX 0x10
#define SR_BANKSTBYCTL 0x14
#define SR_PWRCTL 0x1e8
/* Coreinfo register */
#define SRCI_PT_MASK 0x00070000 /* corerev >= 6; port type[18:16] */
#define SRCI_PT_SHIFT 16
/* port types : SRCI_PT_<processorPT>_<backplanePT> */
#define SRCI_PT_OCP_OCP 0
#define SRCI_PT_AXI_OCP 1
#define SRCI_PT_ARM7AHB_OCP 2
#define SRCI_PT_CM3AHB_OCP 3
#define SRCI_PT_AXI_AXI 4
#define SRCI_PT_AHB_AXI 5
/* corerev >= 3 */
#define SRCI_LSS_MASK 0x00f00000
#define SRCI_LSS_SHIFT 20
#define SRCI_LRS_MASK 0x0f000000
#define SRCI_LRS_SHIFT 24
/* In corerev 0, the memory size is 2 to the power of the
* base plus 16 plus to the contents of the memsize field plus 1.
*/
#define SRCI_MS0_MASK 0xf
#define SR_MS0_BASE 16
/*
* In corerev 1 the bank size is 2 ^ the bank size field plus 14,
* the memory size is number of banks times bank size.
* The same applies to rom size.
*/
#define SRCI_ROMNB_MASK 0xf000
#define SRCI_ROMNB_SHIFT 12
#define SRCI_ROMBSZ_MASK 0xf00
#define SRCI_ROMBSZ_SHIFT 8
#define SRCI_SRNB_MASK 0xf0
#define SRCI_SRNB_SHIFT 4
#define SRCI_SRBSZ_MASK 0xf
#define SRCI_SRBSZ_SHIFT 0
#define SR_BSZ_BASE 14
/* Standby control register */
#define SRSC_SBYOVR_MASK 0x80000000
#define SRSC_SBYOVR_SHIFT 31
#define SRSC_SBYOVRVAL_MASK 0x60000000
#define SRSC_SBYOVRVAL_SHIFT 29
#define SRSC_SBYEN_MASK 0x01000000 /* rev >= 3 */
#define SRSC_SBYEN_SHIFT 24
/* Power control register */
#define SRPC_PMU_STBYDIS_MASK 0x00000010 /* rev >= 3 */
#define SRPC_PMU_STBYDIS_SHIFT 4
#define SRPC_STBYOVRVAL_MASK 0x00000008
#define SRPC_STBYOVRVAL_SHIFT 3
#define SRPC_STBYOVR_MASK 0x00000007
#define SRPC_STBYOVR_SHIFT 0
/* Extra core capability register */
#define SRECC_NUM_BANKS_MASK 0x000000F0
#define SRECC_NUM_BANKS_SHIFT 4
#define SRECC_BANKSIZE_MASK 0x0000000F
#define SRECC_BANKSIZE_SHIFT 0
#define SRECC_BANKSIZE(value) (1 << (value))
/* CAM bank patch control */
#define SRCBPC_PATCHENABLE 0x80000000
#define SRP_ADDRESS 0x0001FFFC
#define SRP_VALID 0x8000
/* CAM bank command reg */
#define SRCMD_WRITE 0x00020000
#define SRCMD_READ 0x00010000
#define SRCMD_DONE 0x80000000
#define SRCMD_DONE_DLY 1000
/* bankidx and bankinfo reg defines corerev >= 8 */
#define SOCRAM_BANKINFO_SZMASK 0x3f
#define SOCRAM_BANKIDX_ROM_MASK 0x100
#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
/* socram bankinfo memtype */
#define SOCRAM_MEMTYPE_RAM 0
#define SOCRAM_MEMTYPE_R0M 1
#define SOCRAM_MEMTYPE_DEVRAM 2
#define SOCRAM_BANKINFO_REG 0x40
#define SOCRAM_BANKIDX_REG 0x10
#define SOCRAM_BANKINFO_STDBY_MASK 0x400
#define SOCRAM_BANKINFO_STDBY_TIMER 0x800
/* bankinfo rev >= 10 */
#define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13
#define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000
#define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14
#define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000
/* extracoreinfo register */
#define SOCRAM_DEVRAMBANK_MASK 0xF000
#define SOCRAM_DEVRAMBANK_SHIFT 12
/* bank info to calculate bank size */
#define SOCRAM_BANKINFO_SZBASE 8192
#define SOCRAM_BANKSIZE_SHIFT 13 /* SOCRAM_BANKINFO_SZBASE */
#endif /* _SBSOCRAM_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SDIO_H
#define _SDIO_H
#ifdef BCMSDIO
/* CCCR structure for function 0 */
typedef volatile struct {
uint8 cccr_sdio_rev; /* RO, cccr and sdio revision */
uint8 sd_rev; /* RO, sd spec revision */
uint8 io_en; /* I/O enable */
uint8 io_rdy; /* I/O ready reg */
uint8 intr_ctl; /* Master and per function interrupt enable control */
uint8 intr_status; /* RO, interrupt pending status */
uint8 io_abort; /* read/write abort or reset all functions */
uint8 bus_inter; /* bus interface control */
uint8 capability; /* RO, card capability */
uint8 cis_base_low; /* 0x9 RO, common CIS base address, LSB */
uint8 cis_base_mid;
uint8 cis_base_high; /* 0xB RO, common CIS base address, MSB */
/* suspend/resume registers */
uint8 bus_suspend; /* 0xC */
uint8 func_select; /* 0xD */
uint8 exec_flag; /* 0xE */
uint8 ready_flag; /* 0xF */
uint8 fn0_blk_size[2]; /* 0x10(LSB), 0x11(MSB) */
uint8 power_control; /* 0x12 (SDIO version 1.10) */
uint8 speed_control; /* 0x13 */
} sdio_regs_t;
/* SDIO Device CCCR offsets */
#define SDIOD_CCCR_REV 0x00
#define SDIOD_CCCR_SDREV 0x01
#define SDIOD_CCCR_IOEN 0x02
#define SDIOD_CCCR_IORDY 0x03
#define SDIOD_CCCR_INTEN 0x04
#define SDIOD_CCCR_INTPEND 0x05
#define SDIOD_CCCR_IOABORT 0x06
#define SDIOD_CCCR_BICTRL 0x07
#define SDIOD_CCCR_CAPABLITIES 0x08
#define SDIOD_CCCR_CISPTR_0 0x09
#define SDIOD_CCCR_CISPTR_1 0x0A
#define SDIOD_CCCR_CISPTR_2 0x0B
#define SDIOD_CCCR_BUSSUSP 0x0C
#define SDIOD_CCCR_FUNCSEL 0x0D
#define SDIOD_CCCR_EXECFLAGS 0x0E
#define SDIOD_CCCR_RDYFLAGS 0x0F
#define SDIOD_CCCR_BLKSIZE_0 0x10
#define SDIOD_CCCR_BLKSIZE_1 0x11
#define SDIOD_CCCR_POWER_CONTROL 0x12
#define SDIOD_CCCR_SPEED_CONTROL 0x13
/* Broadcom extensions (corerev >= 1) */
#define SDIOD_CCCR_BRCM_SEPINT 0xf2
/* cccr_sdio_rev */
#define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */
#define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */
/* sd_rev */
#define SD_REV_PHY_MASK 0x0f /* SD format version number */
/* io_en */
#define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */
#define SDIO_FUNC_ENABLE_2 0x04 /* function 2 I/O enable */
/* io_rdys */
#define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */
#define SDIO_FUNC_READY_2 0x04 /* function 2 I/O ready */
/* intr_ctl */
#define INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */
#define INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */
#define INTR_CTL_FUNC2_EN 0x4 /* interrupt enable for function 2 */
/* intr_status */
#define INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */
#define INTR_STATUS_FUNC2 0x4 /* interrupt pending for function 2 */
/* io_abort */
#define IO_ABORT_RESET_ALL 0x08 /* I/O card reset */
#define IO_ABORT_FUNC_MASK 0x07 /* abort selction: function x */
/* bus_inter */
#define BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */
#define BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */
#define BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */
#define BUS_SD_DATA_WIDTH_MASK 0x03 /* bus width mask */
#define BUS_SD_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */
#define BUS_SD_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */
/* capability */
#define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */
#define SDIO_CAP_LSC 0x40 /* low speed card */
#define SDIO_CAP_E4MI 0x20 /* enable interrupt between block of data in 4-bit mode */
#define SDIO_CAP_S4MI 0x10 /* support interrupt between block of data in 4-bit mode */
#define SDIO_CAP_SBS 0x08 /* support suspend/resume */
#define SDIO_CAP_SRW 0x04 /* support read wait */
#define SDIO_CAP_SMB 0x02 /* support multi-block transfer */
#define SDIO_CAP_SDC 0x01 /* Support Direct commands during multi-byte transfer */
/* power_control */
#define SDIO_POWER_SMPC 0x01 /* supports master power control (RO) */
#define SDIO_POWER_EMPC 0x02 /* enable master power control (allow > 200mA) (RW) */
/* speed_control (control device entry into high-speed clocking mode) */
#define SDIO_SPEED_SHS 0x01 /* supports high-speed [clocking] mode (RO) */
#define SDIO_SPEED_EHS 0x02 /* enable high-speed [clocking] mode (RW) */
/* brcm sepint */
#define SDIO_SEPINT_MASK 0x01 /* route sdpcmdev intr onto separate pad (chip-specific) */
#define SDIO_SEPINT_OE 0x02 /* 1 asserts output enable for above pad */
#define SDIO_SEPINT_ACT_HI 0x04 /* use active high interrupt level instead of active low */
/* FBR structure for function 1-7, FBR addresses and register offsets */
typedef volatile struct {
uint8 devctr; /* device interface, CSA control */
uint8 ext_dev; /* extended standard I/O device type code */
uint8 pwr_sel; /* power selection support */
uint8 PAD[6]; /* reserved */
uint8 cis_low; /* CIS LSB */
uint8 cis_mid;
uint8 cis_high; /* CIS MSB */
uint8 csa_low; /* code storage area, LSB */
uint8 csa_mid;
uint8 csa_high; /* code storage area, MSB */
uint8 csa_dat_win; /* data access window to function */
uint8 fnx_blk_size[2]; /* block size, little endian */
} sdio_fbr_t;
/* Maximum number of I/O funcs */
#define SDIOD_MAX_IOFUNCS 7
/* SDIO Device FBR Start Address */
#define SDIOD_FBR_STARTADDR 0x100
/* SDIO Device FBR Size */
#define SDIOD_FBR_SIZE 0x100
/* Macro to calculate FBR register base */
#define SDIOD_FBR_BASE(n) ((n) * 0x100)
/* Function register offsets */
#define SDIOD_FBR_DEVCTR 0x00 /* basic info for function */
#define SDIOD_FBR_EXT_DEV 0x01 /* extended I/O device code */
#define SDIOD_FBR_PWR_SEL 0x02 /* power selection bits */
/* SDIO Function CIS ptr offset */
#define SDIOD_FBR_CISPTR_0 0x09
#define SDIOD_FBR_CISPTR_1 0x0A
#define SDIOD_FBR_CISPTR_2 0x0B
/* Code Storage Area pointer */
#define SDIOD_FBR_CSA_ADDR_0 0x0C
#define SDIOD_FBR_CSA_ADDR_1 0x0D
#define SDIOD_FBR_CSA_ADDR_2 0x0E
#define SDIOD_FBR_CSA_DATA 0x0F
/* SDIO Function I/O Block Size */
#define SDIOD_FBR_BLKSIZE_0 0x10
#define SDIOD_FBR_BLKSIZE_1 0x11
/* devctr */
#define SDIOD_FBR_DEVCTR_DIC 0x0f /* device interface code */
#define SDIOD_FBR_DECVTR_CSA 0x40 /* CSA support flag */
#define SDIOD_FBR_DEVCTR_CSA_EN 0x80 /* CSA enabled */
/* interface codes */
#define SDIOD_DIC_NONE 0 /* SDIO standard interface is not supported */
#define SDIOD_DIC_UART 1
#define SDIOD_DIC_BLUETOOTH_A 2
#define SDIOD_DIC_BLUETOOTH_B 3
#define SDIOD_DIC_GPS 4
#define SDIOD_DIC_CAMERA 5
#define SDIOD_DIC_PHS 6
#define SDIOD_DIC_WLAN 7
#define SDIOD_DIC_EXT 0xf /* extended device interface, read ext_dev register */
/* pwr_sel */
#define SDIOD_PWR_SEL_SPS 0x01 /* supports power selection */
#define SDIOD_PWR_SEL_EPS 0x02 /* enable power selection (low-current mode) */
/* misc defines */
#define SDIO_FUNC_0 0
#define SDIO_FUNC_1 1
#define SDIO_FUNC_2 2
#define SDIO_FUNC_3 3
#define SDIO_FUNC_4 4
#define SDIO_FUNC_5 5
#define SDIO_FUNC_6 6
#define SDIO_FUNC_7 7
#define SD_CARD_TYPE_UNKNOWN 0 /* bad type or unrecognized */
#define SD_CARD_TYPE_IO 1 /* IO only card */
#define SD_CARD_TYPE_MEMORY 2 /* memory only card */
#define SD_CARD_TYPE_COMBO 3 /* IO and memory combo card */
#define SDIO_MAX_BLOCK_SIZE 2048 /* maximum block size for block mode operation */
#define SDIO_MIN_BLOCK_SIZE 1 /* minimum block size for block mode operation */
/* Card registers: status bit position */
#define CARDREG_STATUS_BIT_OUTOFRANGE 31
#define CARDREG_STATUS_BIT_COMCRCERROR 23
#define CARDREG_STATUS_BIT_ILLEGALCOMMAND 22
#define CARDREG_STATUS_BIT_ERROR 19
#define CARDREG_STATUS_BIT_IOCURRENTSTATE3 12
#define CARDREG_STATUS_BIT_IOCURRENTSTATE2 11
#define CARDREG_STATUS_BIT_IOCURRENTSTATE1 10
#define CARDREG_STATUS_BIT_IOCURRENTSTATE0 9
#define CARDREG_STATUS_BIT_FUN_NUM_ERROR 4
#define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */
#define SD_CMD_SEND_OPCOND 1
#define SD_CMD_MMC_SET_RCA 3
#define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */
#define SD_CMD_SELECT_DESELECT_CARD 7
#define SD_CMD_SEND_CSD 9
#define SD_CMD_SEND_CID 10
#define SD_CMD_STOP_TRANSMISSION 12
#define SD_CMD_SEND_STATUS 13
#define SD_CMD_GO_INACTIVE_STATE 15
#define SD_CMD_SET_BLOCKLEN 16
#define SD_CMD_READ_SINGLE_BLOCK 17
#define SD_CMD_READ_MULTIPLE_BLOCK 18
#define SD_CMD_WRITE_BLOCK 24
#define SD_CMD_WRITE_MULTIPLE_BLOCK 25
#define SD_CMD_PROGRAM_CSD 27
#define SD_CMD_SET_WRITE_PROT 28
#define SD_CMD_CLR_WRITE_PROT 29
#define SD_CMD_SEND_WRITE_PROT 30
#define SD_CMD_ERASE_WR_BLK_START 32
#define SD_CMD_ERASE_WR_BLK_END 33
#define SD_CMD_ERASE 38
#define SD_CMD_LOCK_UNLOCK 42
#define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */
#define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */
#define SD_CMD_APP_CMD 55
#define SD_CMD_GEN_CMD 56
#define SD_CMD_READ_OCR 58
#define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */
#define SD_ACMD_SD_STATUS 13
#define SD_ACMD_SEND_NUM_WR_BLOCKS 22
#define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23
#define SD_ACMD_SD_SEND_OP_COND 41
#define SD_ACMD_SET_CLR_CARD_DETECT 42
#define SD_ACMD_SEND_SCR 51
/* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */
#define SD_IO_OP_READ 0 /* Read_Write: Read */
#define SD_IO_OP_WRITE 1 /* Read_Write: Write */
#define SD_IO_RW_NORMAL 0 /* no RAW */
#define SD_IO_RW_RAW 1 /* RAW */
#define SD_IO_BYTE_MODE 0 /* Byte Mode */
#define SD_IO_BLOCK_MODE 1 /* BlockMode */
#define SD_IO_FIXED_ADDRESS 0 /* fix Address */
#define SD_IO_INCREMENT_ADDRESS 1 /* IncrementAddress */
/* build SD_CMD_IO_RW_DIRECT Argument */
#define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \
((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \
(((addr) & 0x1FFFF) << 9) | ((data) & 0xFF))
/* build SD_CMD_IO_RW_EXTENDED Argument */
#define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \
((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \
(((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF))
/* SDIO response parameters */
#define SD_RSP_NO_NONE 0
#define SD_RSP_NO_1 1
#define SD_RSP_NO_2 2
#define SD_RSP_NO_3 3
#define SD_RSP_NO_4 4
#define SD_RSP_NO_5 5
#define SD_RSP_NO_6 6
/* Modified R6 response (to CMD3) */
#define SD_RSP_MR6_COM_CRC_ERROR 0x8000
#define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000
#define SD_RSP_MR6_ERROR 0x2000
/* Modified R1 in R4 Response (to CMD5) */
#define SD_RSP_MR1_SBIT 0x80
#define SD_RSP_MR1_PARAMETER_ERROR 0x40
#define SD_RSP_MR1_RFU5 0x20
#define SD_RSP_MR1_FUNC_NUM_ERROR 0x10
#define SD_RSP_MR1_COM_CRC_ERROR 0x08
#define SD_RSP_MR1_ILLEGAL_COMMAND 0x04
#define SD_RSP_MR1_RFU1 0x02
#define SD_RSP_MR1_IDLE_STATE 0x01
/* R5 response (to CMD52 and CMD53) */
#define SD_RSP_R5_COM_CRC_ERROR 0x80
#define SD_RSP_R5_ILLEGAL_COMMAND 0x40
#define SD_RSP_R5_IO_CURRENTSTATE1 0x20
#define SD_RSP_R5_IO_CURRENTSTATE0 0x10
#define SD_RSP_R5_ERROR 0x08
#define SD_RSP_R5_RFU 0x04
#define SD_RSP_R5_FUNC_NUM_ERROR 0x02
#define SD_RSP_R5_OUT_OF_RANGE 0x01
#define SD_RSP_R5_ERRBITS 0xCB
/* ------------------------------------------------
* SDIO Commands and responses
*
* I/O only commands are:
* CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53
* ------------------------------------------------
*/
/* SDIO Commands */
#define SDIOH_CMD_0 0
#define SDIOH_CMD_3 3
#define SDIOH_CMD_5 5
#define SDIOH_CMD_7 7
#define SDIOH_CMD_15 15
#define SDIOH_CMD_52 52
#define SDIOH_CMD_53 53
#define SDIOH_CMD_59 59
/* SDIO Command Responses */
#define SDIOH_RSP_NONE 0
#define SDIOH_RSP_R1 1
#define SDIOH_RSP_R2 2
#define SDIOH_RSP_R3 3
#define SDIOH_RSP_R4 4
#define SDIOH_RSP_R5 5
#define SDIOH_RSP_R6 6
/*
* SDIO Response Error flags
*/
#define SDIOH_RSP5_ERROR_FLAGS 0xCB
/* ------------------------------------------------
* SDIO Command structures. I/O only commands are:
*
* CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53
* ------------------------------------------------
*/
#define CMD5_OCR_M BITFIELD_MASK(24)
#define CMD5_OCR_S 0
#define CMD7_RCA_M BITFIELD_MASK(16)
#define CMD7_RCA_S 16
#define CMD_15_RCA_M BITFIELD_MASK(16)
#define CMD_15_RCA_S 16
#define CMD52_DATA_M BITFIELD_MASK(8) /* Bits [7:0] - Write Data/Stuff bits of CMD52
*/
#define CMD52_DATA_S 0
#define CMD52_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */
#define CMD52_REG_ADDR_S 9
#define CMD52_RAW_M BITFIELD_MASK(1) /* Bit 27 - Read after Write flag */
#define CMD52_RAW_S 27
#define CMD52_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */
#define CMD52_FUNCTION_S 28
#define CMD52_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */
#define CMD52_RW_FLAG_S 31
#define CMD53_BYTE_BLK_CNT_M BITFIELD_MASK(9) /* Bits [8:0] - Byte/Block Count of CMD53 */
#define CMD53_BYTE_BLK_CNT_S 0
#define CMD53_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */
#define CMD53_REG_ADDR_S 9
#define CMD53_OP_CODE_M BITFIELD_MASK(1) /* Bit 26 - R/W Operation Code */
#define CMD53_OP_CODE_S 26
#define CMD53_BLK_MODE_M BITFIELD_MASK(1) /* Bit 27 - Block Mode */
#define CMD53_BLK_MODE_S 27
#define CMD53_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */
#define CMD53_FUNCTION_S 28
#define CMD53_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */
#define CMD53_RW_FLAG_S 31
/* ------------------------------------------------------
* SDIO Command Response structures for SD1 and SD4 modes
* -----------------------------------------------------
*/
#define RSP4_IO_OCR_M BITFIELD_MASK(24) /* Bits [23:0] - Card's OCR Bits [23:0] */
#define RSP4_IO_OCR_S 0
#define RSP4_STUFF_M BITFIELD_MASK(3) /* Bits [26:24] - Stuff bits */
#define RSP4_STUFF_S 24
#define RSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 27 - Memory present */
#define RSP4_MEM_PRESENT_S 27
#define RSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [30:28] - Number of I/O funcs */
#define RSP4_NUM_FUNCS_S 28
#define RSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 31 - SDIO card ready */
#define RSP4_CARD_READY_S 31
#define RSP6_STATUS_M BITFIELD_MASK(16) /* Bits [15:0] - Card status bits [19,22,23,12:0]
*/
#define RSP6_STATUS_S 0
#define RSP6_IO_RCA_M BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */
#define RSP6_IO_RCA_S 16
#define RSP1_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error */
#define RSP1_AKE_SEQ_ERROR_S 3
#define RSP1_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */
#define RSP1_APP_CMD_S 5
#define RSP1_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data (buff empty) */
#define RSP1_READY_FOR_DATA_S 8
#define RSP1_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - State of card
* when Cmd was received
*/
#define RSP1_CURR_STATE_S 9
#define RSP1_EARSE_RESET_M BITFIELD_MASK(1) /* Bit 13 - Erase seq cleared */
#define RSP1_EARSE_RESET_S 13
#define RSP1_CARD_ECC_DISABLE_M BITFIELD_MASK(1) /* Bit 14 - Card ECC disabled */
#define RSP1_CARD_ECC_DISABLE_S 14
#define RSP1_WP_ERASE_SKIP_M BITFIELD_MASK(1) /* Bit 15 - Partial blocks erased due to W/P */
#define RSP1_WP_ERASE_SKIP_S 15
#define RSP1_CID_CSD_OVERW_M BITFIELD_MASK(1) /* Bit 16 - Illegal write to CID or R/O bits
* of CSD
*/
#define RSP1_CID_CSD_OVERW_S 16
#define RSP1_ERROR_M BITFIELD_MASK(1) /* Bit 19 - General/Unknown error */
#define RSP1_ERROR_S 19
#define RSP1_CC_ERROR_M BITFIELD_MASK(1) /* Bit 20 - Internal Card Control error */
#define RSP1_CC_ERROR_S 20
#define RSP1_CARD_ECC_FAILED_M BITFIELD_MASK(1) /* Bit 21 - Card internal ECC failed
* to correct data
*/
#define RSP1_CARD_ECC_FAILED_S 21
#define RSP1_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 22 - Cmd not legal for the card state */
#define RSP1_ILLEGAL_CMD_S 22
#define RSP1_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 23 - CRC check of previous command failed
*/
#define RSP1_COM_CRC_ERROR_S 23
#define RSP1_LOCK_UNLOCK_FAIL_M BITFIELD_MASK(1) /* Bit 24 - Card lock-unlock Cmd Seq error */
#define RSP1_LOCK_UNLOCK_FAIL_S 24
#define RSP1_CARD_LOCKED_M BITFIELD_MASK(1) /* Bit 25 - Card locked by the host */
#define RSP1_CARD_LOCKED_S 25
#define RSP1_WP_VIOLATION_M BITFIELD_MASK(1) /* Bit 26 - Attempt to program
* write-protected blocks
*/
#define RSP1_WP_VIOLATION_S 26
#define RSP1_ERASE_PARAM_M BITFIELD_MASK(1) /* Bit 27 - Invalid erase blocks */
#define RSP1_ERASE_PARAM_S 27
#define RSP1_ERASE_SEQ_ERR_M BITFIELD_MASK(1) /* Bit 28 - Erase Cmd seq error */
#define RSP1_ERASE_SEQ_ERR_S 28
#define RSP1_BLK_LEN_ERR_M BITFIELD_MASK(1) /* Bit 29 - Block length error */
#define RSP1_BLK_LEN_ERR_S 29
#define RSP1_ADDR_ERR_M BITFIELD_MASK(1) /* Bit 30 - Misaligned address */
#define RSP1_ADDR_ERR_S 30
#define RSP1_OUT_OF_RANGE_M BITFIELD_MASK(1) /* Bit 31 - Cmd arg was out of range */
#define RSP1_OUT_OF_RANGE_S 31
#define RSP5_DATA_M BITFIELD_MASK(8) /* Bits [0:7] - data */
#define RSP5_DATA_S 0
#define RSP5_FLAGS_M BITFIELD_MASK(8) /* Bit [15:8] - Rsp flags */
#define RSP5_FLAGS_S 8
#define RSP5_STUFF_M BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */
#define RSP5_STUFF_S 16
/* ----------------------------------------------
* SDIO Command Response structures for SPI mode
* ----------------------------------------------
*/
#define SPIRSP4_IO_OCR_M BITFIELD_MASK(16) /* Bits [15:0] - Card's OCR Bits [23:8] */
#define SPIRSP4_IO_OCR_S 0
#define SPIRSP4_STUFF_M BITFIELD_MASK(3) /* Bits [18:16] - Stuff bits */
#define SPIRSP4_STUFF_S 16
#define SPIRSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 19 - Memory present */
#define SPIRSP4_MEM_PRESENT_S 19
#define SPIRSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [22:20] - Number of I/O funcs */
#define SPIRSP4_NUM_FUNCS_S 20
#define SPIRSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 23 - SDIO card ready */
#define SPIRSP4_CARD_READY_S 23
#define SPIRSP4_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - idle state */
#define SPIRSP4_IDLE_STATE_S 24
#define SPIRSP4_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */
#define SPIRSP4_ILLEGAL_CMD_S 26
#define SPIRSP4_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */
#define SPIRSP4_COM_CRC_ERROR_S 27
#define SPIRSP4_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error
*/
#define SPIRSP4_FUNC_NUM_ERROR_S 28
#define SPIRSP4_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */
#define SPIRSP4_PARAM_ERROR_S 30
#define SPIRSP4_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */
#define SPIRSP4_START_BIT_S 31
#define SPIRSP5_DATA_M BITFIELD_MASK(8) /* Bits [23:16] - R/W Data */
#define SPIRSP5_DATA_S 16
#define SPIRSP5_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - Idle state */
#define SPIRSP5_IDLE_STATE_S 24
#define SPIRSP5_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */
#define SPIRSP5_ILLEGAL_CMD_S 26
#define SPIRSP5_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */
#define SPIRSP5_COM_CRC_ERROR_S 27
#define SPIRSP5_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error
*/
#define SPIRSP5_FUNC_NUM_ERROR_S 28
#define SPIRSP5_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */
#define SPIRSP5_PARAM_ERROR_S 30
#define SPIRSP5_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */
#define SPIRSP5_START_BIT_S 31
/* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */
#define RSP6STAT_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error
*/
#define RSP6STAT_AKE_SEQ_ERROR_S 3
#define RSP6STAT_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */
#define RSP6STAT_APP_CMD_S 5
#define RSP6STAT_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data
* (buff empty)
*/
#define RSP6STAT_READY_FOR_DATA_S 8
#define RSP6STAT_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - Card state at
* Cmd reception
*/
#define RSP6STAT_CURR_STATE_S 9
#define RSP6STAT_ERROR_M BITFIELD_MASK(1) /* Bit 13 - General/Unknown error Bit 19
*/
#define RSP6STAT_ERROR_S 13
#define RSP6STAT_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 14 - Illegal cmd for
* card state Bit 22
*/
#define RSP6STAT_ILLEGAL_CMD_S 14
#define RSP6STAT_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 15 - CRC previous command
* failed Bit 23
*/
#define RSP6STAT_COM_CRC_ERROR_S 15
#define SDIOH_XFER_TYPE_READ SD_IO_OP_READ
#define SDIOH_XFER_TYPE_WRITE SD_IO_OP_WRITE
#endif /* def BCMSDIO */
#endif /* _SDIO_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SDIOH_H
#define _SDIOH_H
#define SD_SysAddr 0x000
#define SD_BlockSize 0x004
#define SD_BlockCount 0x006
#define SD_Arg0 0x008
#define SD_Arg1 0x00A
#define SD_TransferMode 0x00C
#define SD_Command 0x00E
#define SD_Response0 0x010
#define SD_Response1 0x012
#define SD_Response2 0x014
#define SD_Response3 0x016
#define SD_Response4 0x018
#define SD_Response5 0x01A
#define SD_Response6 0x01C
#define SD_Response7 0x01E
#define SD_BufferDataPort0 0x020
#define SD_BufferDataPort1 0x022
#define SD_PresentState 0x024
#define SD_HostCntrl 0x028
#define SD_PwrCntrl 0x029
#define SD_BlockGapCntrl 0x02A
#define SD_WakeupCntrl 0x02B
#define SD_ClockCntrl 0x02C
#define SD_TimeoutCntrl 0x02E
#define SD_SoftwareReset 0x02F
#define SD_IntrStatus 0x030
#define SD_ErrorIntrStatus 0x032
#define SD_IntrStatusEnable 0x034
#define SD_ErrorIntrStatusEnable 0x036
#define SD_IntrSignalEnable 0x038
#define SD_ErrorIntrSignalEnable 0x03A
#define SD_CMD12ErrorStatus 0x03C
#define SD_Capabilities 0x040
#define SD_Capabilities_Reserved 0x044
#define SD_MaxCurCap 0x048
#define SD_MaxCurCap_Reserved 0x04C
#define SD_ADMA_SysAddr 0x58
#define SD_SlotInterruptStatus 0x0FC
#define SD_HostControllerVersion 0x0FE
/* SD specific registers in PCI config space */
#define SD_SlotInfo 0x40
#endif /* _SDIOH_H */

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drivers/staging/brcm80211/include/sdiovar.h Normal file
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _sdiovar_h_
#define _sdiovar_h_
#include <typedefs.h>
/* require default structure packing */
#define BWL_DEFAULT_PACKING
#include <packed_section_start.h>
typedef struct sdreg {
int func;
int offset;
int value;
} sdreg_t;
/* Common msglevel constants */
#define SDH_ERROR_VAL 0x0001 /* Error */
#define SDH_TRACE_VAL 0x0002 /* Trace */
#define SDH_INFO_VAL 0x0004 /* Info */
#define SDH_DEBUG_VAL 0x0008 /* Debug */
#define SDH_DATA_VAL 0x0010 /* Data */
#define SDH_CTRL_VAL 0x0020 /* Control Regs */
#define SDH_LOG_VAL 0x0040 /* Enable bcmlog */
#define SDH_DMA_VAL 0x0080 /* DMA */
#define NUM_PREV_TRANSACTIONS 16
#include <packed_section_end.h>
#endif /* _sdiovar_h_ */

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drivers/staging/brcm80211/include/siutils.h Normal file
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _siutils_h_
#define _siutils_h_
#include <hndsoc.h>
#if !defined(WLC_LOW)
#include "bcm_rpc.h"
#endif
/*
* Data structure to export all chip specific common variables
* public (read-only) portion of siutils handle returned by si_attach()
*/
struct si_pub {
uint socitype; /* SOCI_SB, SOCI_AI */
uint bustype; /* SI_BUS, PCI_BUS */
uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
uint buscorerev; /* buscore rev */
uint buscoreidx; /* buscore index */
int ccrev; /* chip common core rev */
uint32 cccaps; /* chip common capabilities */
uint32 cccaps_ext; /* chip common capabilities extension */
int pmurev; /* pmu core rev */
uint32 pmucaps; /* pmu capabilities */
uint boardtype; /* board type */
uint boardvendor; /* board vendor */
uint boardflags; /* board flags */
uint boardflags2; /* board flags2 */
uint chip; /* chip number */
uint chiprev; /* chip revision */
uint chippkg; /* chip package option */
uint32 chipst; /* chip status */
bool issim; /* chip is in simulation or emulation */
uint socirev; /* SOC interconnect rev */
bool pci_pr32414;
#if !defined(WLC_LOW)
rpc_info_t *rpc;
#endif
};
/* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
* for monolithic driver, it is readonly to prevent accident change
*/
#if !defined(WLC_LOW)
typedef struct si_pub si_t;
#else
typedef const struct si_pub si_t;
#endif
/*
* Many of the routines below take an 'sih' handle as their first arg.
* Allocate this by calling si_attach(). Free it by calling si_detach().
* At any one time, the sih is logically focused on one particular si core
* (the "current core").
* Use si_setcore() or si_setcoreidx() to change the association to another core.
*/
#define BADIDX (SI_MAXCORES + 1)
/* clkctl xtal what flags */
#define XTAL 0x1 /* primary crystal oscillator (2050) */
#define PLL 0x2 /* main chip pll */
/* clkctl clk mode */
#define CLK_FAST 0 /* force fast (pll) clock */
#define CLK_DYNAMIC 2 /* enable dynamic clock control */
/* GPIO usage priorities */
#define GPIO_DRV_PRIORITY 0 /* Driver */
#define GPIO_APP_PRIORITY 1 /* Application */
#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
/* GPIO pull up/down */
#define GPIO_PULLUP 0
#define GPIO_PULLDN 1
/* GPIO event regtype */
#define GPIO_REGEVT 0 /* GPIO register event */
#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
/* device path */
#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
/* SI routine enumeration: to be used by update function with multiple hooks */
#define SI_DOATTACH 1
#define SI_PCIDOWN 2
#define SI_PCIUP 3
#define ISSIM_ENAB(sih) 0
/* PMU clock/power control */
#if defined(BCMPMUCTL)
#define PMUCTL_ENAB(sih) (BCMPMUCTL)
#else
#define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
#endif
/* chipcommon clock/power control (exclusive with PMU's) */
#if defined(BCMPMUCTL) && BCMPMUCTL
#define CCCTL_ENAB(sih) (0)
#define CCPLL_ENAB(sih) (0)
#else
#define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
#endif
typedef void (*gpio_handler_t) (uint32 stat, void *arg);
/* External PA enable mask */
#define GPIO_CTRL_EPA_EN_MASK 0x40
/* === exported functions === */
extern si_t *si_attach(uint pcidev, osl_t * osh, void *regs, uint bustype,
void *sdh, char **vars, uint * varsz);
extern void si_detach(si_t * sih);
extern bool si_pci_war16165(si_t * sih);
extern uint si_corelist(si_t * sih, uint coreid[]);
extern uint si_coreid(si_t * sih);
extern uint si_flag(si_t * sih);
extern uint si_intflag(si_t * sih);
extern uint si_coreidx(si_t * sih);
extern uint si_coreunit(si_t * sih);
extern uint si_corevendor(si_t * sih);
extern uint si_corerev(si_t * sih);
extern void *si_osh(si_t * sih);
extern void si_setosh(si_t * sih, osl_t * osh);
extern uint si_corereg(si_t * sih, uint coreidx, uint regoff, uint mask,
uint val);
extern void *si_coreregs(si_t * sih);
extern void si_write_wrapperreg(si_t * sih, uint32 offset, uint32 val);
extern uint32 si_core_cflags(si_t * sih, uint32 mask, uint32 val);
extern void si_core_cflags_wo(si_t * sih, uint32 mask, uint32 val);
extern uint32 si_core_sflags(si_t * sih, uint32 mask, uint32 val);
extern bool si_iscoreup(si_t * sih);
extern uint si_findcoreidx(si_t * sih, uint coreid, uint coreunit);
#ifndef BCMSDIO
extern void *si_setcoreidx(si_t * sih, uint coreidx);
#endif
extern void *si_setcore(si_t * sih, uint coreid, uint coreunit);
extern void *si_switch_core(si_t * sih, uint coreid, uint * origidx,
uint * intr_val);
extern void si_restore_core(si_t * sih, uint coreid, uint intr_val);
extern int si_numaddrspaces(si_t * sih);
extern uint32 si_addrspace(si_t * sih, uint asidx);
extern uint32 si_addrspacesize(si_t * sih, uint asidx);
extern int si_corebist(si_t * sih);
extern void si_core_reset(si_t * sih, uint32 bits, uint32 resetbits);
extern void si_core_disable(si_t * sih, uint32 bits);
extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
extern uint32 si_clock(si_t * sih);
extern uint32 si_alp_clock(si_t * sih);
extern uint32 si_ilp_clock(si_t * sih);
extern void si_pci_setup(si_t * sih, uint coremask);
extern void si_setint(si_t * sih, int siflag);
extern bool si_backplane64(si_t * sih);
extern void si_register_intr_callback(si_t * sih, void *intrsoff_fn,
void *intrsrestore_fn,
void *intrsenabled_fn, void *intr_arg);
extern void si_deregister_intr_callback(si_t * sih);
extern void si_clkctl_init(si_t * sih);
extern uint16 si_clkctl_fast_pwrup_delay(si_t * sih);
extern bool si_clkctl_cc(si_t * sih, uint mode);
extern int si_clkctl_xtal(si_t * sih, uint what, bool on);
extern uint32 si_gpiotimerval(si_t * sih, uint32 mask, uint32 val);
extern bool si_deviceremoved(si_t * sih);
extern uint32 si_socram_size(si_t * sih);
extern uint32 si_socdevram_size(si_t * sih);
extern void si_socdevram(si_t * sih, bool set, uint8 * ennable,
uint8 * protect);
extern bool si_socdevram_pkg(si_t * sih);
extern void si_watchdog(si_t * sih, uint ticks);
extern void si_watchdog_ms(si_t * sih, uint32 ms);
extern void *si_gpiosetcore(si_t * sih);
extern uint32 si_gpiocontrol(si_t * sih, uint32 mask, uint32 val,
uint8 priority);
extern uint32 si_gpioouten(si_t * sih, uint32 mask, uint32 val, uint8 priority);
extern uint32 si_gpioout(si_t * sih, uint32 mask, uint32 val, uint8 priority);
extern uint32 si_gpioin(si_t * sih);
extern uint32 si_gpiointpolarity(si_t * sih, uint32 mask, uint32 val,
uint8 priority);
extern uint32 si_gpiointmask(si_t * sih, uint32 mask, uint32 val,
uint8 priority);
extern uint32 si_gpioled(si_t * sih, uint32 mask, uint32 val);
extern uint32 si_gpioreserve(si_t * sih, uint32 gpio_num, uint8 priority);
extern uint32 si_gpiorelease(si_t * sih, uint32 gpio_num, uint8 priority);
extern uint32 si_gpiopull(si_t * sih, bool updown, uint32 mask, uint32 val);
extern uint32 si_gpioevent(si_t * sih, uint regtype, uint32 mask, uint32 val);
extern uint32 si_gpio_int_enable(si_t * sih, bool enable);
/* GPIO event handlers */
extern void *si_gpio_handler_register(si_t * sih, uint32 e, bool lev,
gpio_handler_t cb, void *arg);
extern void si_gpio_handler_unregister(si_t * sih, void *gpioh);
extern void si_gpio_handler_process(si_t * sih);
/* Wake-on-wireless-LAN (WOWL) */
extern bool si_pci_pmecap(si_t * sih);
struct osl_info;
extern bool si_pci_fastpmecap(struct osl_info *osh);
extern bool si_pci_pmestat(si_t * sih);
extern void si_pci_pmeclr(si_t * sih);
extern void si_pci_pmeen(si_t * sih);
extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
#ifdef BCMSDIO
extern void si_sdio_init(si_t * sih);
#endif
extern uint16 si_d11_devid(si_t * sih);
#define si_eci(sih) 0
#define si_eci_init(sih) (0)
#define si_eci_notify_bt(sih, type, val) (0)
#define si_seci(sih) 0
static INLINE void *si_seci_init(si_t * sih, uint8 use_seci)
{
return NULL;
}
/* OTP status */
extern bool si_is_otp_disabled(si_t * sih);
extern bool si_is_otp_powered(si_t * sih);
extern void si_otp_power(si_t * sih, bool on);
/* SPROM availability */
extern bool si_is_sprom_available(si_t * sih);
extern bool si_is_sprom_enabled(si_t * sih);
extern void si_sprom_enable(si_t * sih, bool enable);
#ifdef SI_SPROM_PROBE
extern void si_sprom_init(si_t * sih);
#endif /* SI_SPROM_PROBE */
/* OTP/SROM CIS stuff */
extern int si_cis_source(si_t * sih);
#define CIS_DEFAULT 0
#define CIS_SROM 1
#define CIS_OTP 2
/* Fab-id information */
#define DEFAULT_FAB 0x0 /* Original/first fab used for this chip */
#define CSM_FAB7 0x1 /* CSM Fab7 chip */
#define TSMC_FAB12 0x2 /* TSMC Fab12/Fab14 chip */
#define SMIC_FAB4 0x3 /* SMIC Fab4 chip */
#define SI_ERROR(args)
#ifdef BCMDBG
#define SI_MSG(args) printf args
#else
#define SI_MSG(args)
#endif /* BCMDBG */
/* Define SI_VMSG to printf for verbose debugging, but don't check it in */
#define SI_VMSG(args)
#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
typedef uint32(*si_intrsoff_t) (void *intr_arg);
typedef void (*si_intrsrestore_t) (void *intr_arg, uint32 arg);
typedef bool(*si_intrsenabled_t) (void *intr_arg);
typedef struct gpioh_item {
void *arg;
bool level;
gpio_handler_t handler;
uint32 event;
struct gpioh_item *next;
} gpioh_item_t;
/* misc si info needed by some of the routines */
typedef struct si_info {
struct si_pub pub; /* back plane public state (must be first field) */
void *osh; /* osl os handle */
void *sdh; /* bcmsdh handle */
uint dev_coreid; /* the core provides driver functions */
void *intr_arg; /* interrupt callback function arg */
si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
void *pch; /* PCI/E core handle */
gpioh_item_t *gpioh_head; /* GPIO event handlers list */
bool memseg; /* flag to toggle MEM_SEG register */
char *vars;
uint varsz;
void *curmap; /* current regs va */
void *regs[SI_MAXCORES]; /* other regs va */
uint curidx; /* current core index */
uint numcores; /* # discovered cores */
uint coreid[SI_MAXCORES]; /* id of each core */
uint32 coresba[SI_MAXCORES]; /* backplane address of each core */
void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */
uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */
uint32 coresba2_size[SI_MAXCORES]; /* second address space size */
void *curwrap; /* current wrapper va */
void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */
uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */
uint32 oob_router; /* oob router registers for axi */
} si_info_t;
#define SI_INFO(sih) (si_info_t *)(uintptr)sih
#define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
ISALIGNED((x), SI_CORE_SIZE))
#define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
#define BADCOREADDR 0
#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
#define NOREV -1 /* Invalid rev */
/* Newer chips can access PCI/PCIE and CC core without requiring to change
* PCI BAR0 WIN
*/
#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
(((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
/*
* Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
* before after core switching to avoid invalid register accesss inside ISR.
*/
#define INTR_OFF(si, intr_val) \
if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
#define INTR_RESTORE(si, intr_val) \
if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
/* dynamic clock control defines */
#define LPOMINFREQ 25000 /* low power oscillator min */
#define LPOMAXFREQ 43000 /* low power oscillator max */
#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
#define PCIMINFREQ 25000000 /* 25 MHz */
#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
#define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
((si)->pub.buscoretype == PCI_CORE_ID))
#define PCIE(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
((si)->pub.buscoretype == PCIE_CORE_ID))
#define PCI_FORCEHT(si) \
(PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
/* GPIO Based LED powersave defines */
#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
#ifndef DEFAULT_GPIOTIMERVAL
#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
#endif
/*
* Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
* The returned path is NULL terminated and has trailing '/'.
* Return 0 on success, nonzero otherwise.
*/
extern int si_devpath(si_t * sih, char *path, int size);
/* Read variable with prepending the devpath to the name */
extern char *si_getdevpathvar(si_t * sih, const char *name);
extern int si_getdevpathintvar(si_t * sih, const char *name);
extern uint8 si_pcieclkreq(si_t * sih, uint32 mask, uint32 val);
extern uint32 si_pcielcreg(si_t * sih, uint32 mask, uint32 val);
extern void si_war42780_clkreq(si_t * sih, bool clkreq);
extern void si_pci_sleep(si_t * sih);
extern void si_pci_down(si_t * sih);
extern void si_pci_up(si_t * sih);
extern void si_pcie_war_ovr_update(si_t * sih, uint8 aspm);
extern void si_pcie_extendL1timer(si_t * sih, bool extend);
extern int si_pci_fixcfg(si_t * sih);
extern void si_chippkg_set(si_t * sih, uint);
extern void si_chipcontrl_epa4331(si_t * sih, bool on);
/* Enable Ex-PA for 4313 */
extern void si_epa_4313war(si_t * sih);
/* === debug routines === */
extern uint32 si_pciereg(si_t * sih, uint32 offset, uint32 mask, uint32 val,
uint type);
extern uint32 si_pcieserdesreg(si_t * sih, uint32 mdioslave, uint32 offset,
uint32 mask, uint32 val);
char *si_getnvramflvar(si_t * sih, const char *name);
/* AMBA Interconnect exported externs */
extern si_t *ai_attach(uint pcidev, osl_t * osh, void *regs, uint bustype,
void *sdh, char **vars, uint * varsz);
extern si_t *ai_kattach(osl_t * osh);
extern void ai_scan(si_t * sih, void *regs, uint devid);
extern uint ai_flag(si_t * sih);
extern void ai_setint(si_t * sih, int siflag);
extern uint ai_coreidx(si_t * sih);
extern uint ai_corevendor(si_t * sih);
extern uint ai_corerev(si_t * sih);
extern bool ai_iscoreup(si_t * sih);
extern void *ai_setcoreidx(si_t * sih, uint coreidx);
extern uint32 ai_core_cflags(si_t * sih, uint32 mask, uint32 val);
extern void ai_core_cflags_wo(si_t * sih, uint32 mask, uint32 val);
extern uint32 ai_core_sflags(si_t * sih, uint32 mask, uint32 val);
extern uint ai_corereg(si_t * sih, uint coreidx, uint regoff, uint mask,
uint val);
extern void ai_core_reset(si_t * sih, uint32 bits, uint32 resetbits);
extern void ai_core_disable(si_t * sih, uint32 bits);
extern int ai_numaddrspaces(si_t * sih);
extern uint32 ai_addrspace(si_t * sih, uint asidx);
extern uint32 ai_addrspacesize(si_t * sih, uint asidx);
extern void ai_write_wrap_reg(si_t * sih, uint32 offset, uint32 val);
#ifdef BCMDBG
extern void ai_view(si_t * sih, bool verbose);
#endif
#ifdef BCMSDIO
#define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx)
#define si_coreid(sih) sb_coreid(sih)
#define si_corerev(sih) sb_corerev(sih)
#endif
#endif /* _siutils_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SPI_H
#define _SPI_H
/*
* Brcm SPI Device Register Map.
*
*/
typedef volatile struct {
uint8 config; /* 0x00, len, endian, clock, speed, polarity, wakeup */
uint8 response_delay; /* 0x01, read response delay in bytes (corerev < 3) */
uint8 status_enable; /* 0x02, status-enable, intr with status, response_delay
* function selection, command/data error check
*/
uint8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */
uint16 intr_reg; /* 0x04, Intr status register */
uint16 intr_en_reg; /* 0x06, Intr mask register */
uint32 status_reg; /* 0x08, RO, Status bits of last spi transfer */
uint16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */
uint16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */
uint16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */
uint32 test_read; /* 0x14, RO 0xfeedbead signature */
uint32 test_rw; /* 0x18, RW */
uint8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */
uint8 resp_delay_f1; /* 0x1d, read resp delay bytes for F1 (corerev >= 3) */
uint8 resp_delay_f2; /* 0x1e, read resp delay bytes for F2 (corerev >= 3) */
uint8 resp_delay_f3; /* 0x1f, read resp delay bytes for F3 (corerev >= 3) */
} spi_regs_t;
/* SPI device register offsets */
#define SPID_CONFIG 0x00
#define SPID_RESPONSE_DELAY 0x01
#define SPID_STATUS_ENABLE 0x02
#define SPID_RESET_BP 0x03 /* (corerev >= 1) */
#define SPID_INTR_REG 0x04 /* 16 bits - Interrupt status */
#define SPID_INTR_EN_REG 0x06 /* 16 bits - Interrupt mask */
#define SPID_STATUS_REG 0x08 /* 32 bits */
#define SPID_F1_INFO_REG 0x0C /* 16 bits */
#define SPID_F2_INFO_REG 0x0E /* 16 bits */
#define SPID_F3_INFO_REG 0x10 /* 16 bits */
#define SPID_TEST_READ 0x14 /* 32 bits */
#define SPID_TEST_RW 0x18 /* 32 bits */
#define SPID_RESP_DELAY_F0 0x1c /* 8 bits (corerev >= 3) */
#define SPID_RESP_DELAY_F1 0x1d /* 8 bits (corerev >= 3) */
#define SPID_RESP_DELAY_F2 0x1e /* 8 bits (corerev >= 3) */
#define SPID_RESP_DELAY_F3 0x1f /* 8 bits (corerev >= 3) */
/* Bit masks for SPID_CONFIG device register */
#define WORD_LENGTH_32 0x1 /* 0/1 16/32 bit word length */
#define ENDIAN_BIG 0x2 /* 0/1 Little/Big Endian */
#define CLOCK_PHASE 0x4 /* 0/1 clock phase delay */
#define CLOCK_POLARITY 0x8 /* 0/1 Idle state clock polarity is low/high */
#define HIGH_SPEED_MODE 0x10 /* 1/0 High Speed mode / Normal mode */
#define INTR_POLARITY 0x20 /* 1/0 Interrupt active polarity is high/low */
#define WAKE_UP 0x80 /* 0/1 Wake-up command from Host to WLAN */
/* Bit mask for SPID_RESPONSE_DELAY device register */
#define RESPONSE_DELAY_MASK 0xFF /* Configurable rd response delay in multiples of 8 bits */
/* Bit mask for SPID_STATUS_ENABLE device register */
#define STATUS_ENABLE 0x1 /* 1/0 Status sent/not sent to host after read/write */
#define INTR_WITH_STATUS 0x2 /* 0/1 Do-not / do-interrupt if status is sent */
#define RESP_DELAY_ALL 0x4 /* Applicability of resp delay to F1 or all func's read */
#define DWORD_PKT_LEN_EN 0x8 /* Packet len denoted in dwords instead of bytes */
#define CMD_ERR_CHK_EN 0x20 /* Command error check enable */
#define DATA_ERR_CHK_EN 0x40 /* Data error check enable */
/* Bit mask for SPID_RESET_BP device register */
#define RESET_ON_WLAN_BP_RESET 0x4 /* enable reset for WLAN backplane */
#define RESET_ON_BT_BP_RESET 0x8 /* enable reset for BT backplane */
#define RESET_SPI 0x80 /* reset the above enabled logic */
/* Bit mask for SPID_INTR_REG device register */
#define DATA_UNAVAILABLE 0x0001 /* Requested data not available; Clear by writing a "1" */
#define F2_F3_FIFO_RD_UNDERFLOW 0x0002
#define F2_F3_FIFO_WR_OVERFLOW 0x0004
#define COMMAND_ERROR 0x0008 /* Cleared by writing 1 */
#define DATA_ERROR 0x0010 /* Cleared by writing 1 */
#define F2_PACKET_AVAILABLE 0x0020
#define F3_PACKET_AVAILABLE 0x0040
#define F1_OVERFLOW 0x0080 /* Due to last write. Bkplane has pending write requests */
#define MISC_INTR0 0x0100
#define MISC_INTR1 0x0200
#define MISC_INTR2 0x0400
#define MISC_INTR3 0x0800
#define MISC_INTR4 0x1000
#define F1_INTR 0x2000
#define F2_INTR 0x4000
#define F3_INTR 0x8000
/* Bit mask for 32bit SPID_STATUS_REG device register */
#define STATUS_DATA_NOT_AVAILABLE 0x00000001
#define STATUS_UNDERFLOW 0x00000002
#define STATUS_OVERFLOW 0x00000004
#define STATUS_F2_INTR 0x00000008
#define STATUS_F3_INTR 0x00000010
#define STATUS_F2_RX_READY 0x00000020
#define STATUS_F3_RX_READY 0x00000040
#define STATUS_HOST_CMD_DATA_ERR 0x00000080
#define STATUS_F2_PKT_AVAILABLE 0x00000100
#define STATUS_F2_PKT_LEN_MASK 0x000FFE00
#define STATUS_F2_PKT_LEN_SHIFT 9
#define STATUS_F3_PKT_AVAILABLE 0x00100000
#define STATUS_F3_PKT_LEN_MASK 0xFFE00000
#define STATUS_F3_PKT_LEN_SHIFT 21
/* Bit mask for 16 bits SPID_F1_INFO_REG device register */
#define F1_ENABLED 0x0001
#define F1_RDY_FOR_DATA_TRANSFER 0x0002
#define F1_MAX_PKT_SIZE 0x01FC
/* Bit mask for 16 bits SPID_F2_INFO_REG device register */
#define F2_ENABLED 0x0001
#define F2_RDY_FOR_DATA_TRANSFER 0x0002
#define F2_MAX_PKT_SIZE 0x3FFC
/* Bit mask for 16 bits SPID_F3_INFO_REG device register */
#define F3_ENABLED 0x0001
#define F3_RDY_FOR_DATA_TRANSFER 0x0002
#define F3_MAX_PKT_SIZE 0x3FFC
/* Bit mask for 32 bits SPID_TEST_READ device register read in 16bit LE mode */
#define TEST_RO_DATA_32BIT_LE 0xFEEDBEAD
/* Maximum number of I/O funcs */
#define SPI_MAX_IOFUNCS 4
#define SPI_MAX_PKT_LEN (2048*4)
/* Misc defines */
#define SPI_FUNC_0 0
#define SPI_FUNC_1 1
#define SPI_FUNC_2 2
#define SPI_FUNC_3 3
#define WAIT_F2RXFIFORDY 100
#define WAIT_F2RXFIFORDY_DELAY 20
#endif /* _SPI_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _TYPEDEFS_H_
#define _TYPEDEFS_H_
/*
* Infer the compile environment based on preprocessor symbols and pragmas.
* Override type definitions as needed, and include configuration-dependent
* header files to define types.
*/
#if defined(__x86_64__)
#define TYPEDEF_UINTPTR
typedef unsigned long long int uintptr;
#endif
#if defined(_NEED_SIZE_T_)
typedef long unsigned int size_t;
#endif
#define TYPEDEF_UINT
#define TYPEDEF_USHORT
#define TYPEDEF_ULONG
#include <linux/version.h>
#define TYPEDEF_BOOL
/* Do not support the (u)int64 types with strict ansi for GNU C */
#if defined(__GNUC__) && defined(__STRICT_ANSI__)
#define TYPEDEF_INT64
#define TYPEDEF_UINT64
#endif
#include <linux/types.h>
/*
* Default Typedefs
*/
#ifndef TYPEDEF_BOOL
typedef /* @abstract@ */ unsigned char bool;
#endif
/* define uchar, ushort, uint, ulong */
#ifndef TYPEDEF_UCHAR
typedef unsigned char uchar;
#endif
#ifndef TYPEDEF_USHORT
typedef unsigned short ushort;
#endif
#ifndef TYPEDEF_UINT
typedef unsigned int uint;
#endif
#ifndef TYPEDEF_ULONG
typedef unsigned long ulong;
#endif
/* define [u]int8/16/32/64, uintptr */
#ifndef TYPEDEF_UINT8
typedef unsigned char uint8;
#endif
#ifndef TYPEDEF_UINT16
typedef unsigned short uint16;
#endif
#ifndef TYPEDEF_UINT32
typedef unsigned int uint32;
#endif
#ifndef TYPEDEF_UINT64
typedef unsigned long long uint64;
#endif
#ifndef TYPEDEF_UINTPTR
typedef unsigned int uintptr;
#endif
#ifndef TYPEDEF_INT8
typedef signed char int8;
#endif
#ifndef TYPEDEF_INT16
typedef signed short int16;
#endif
#ifndef TYPEDEF_INT32
typedef signed int int32;
#endif
#ifndef TYPEDEF_INT64
typedef signed long long int64;
#endif
/* define float32/64, float_t */
#ifndef TYPEDEF_FLOAT32
typedef float float32;
#endif
#ifndef TYPEDEF_FLOAT64
typedef double float64;
#endif
/*
* abstracted floating point type allows for compile time selection of
* single or double precision arithmetic. Compiling with -DFLOAT32
* selects single precision; the default is double precision.
*/
#ifndef TYPEDEF_FLOAT_T
#if defined(FLOAT32)
typedef float32 float_t;
#else /* default to double precision floating point */
typedef float64 float_t;
#endif
#endif /* TYPEDEF_FLOAT_T */
/* define macro values */
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1 /* TRUE */
#endif
#ifndef NULL
#define NULL 0
#endif
#ifndef OFF
#define OFF 0
#endif
#ifndef ON
#define ON 1 /* ON = 1 */
#endif
#define AUTO (-1) /* Auto = -1 */
/* define PTRSZ, INLINE */
#ifndef PTRSZ
#define PTRSZ sizeof(char*)
#endif
/* Detect compiler type. */
#if defined(__GNUC__)
#define BWL_COMPILER_GNU
#elif defined(__CC_ARM) && __CC_ARM
#define BWL_COMPILER_ARMCC
#else
#error "Unknown compiler!"
#endif
#ifndef INLINE
#if defined(BWL_COMPILER_GNU)
#define INLINE __inline__
#elif defined(BWL_COMPILER_ARMCC)
#define INLINE __inline
#else
#define INLINE
#endif
#endif /* INLINE */
#undef TYPEDEF_BOOL
#undef TYPEDEF_UCHAR
#undef TYPEDEF_USHORT
#undef TYPEDEF_UINT
#undef TYPEDEF_ULONG
#undef TYPEDEF_UINT8
#undef TYPEDEF_UINT16
#undef TYPEDEF_UINT32
#undef TYPEDEF_UINT64
#undef TYPEDEF_UINTPTR
#undef TYPEDEF_INT8
#undef TYPEDEF_INT16
#undef TYPEDEF_INT32
#undef TYPEDEF_INT64
#undef TYPEDEF_FLOAT32
#undef TYPEDEF_FLOAT64
#undef TYPEDEF_FLOAT_T
/* Suppress unused parameter warning */
#define UNUSED_PARAMETER(x) (void)(x)
/*
* Including the bcmdefs.h here, to make sure everyone including typedefs.h
* gets this automatically
*/
#include <bcmdefs.h>
#endif /* _TYPEDEFS_H_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef phy_version_h_
#define phy_version_h_
#define PHY_MAJOR_VERSION 1
#define PHY_MINOR_VERSION 82
#define PHY_RC_NUMBER 8
#define PHY_INCREMENTAL_NUMBER 0
#define PHY_BUILD_NUMBER 0
#define PHY_VERSION 1, 82, 8, 0
#define PHY_VERSION_NUM 0x01520800
#define PHY_VERSION_STR "1.82.8.0"
#endif /* phy_version_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_phy_h_
#define _wlc_phy_h_
#include <typedefs.h>
#include <wlioctl.h>
#include <siutils.h>
#include <d11.h>
#include <wlc_phy_shim.h>
#define IDCODE_VER_MASK 0x0000000f
#define IDCODE_VER_SHIFT 0
#define IDCODE_MFG_MASK 0x00000fff
#define IDCODE_MFG_SHIFT 0
#define IDCODE_ID_MASK 0x0ffff000
#define IDCODE_ID_SHIFT 12
#define IDCODE_REV_MASK 0xf0000000
#define IDCODE_REV_SHIFT 28
#define NORADIO_ID 0xe4f5
#define NORADIO_IDCODE 0x4e4f5246
#define BCM2055_ID 0x2055
#define BCM2055_IDCODE 0x02055000
#define BCM2055A0_IDCODE 0x1205517f
#define BCM2056_ID 0x2056
#define BCM2056_IDCODE 0x02056000
#define BCM2056A0_IDCODE 0x1205617f
#define BCM2057_ID 0x2057
#define BCM2057_IDCODE 0x02057000
#define BCM2057A0_IDCODE 0x1205717f
#define BCM2064_ID 0x2064
#define BCM2064_IDCODE 0x02064000
#define BCM2064A0_IDCODE 0x0206417f
#define PHY_TPC_HW_OFF FALSE
#define PHY_TPC_HW_ON TRUE
#define PHY_PERICAL_DRIVERUP 1
#define PHY_PERICAL_WATCHDOG 2
#define PHY_PERICAL_PHYINIT 3
#define PHY_PERICAL_JOIN_BSS 4
#define PHY_PERICAL_START_IBSS 5
#define PHY_PERICAL_UP_BSS 6
#define PHY_PERICAL_CHAN 7
#define PHY_FULLCAL 8
#define PHY_PERICAL_DISABLE 0
#define PHY_PERICAL_SPHASE 1
#define PHY_PERICAL_MPHASE 2
#define PHY_PERICAL_MANUAL 3
#define PHY_HOLD_FOR_ASSOC 1
#define PHY_HOLD_FOR_SCAN 2
#define PHY_HOLD_FOR_RM 4
#define PHY_HOLD_FOR_PLT 8
#define PHY_HOLD_FOR_MUTE 16
#define PHY_HOLD_FOR_NOT_ASSOC 0x20
#define PHY_MUTE_FOR_PREISM 1
#define PHY_MUTE_ALL 0xffffffff
#define PHY_NOISE_FIXED_VAL (-95)
#define PHY_NOISE_FIXED_VAL_NPHY (-92)
#define PHY_NOISE_FIXED_VAL_LCNPHY (-92)
#define PHY_MODE_CAL 0x0002
#define PHY_MODE_NOISEM 0x0004
#define WLC_TXPWR_DB_FACTOR 4
#define WLC_NUM_RATES_CCK 4
#define WLC_NUM_RATES_OFDM 8
#define WLC_NUM_RATES_MCS_1_STREAM 8
#define WLC_NUM_RATES_MCS_2_STREAM 8
#define WLC_NUM_RATES_MCS_3_STREAM 8
#define WLC_NUM_RATES_MCS_4_STREAM 8
typedef struct txpwr_limits {
uint8 cck[WLC_NUM_RATES_CCK];
uint8 ofdm[WLC_NUM_RATES_OFDM];
uint8 ofdm_cdd[WLC_NUM_RATES_OFDM];
uint8 ofdm_40_siso[WLC_NUM_RATES_OFDM];
uint8 ofdm_40_cdd[WLC_NUM_RATES_OFDM];
uint8 mcs_20_siso[WLC_NUM_RATES_MCS_1_STREAM];
uint8 mcs_20_cdd[WLC_NUM_RATES_MCS_1_STREAM];
uint8 mcs_20_stbc[WLC_NUM_RATES_MCS_1_STREAM];
uint8 mcs_20_mimo[WLC_NUM_RATES_MCS_2_STREAM];
uint8 mcs_40_siso[WLC_NUM_RATES_MCS_1_STREAM];
uint8 mcs_40_cdd[WLC_NUM_RATES_MCS_1_STREAM];
uint8 mcs_40_stbc[WLC_NUM_RATES_MCS_1_STREAM];
uint8 mcs_40_mimo[WLC_NUM_RATES_MCS_2_STREAM];
uint8 mcs32;
} txpwr_limits_t;
typedef struct {
uint8 vec[MAXCHANNEL / NBBY];
} chanvec_t;
struct rpc_info;
typedef struct shared_phy shared_phy_t;
struct phy_pub;
#ifdef WLC_HIGH_ONLY
typedef struct wlc_rpc_phy wlc_phy_t;
#else
typedef struct phy_pub wlc_phy_t;
#endif
typedef struct shared_phy_params {
void *osh;
si_t *sih;
void *physhim;
uint unit;
uint corerev;
uint bustype;
uint buscorerev;
char *vars;
uint16 vid;
uint16 did;
uint chip;
uint chiprev;
uint chippkg;
uint sromrev;
uint boardtype;
uint boardrev;
uint boardvendor;
uint32 boardflags;
uint32 boardflags2;
} shared_phy_params_t;
#ifdef WLC_LOW
extern shared_phy_t *wlc_phy_shared_attach(shared_phy_params_t * shp);
extern void wlc_phy_shared_detach(shared_phy_t * phy_sh);
extern wlc_phy_t *wlc_phy_attach(shared_phy_t * sh, void *regs, int bandtype,
char *vars);
extern void wlc_phy_detach(wlc_phy_t * ppi);
extern bool wlc_phy_get_phyversion(wlc_phy_t * pih, uint16 * phytype,
uint16 * phyrev, uint16 * radioid,
uint16 * radiover);
extern bool wlc_phy_get_encore(wlc_phy_t * pih);
extern uint32 wlc_phy_get_coreflags(wlc_phy_t * pih);
extern void wlc_phy_hw_clk_state_upd(wlc_phy_t * ppi, bool newstate);
extern void wlc_phy_hw_state_upd(wlc_phy_t * ppi, bool newstate);
extern void wlc_phy_init(wlc_phy_t * ppi, chanspec_t chanspec);
extern void wlc_phy_watchdog(wlc_phy_t * ppi);
extern int wlc_phy_down(wlc_phy_t * ppi);
extern uint32 wlc_phy_clk_bwbits(wlc_phy_t * pih);
extern void wlc_phy_cal_init(wlc_phy_t * ppi);
extern void wlc_phy_antsel_init(wlc_phy_t * ppi, bool lut_init);
extern void wlc_phy_chanspec_set(wlc_phy_t * ppi, chanspec_t chanspec);
extern chanspec_t wlc_phy_chanspec_get(wlc_phy_t * ppi);
extern void wlc_phy_chanspec_radio_set(wlc_phy_t * ppi, chanspec_t newch);
extern uint16 wlc_phy_bw_state_get(wlc_phy_t * ppi);
extern void wlc_phy_bw_state_set(wlc_phy_t * ppi, uint16 bw);
extern void wlc_phy_rssi_compute(wlc_phy_t * pih, void *ctx);
extern void wlc_phy_por_inform(wlc_phy_t * ppi);
extern void wlc_phy_noise_sample_intr(wlc_phy_t * ppi);
extern bool wlc_phy_bist_check_phy(wlc_phy_t * ppi);
extern void wlc_phy_set_deaf(wlc_phy_t * ppi, bool user_flag);
extern void wlc_phy_switch_radio(wlc_phy_t * ppi, bool on);
extern void wlc_phy_anacore(wlc_phy_t * ppi, bool on);
#endif /* WLC_LOW */
extern void wlc_phy_BSSinit(wlc_phy_t * ppi, bool bonlyap, int rssi);
extern void wlc_phy_chanspec_ch14_widefilter_set(wlc_phy_t * ppi,
bool wide_filter);
extern void wlc_phy_chanspec_band_validch(wlc_phy_t * ppi, uint band,
chanvec_t * channels);
extern chanspec_t wlc_phy_chanspec_band_firstch(wlc_phy_t * ppi, uint band);
extern void wlc_phy_txpower_sromlimit(wlc_phy_t * ppi, uint chan,
uint8 * _min_, uint8 * _max_, int rate);
extern void wlc_phy_txpower_sromlimit_max_get(wlc_phy_t * ppi, uint chan,
uint8 * _max_, uint8 * _min_);
extern void wlc_phy_txpower_boardlimit_band(wlc_phy_t * ppi, uint band, int32 *,
int32 *, uint32 *);
extern void wlc_phy_txpower_limit_set(wlc_phy_t * ppi, struct txpwr_limits *,
chanspec_t chanspec);
extern int wlc_phy_txpower_get(wlc_phy_t * ppi, uint * qdbm, bool * override);
extern int wlc_phy_txpower_set(wlc_phy_t * ppi, uint qdbm, bool override);
extern void wlc_phy_txpower_target_set(wlc_phy_t * ppi, struct txpwr_limits *);
extern bool wlc_phy_txpower_hw_ctrl_get(wlc_phy_t * ppi);
extern void wlc_phy_txpower_hw_ctrl_set(wlc_phy_t * ppi, bool hwpwrctrl);
extern uint8 wlc_phy_txpower_get_target_min(wlc_phy_t * ppi);
extern uint8 wlc_phy_txpower_get_target_max(wlc_phy_t * ppi);
extern bool wlc_phy_txpower_ipa_ison(wlc_phy_t * pih);
extern void wlc_phy_stf_chain_init(wlc_phy_t * pih, uint8 txchain,
uint8 rxchain);
extern void wlc_phy_stf_chain_set(wlc_phy_t * pih, uint8 txchain,
uint8 rxchain);
extern void wlc_phy_stf_chain_get(wlc_phy_t * pih, uint8 * txchain,
uint8 * rxchain);
extern uint8 wlc_phy_stf_chain_active_get(wlc_phy_t * pih);
extern int8 wlc_phy_stf_ssmode_get(wlc_phy_t * pih, chanspec_t chanspec);
extern void wlc_phy_ldpc_override_set(wlc_phy_t * ppi, bool val);
extern void wlc_phy_cal_perical(wlc_phy_t * ppi, uint8 reason);
extern void wlc_phy_noise_sample_request_external(wlc_phy_t * ppi);
extern void wlc_phy_edcrs_lock(wlc_phy_t * pih, bool lock);
extern void wlc_phy_cal_papd_recal(wlc_phy_t * ppi);
extern void wlc_phy_ant_rxdiv_set(wlc_phy_t * ppi, uint8 val);
extern bool wlc_phy_ant_rxdiv_get(wlc_phy_t * ppi, uint8 * pval);
extern void wlc_phy_clear_tssi(wlc_phy_t * ppi);
extern void wlc_phy_hold_upd(wlc_phy_t * ppi, mbool id, bool val);
extern void wlc_phy_mute_upd(wlc_phy_t * ppi, bool val, mbool flags);
extern void wlc_phy_antsel_type_set(wlc_phy_t * ppi, uint8 antsel_type);
extern void wlc_phy_txpower_get_current(wlc_phy_t * ppi, tx_power_t * power,
uint channel);
extern void wlc_phy_initcal_enable(wlc_phy_t * pih, bool initcal);
extern bool wlc_phy_test_ison(wlc_phy_t * ppi);
extern void wlc_phy_txpwr_percent_set(wlc_phy_t * ppi, uint8 txpwr_percent);
extern void wlc_phy_ofdm_rateset_war(wlc_phy_t * pih, bool war);
extern void wlc_phy_bf_preempt_enable(wlc_phy_t * pih, bool bf_preempt);
extern void wlc_phy_machwcap_set(wlc_phy_t * ppi, uint32 machwcap);
extern void wlc_phy_runbist_config(wlc_phy_t * ppi, bool start_end);
extern void wlc_phy_freqtrack_start(wlc_phy_t * ppi);
extern void wlc_phy_freqtrack_end(wlc_phy_t * ppi);
extern const uint8 *wlc_phy_get_ofdm_rate_lookup(void);
extern int8 wlc_phy_get_tx_power_offset_by_mcs(wlc_phy_t * ppi,
uint8 mcs_offset);
extern int8 wlc_phy_get_tx_power_offset(wlc_phy_t * ppi, uint8 tbl_offset);
#endif /* _wlc_phy_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_phy_lcn_h_
#define _wlc_phy_lcn_h_
#include <typedefs.h>
struct phy_info_lcnphy {
int lcnphy_txrf_sp_9_override;
uint8 lcnphy_full_cal_channel;
uint8 lcnphy_cal_counter;
uint16 lcnphy_cal_temper;
bool lcnphy_recal;
uint8 lcnphy_rc_cap;
uint32 lcnphy_mcs20_po;
uint8 lcnphy_tr_isolation_mid;
uint8 lcnphy_tr_isolation_low;
uint8 lcnphy_tr_isolation_hi;
uint8 lcnphy_bx_arch;
uint8 lcnphy_rx_power_offset;
uint8 lcnphy_rssi_vf;
uint8 lcnphy_rssi_vc;
uint8 lcnphy_rssi_gs;
uint8 lcnphy_tssi_val;
uint8 lcnphy_rssi_vf_lowtemp;
uint8 lcnphy_rssi_vc_lowtemp;
uint8 lcnphy_rssi_gs_lowtemp;
uint8 lcnphy_rssi_vf_hightemp;
uint8 lcnphy_rssi_vc_hightemp;
uint8 lcnphy_rssi_gs_hightemp;
int16 lcnphy_pa0b0;
int16 lcnphy_pa0b1;
int16 lcnphy_pa0b2;
uint16 lcnphy_rawtempsense;
uint8 lcnphy_measPower;
uint8 lcnphy_tempsense_slope;
uint8 lcnphy_freqoffset_corr;
uint8 lcnphy_tempsense_option;
uint8 lcnphy_tempcorrx;
bool lcnphy_iqcal_swp_dis;
bool lcnphy_hw_iqcal_en;
uint lcnphy_bandedge_corr;
bool lcnphy_spurmod;
uint16 lcnphy_tssi_tx_cnt;
uint16 lcnphy_tssi_idx;
uint16 lcnphy_tssi_npt;
uint16 lcnphy_target_tx_freq;
int8 lcnphy_tx_power_idx_override;
uint16 lcnphy_noise_samples;
uint32 lcnphy_papdRxGnIdx;
uint32 lcnphy_papd_rxGnCtrl_init;
uint32 lcnphy_gain_idx_14_lowword;
uint32 lcnphy_gain_idx_14_hiword;
uint32 lcnphy_gain_idx_27_lowword;
uint32 lcnphy_gain_idx_27_hiword;
int16 lcnphy_ofdmgainidxtableoffset;
int16 lcnphy_dsssgainidxtableoffset;
uint32 lcnphy_tr_R_gain_val;
uint32 lcnphy_tr_T_gain_val;
int8 lcnphy_input_pwr_offset_db;
uint16 lcnphy_Med_Low_Gain_db;
uint16 lcnphy_Very_Low_Gain_db;
int8 lcnphy_lastsensed_temperature;
int8 lcnphy_pkteng_rssi_slope;
uint8 lcnphy_saved_tx_user_target[TXP_NUM_RATES];
uint8 lcnphy_volt_winner;
uint8 lcnphy_volt_low;
uint8 lcnphy_54_48_36_24mbps_backoff;
uint8 lcnphy_11n_backoff;
uint8 lcnphy_lowerofdm;
uint8 lcnphy_cck;
uint8 lcnphy_psat_2pt3_detected;
int32 lcnphy_lowest_Re_div_Im;
int8 lcnphy_final_papd_cal_idx;
uint16 lcnphy_extstxctrl4;
uint16 lcnphy_extstxctrl0;
uint16 lcnphy_extstxctrl1;
int16 lcnphy_cck_dig_filt_type;
int16 lcnphy_ofdm_dig_filt_type;
lcnphy_cal_results_t lcnphy_cal_results;
uint8 lcnphy_psat_pwr;
uint8 lcnphy_psat_indx;
int32 lcnphy_min_phase;
uint8 lcnphy_final_idx;
uint8 lcnphy_start_idx;
uint8 lcnphy_current_index;
uint16 lcnphy_logen_buf_1;
uint16 lcnphy_local_ovr_2;
uint16 lcnphy_local_oval_6;
uint16 lcnphy_local_oval_5;
uint16 lcnphy_logen_mixer_1;
uint8 lcnphy_aci_stat;
uint lcnphy_aci_start_time;
int8 lcnphy_tx_power_offset[TXP_NUM_RATES];
};
#endif /* _wlc_phy_lcn_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define NPHY_TBL_ID_GAIN1 0
#define NPHY_TBL_ID_GAIN2 1
#define NPHY_TBL_ID_GAINBITS1 2
#define NPHY_TBL_ID_GAINBITS2 3
#define NPHY_TBL_ID_GAINLIMIT 4
#define NPHY_TBL_ID_WRSSIGainLimit 5
#define NPHY_TBL_ID_RFSEQ 7
#define NPHY_TBL_ID_AFECTRL 8
#define NPHY_TBL_ID_ANTSWCTRLLUT 9
#define NPHY_TBL_ID_IQLOCAL 15
#define NPHY_TBL_ID_NOISEVAR 16
#define NPHY_TBL_ID_SAMPLEPLAY 17
#define NPHY_TBL_ID_CORE1TXPWRCTL 26
#define NPHY_TBL_ID_CORE2TXPWRCTL 27
#define NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL 30
#define NPHY_TBL_ID_EPSILONTBL0 31
#define NPHY_TBL_ID_SCALARTBL0 32
#define NPHY_TBL_ID_EPSILONTBL1 33
#define NPHY_TBL_ID_SCALARTBL1 34
#define NPHY_TO_BPHY_OFF 0xc00
#define NPHY_BandControl_currentBand 0x0001
#define RFCC_CHIP0_PU 0x0400
#define RFCC_POR_FORCE 0x0040
#define RFCC_OE_POR_FORCE 0x0080
#define NPHY_RfctrlIntc_override_OFF 0
#define NPHY_RfctrlIntc_override_TRSW 1
#define NPHY_RfctrlIntc_override_PA 2
#define NPHY_RfctrlIntc_override_EXT_LNA_PU 3
#define NPHY_RfctrlIntc_override_EXT_LNA_GAIN 4
#define RIFS_ENABLE 0x80
#define BPHY_BAND_SEL_UP20 0x10
#define NPHY_MLenable 0x02
#define NPHY_RfseqMode_CoreActv_override 0x0001
#define NPHY_RfseqMode_Trigger_override 0x0002
#define NPHY_RfseqCoreActv_TxRxChain0 (0x11)
#define NPHY_RfseqCoreActv_TxRxChain1 (0x22)
#define NPHY_RfseqTrigger_rx2tx 0x0001
#define NPHY_RfseqTrigger_tx2rx 0x0002
#define NPHY_RfseqTrigger_updategainh 0x0004
#define NPHY_RfseqTrigger_updategainl 0x0008
#define NPHY_RfseqTrigger_updategainu 0x0010
#define NPHY_RfseqTrigger_reset2rx 0x0020
#define NPHY_RfseqStatus_rx2tx 0x0001
#define NPHY_RfseqStatus_tx2rx 0x0002
#define NPHY_RfseqStatus_updategainh 0x0004
#define NPHY_RfseqStatus_updategainl 0x0008
#define NPHY_RfseqStatus_updategainu 0x0010
#define NPHY_RfseqStatus_reset2rx 0x0020
#define NPHY_ClassifierCtrl_cck_en 0x1
#define NPHY_ClassifierCtrl_ofdm_en 0x2
#define NPHY_ClassifierCtrl_waited_en 0x4
#define NPHY_IQFlip_ADC1 0x0001
#define NPHY_IQFlip_ADC2 0x0010
#define NPHY_sampleCmd_STOP 0x0002
#define RX_GF_OR_MM 0x0004
#define RX_GF_MM_AUTO 0x0100
#define NPHY_iqloCalCmdGctl_IQLO_CAL_EN 0x8000
#define NPHY_IqestCmd_iqstart 0x1
#define NPHY_IqestCmd_iqMode 0x2
#define NPHY_TxPwrCtrlCmd_pwrIndex_init 0x40
#define NPHY_TxPwrCtrlCmd_pwrIndex_init_rev7 0x19
#define PRIM_SEL_UP20 0x8000
#define NPHY_RFSEQ_RX2TX 0x0
#define NPHY_RFSEQ_TX2RX 0x1
#define NPHY_RFSEQ_RESET2RX 0x2
#define NPHY_RFSEQ_UPDATEGAINH 0x3
#define NPHY_RFSEQ_UPDATEGAINL 0x4
#define NPHY_RFSEQ_UPDATEGAINU 0x5
#define NPHY_RFSEQ_CMD_NOP 0x0
#define NPHY_RFSEQ_CMD_RXG_FBW 0x1
#define NPHY_RFSEQ_CMD_TR_SWITCH 0x2
#define NPHY_RFSEQ_CMD_EXT_PA 0x3
#define NPHY_RFSEQ_CMD_RXPD_TXPD 0x4
#define NPHY_RFSEQ_CMD_TX_GAIN 0x5
#define NPHY_RFSEQ_CMD_RX_GAIN 0x6
#define NPHY_RFSEQ_CMD_SET_HPF_BW 0x7
#define NPHY_RFSEQ_CMD_CLR_HIQ_DIS 0x8
#define NPHY_RFSEQ_CMD_END 0xf
#define NPHY_REV3_RFSEQ_CMD_NOP 0x0
#define NPHY_REV3_RFSEQ_CMD_RXG_FBW 0x1
#define NPHY_REV3_RFSEQ_CMD_TR_SWITCH 0x2
#define NPHY_REV3_RFSEQ_CMD_INT_PA_PU 0x3
#define NPHY_REV3_RFSEQ_CMD_EXT_PA 0x4
#define NPHY_REV3_RFSEQ_CMD_RXPD_TXPD 0x5
#define NPHY_REV3_RFSEQ_CMD_TX_GAIN 0x6
#define NPHY_REV3_RFSEQ_CMD_RX_GAIN 0x7
#define NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS 0x8
#define NPHY_REV3_RFSEQ_CMD_SET_HPF_H_HPC 0x9
#define NPHY_REV3_RFSEQ_CMD_SET_LPF_H_HPC 0xa
#define NPHY_REV3_RFSEQ_CMD_SET_HPF_M_HPC 0xb
#define NPHY_REV3_RFSEQ_CMD_SET_LPF_M_HPC 0xc
#define NPHY_REV3_RFSEQ_CMD_SET_HPF_L_HPC 0xd
#define NPHY_REV3_RFSEQ_CMD_SET_LPF_L_HPC 0xe
#define NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS 0xf
#define NPHY_REV3_RFSEQ_CMD_END 0x1f
#define NPHY_RSSI_SEL_W1 0x0
#define NPHY_RSSI_SEL_W2 0x1
#define NPHY_RSSI_SEL_NB 0x2
#define NPHY_RSSI_SEL_IQ 0x3
#define NPHY_RSSI_SEL_TSSI_2G 0x4
#define NPHY_RSSI_SEL_TSSI_5G 0x5
#define NPHY_RSSI_SEL_TBD 0x6
#define NPHY_RAIL_I 0x0
#define NPHY_RAIL_Q 0x1
#define NPHY_FORCESIG_DECODEGATEDCLKS 0x8
#define NPHY_REV7_RfctrlOverride_cmd_rxrf_pu 0x0
#define NPHY_REV7_RfctrlOverride_cmd_rx_pu 0x1
#define NPHY_REV7_RfctrlOverride_cmd_tx_pu 0x2
#define NPHY_REV7_RfctrlOverride_cmd_rxgain 0x3
#define NPHY_REV7_RfctrlOverride_cmd_txgain 0x4
#define NPHY_REV7_RXGAINCODE_RFMXGAIN_MASK 0x000ff
#define NPHY_REV7_RXGAINCODE_LPFGAIN_MASK 0x0ff00
#define NPHY_REV7_RXGAINCODE_DVGAGAIN_MASK 0xf0000
#define NPHY_REV7_TXGAINCODE_TGAIN_MASK 0x7fff
#define NPHY_REV7_TXGAINCODE_LPFGAIN_MASK 0x8000
#define NPHY_REV7_TXGAINCODE_BIQ0GAIN_SHIFT 14
#define NPHY_REV7_RFCTRLOVERRIDE_ID0 0x0
#define NPHY_REV7_RFCTRLOVERRIDE_ID1 0x1
#define NPHY_REV7_RFCTRLOVERRIDE_ID2 0x2
#define NPHY_IqestIqAccLo(core) ((core == 0) ? 0x12c : 0x134)
#define NPHY_IqestIqAccHi(core) ((core == 0) ? 0x12d : 0x135)
#define NPHY_IqestipwrAccLo(core) ((core == 0) ? 0x12e : 0x136)
#define NPHY_IqestipwrAccHi(core) ((core == 0) ? 0x12f : 0x137)
#define NPHY_IqestqpwrAccLo(core) ((core == 0) ? 0x130 : 0x138)
#define NPHY_IqestqpwrAccHi(core) ((core == 0) ? 0x131 : 0x139)

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drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c Normal file
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
typedef phytbl_info_t dot11lcnphytbl_info_t;
extern CONST dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev0[];
extern CONST uint32 dot11lcnphytbl_rx_gain_info_sz_rev0;
extern CONST dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313;
extern CONST dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa;
extern CONST dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa_combo;
extern CONST dot11lcnphytbl_info_t dot11lcnphytbl_info_rev0[];
extern CONST uint32 dot11lcnphytbl_info_sz_rev0;
extern CONST dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_2G_rev2[];
extern CONST uint32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz;
extern CONST dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_5G_rev2[];
extern CONST uint32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz;
extern CONST dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[];
extern CONST dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[];
typedef struct {
uchar gm;
uchar pga;
uchar pad;
uchar dac;
uchar bb_mult;
} lcnphy_tx_gain_tbl_entry;
extern CONST lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_gaintable_rev0[];
extern CONST lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_extPA_gaintable_rev0[];
extern CONST lcnphy_tx_gain_tbl_entry dot11lcnphy_5GHz_gaintable_rev0[];

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define ANT_SWCTRL_TBL_REV3_IDX (0)
typedef phytbl_info_t mimophytbl_info_t;
extern CONST mimophytbl_info_t mimophytbl_info_rev0[],
mimophytbl_info_rev0_volatile[];
extern CONST uint32 mimophytbl_info_sz_rev0, mimophytbl_info_sz_rev0_volatile;
extern CONST mimophytbl_info_t mimophytbl_info_rev3[],
mimophytbl_info_rev3_volatile[], mimophytbl_info_rev3_volatile1[],
mimophytbl_info_rev3_volatile2[], mimophytbl_info_rev3_volatile3[];
extern CONST uint32 mimophytbl_info_sz_rev3, mimophytbl_info_sz_rev3_volatile,
mimophytbl_info_sz_rev3_volatile1, mimophytbl_info_sz_rev3_volatile2,
mimophytbl_info_sz_rev3_volatile3;
extern CONST uint32 noise_var_tbl_rev3[];
extern CONST mimophytbl_info_t mimophytbl_info_rev7[];
extern CONST uint32 mimophytbl_info_sz_rev7;
extern CONST uint32 noise_var_tbl_rev7[];
extern CONST mimophytbl_info_t mimophytbl_info_rev16[];
extern CONST uint32 mimophytbl_info_sz_rev16;

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
enum {
D11UCODE_NAMETAG_START = 0,
D11LCN0BSINITVALS24,
D11LCN0INITVALS24,
D11LCN1BSINITVALS24,
D11LCN1INITVALS24,
D11LCN2BSINITVALS24,
D11LCN2INITVALS24,
D11N0ABSINITVALS16,
D11N0BSINITVALS16,
D11N0INITVALS16,
D11UCODE_OVERSIGHT16_MIMO,
D11UCODE_OVERSIGHT16_MIMOSZ,
D11UCODE_OVERSIGHT24_LCN,
D11UCODE_OVERSIGHT24_LCNSZ,
D11UCODE_OVERSIGHT_BOMMAJOR,
D11UCODE_OVERSIGHT_BOMMINOR
};
#define UCODE_LOADER_API_VER 0

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wl_dbg_h_
#define _wl_dbg_h_
/* wl_msg_level is a bit vector with defs in wlioctl.h */
extern uint32 wl_msg_level;
#define WL_PRINT(args) printf args
#define WL_NONE(args)
#ifdef BCMDBG
#define WL_ERROR(args) do {if ((wl_msg_level & WL_ERROR_VAL)) WL_PRINT(args);} while (0)
#define WL_TRACE(args) do {if (wl_msg_level & WL_TRACE_VAL) WL_PRINT(args);} while (0)
#define WL_AMPDU(args) do {if (wl_msg_level & WL_AMPDU_VAL) WL_PRINT(args);} while (0)
#define WL_FFPLD(args) do {if (wl_msg_level & WL_FFPLD_VAL) WL_PRINT(args);} while (0)
#define WL_ERROR_ON() (wl_msg_level & WL_ERROR_VAL)
/* Extra message control for AMPDU debugging */
#define WL_AMPDU_UPDN_VAL 0x00000001 /* Config up/down related */
#define WL_AMPDU_ERR_VAL 0x00000002 /* Calls to beaocn update */
#define WL_AMPDU_TX_VAL 0x00000004 /* Transmit data path */
#define WL_AMPDU_RX_VAL 0x00000008 /* Receive data path */
#define WL_AMPDU_CTL_VAL 0x00000010 /* TSF-related items */
#define WL_AMPDU_HW_VAL 0x00000020 /* AMPDU_HW */
#define WL_AMPDU_HWTXS_VAL 0x00000040 /* AMPDU_HWTXS */
#define WL_AMPDU_HWDBG_VAL 0x00000080 /* AMPDU_DBG */
extern uint32 wl_ampdu_dbg;
#define WL_AMPDU_UPDN(args) do {if (wl_ampdu_dbg & WL_AMPDU_UPDN_VAL) {WL_AMPDU(args);}} while (0)
#define WL_AMPDU_RX(args) do {if (wl_ampdu_dbg & WL_AMPDU_RX_VAL) {WL_AMPDU(args);}} while (0)
#define WL_AMPDU_ERR(args) do {if (wl_ampdu_dbg & WL_AMPDU_ERR_VAL) {WL_AMPDU(args);}} while (0)
#define WL_AMPDU_TX(args) do {if (wl_ampdu_dbg & WL_AMPDU_TX_VAL) {WL_AMPDU(args);}} while (0)
#define WL_AMPDU_CTL(args) do {if (wl_ampdu_dbg & WL_AMPDU_CTL_VAL) {WL_AMPDU(args);}} while (0)
#define WL_AMPDU_HW(args) do {if (wl_ampdu_dbg & WL_AMPDU_HW_VAL) {WL_AMPDU(args);}} while (0)
#define WL_AMPDU_HWTXS(args) do {if (wl_ampdu_dbg & WL_AMPDU_HWTXS_VAL) {WL_AMPDU(args);}} while (0)
#define WL_AMPDU_HWDBG(args) do {if (wl_ampdu_dbg & WL_AMPDU_HWDBG_VAL) {WL_AMPDU(args);}} while (0)
#define WL_AMPDU_ERR_ON() (wl_ampdu_dbg & WL_AMPDU_ERR_VAL)
#define WL_AMPDU_HW_ON() (wl_ampdu_dbg & WL_AMPDU_HW_VAL)
#define WL_AMPDU_HWTXS_ON() (wl_ampdu_dbg & WL_AMPDU_HWTXS_VAL)
#else /* BCMDBG */
#define WL_ERROR(args)
#define WL_TRACE(args)
#define WL_AMPDU(args)
#define WL_FFPLD(args)
#define WL_ERROR_ON() 0
#define WL_AMPDU_UPDN(args)
#define WL_AMPDU_RX(args)
#define WL_AMPDU_ERR(args)
#define WL_AMPDU_TX(args)
#define WL_AMPDU_CTL(args)
#define WL_AMPDU_HW(args)
#define WL_AMPDU_HWTXS(args)
#define WL_AMPDU_HWDBG(args)
#define WL_AMPDU_ERR_ON() 0
#define WL_AMPDU_HW_ON() 0
#define WL_AMPDU_HWTXS_ON() 0
#endif /* BCMDBG */
#endif /* _wl_dbg_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wl_export_h_
#define _wl_export_h_
/* misc callbacks */
struct wl_info;
struct wl_if;
struct wlc_if;
extern void wl_init(struct wl_info *wl);
extern uint wl_reset(struct wl_info *wl);
extern void wl_intrson(struct wl_info *wl);
extern uint32 wl_intrsoff(struct wl_info *wl);
extern void wl_intrsrestore(struct wl_info *wl, uint32 macintmask);
extern void wl_event(struct wl_info *wl, char *ifname, wlc_event_t * e);
extern void wl_event_sendup(struct wl_info *wl, const wlc_event_t * e,
uint8 * data, uint32 len);
extern int wl_up(struct wl_info *wl);
extern void wl_down(struct wl_info *wl);
extern void wl_txflowcontrol(struct wl_info *wl, struct wl_if *wlif, bool state,
int prio);
extern bool wl_alloc_dma_resources(struct wl_info *wl, uint dmaddrwidth);
/* timer functions */
struct wl_timer;
extern struct wl_timer *wl_init_timer(struct wl_info *wl,
void (*fn) (void *arg), void *arg,
const char *name);
extern void wl_free_timer(struct wl_info *wl, struct wl_timer *timer);
extern void wl_add_timer(struct wl_info *wl, struct wl_timer *timer, uint ms,
int periodic);
extern bool wl_del_timer(struct wl_info *wl, struct wl_timer *timer);
extern uint wl_buf_to_pktcopy(osl_t * osh, void *p, uchar * buf, int len,
uint offset);
extern void *wl_get_pktbuffer(osl_t * osh, int len);
extern int wl_set_pktlen(osl_t * osh, void *p, int len);
#define wl_sort_bsslist(a, b) FALSE
extern int wl_tkip_miccheck(struct wl_info *wl, void *p, int hdr_len,
bool group_key, int id);
extern int wl_tkip_micadd(struct wl_info *wl, void *p, int hdr_len);
extern int wl_tkip_encrypt(struct wl_info *wl, void *p, int hdr_len);
extern int wl_tkip_decrypt(struct wl_info *wl, void *p, int hdr_len,
bool group_key);
extern void wl_tkip_printstats(struct wl_info *wl, bool group_key);
extern int wl_tkip_keyset(struct wl_info *wl, wsec_key_t * key);
#endif /* _wl_export_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wl_mac80211_h_
#define _wl_mac80211_h_
#include <wlc_types.h>
/* BMAC Note: High-only driver is no longer working in softirq context as it needs to block and
* sleep so perimeter lock has to be a semaphore instead of spinlock. This requires timers to be
* submitted to workqueue instead of being on kernel timer
*/
typedef struct wl_timer {
struct timer_list timer;
struct wl_info *wl;
void (*fn) (void *);
void *arg; /* argument to fn */
uint ms;
bool periodic;
bool set;
struct wl_timer *next;
#ifdef BCMDBG
char *name; /* Description of the timer */
#endif
} wl_timer_t;
/* contortion to call functions at safe time */
/* In 2.6.20 kernels work functions get passed a pointer to the struct work, so things
* will continue to work as long as the work structure is the first component of the task structure.
*/
typedef struct wl_task {
struct work_struct work;
void *context;
} wl_task_t;
struct wl_if {
uint subunit; /* WDS/BSS unit */
struct pci_dev *pci_dev;
};
#define WL_MAX_FW 4
struct wl_firmware {
uint32 fw_cnt;
const struct firmware *fw_bin[WL_MAX_FW];
const struct firmware *fw_hdr[WL_MAX_FW];
uint32 hdr_num_entries[WL_MAX_FW];
};
struct wl_info {
wlc_pub_t *pub; /* pointer to public wlc state */
void *wlc; /* pointer to private common os-independent data */
osl_t *osh; /* pointer to os handler */
uint32 magic;
int irq;
#ifdef WLC_HIGH_ONLY
struct semaphore sem; /* use semaphore to allow sleep */
#else
spinlock_t lock; /* per-device perimeter lock */
spinlock_t isr_lock; /* per-device ISR synchronization lock */
#endif
uint bcm_bustype; /* bus type */
bool piomode; /* set from insmod argument */
void *regsva; /* opaque chip registers virtual address */
atomic_t callbacks; /* # outstanding callback functions */
struct wl_timer *timers; /* timer cleanup queue */
struct tasklet_struct tasklet; /* dpc tasklet */
#ifdef BCMSDIO
bcmsdh_info_t *sdh; /* pointer to sdio bus handler */
ulong flags; /* current irq flags */
#endif /* BCMSDIO */
bool resched; /* dpc needs to be and is rescheduled */
#ifdef LINUXSTA_PS
uint32 pci_psstate[16]; /* pci ps-state save/restore */
#endif
/* RPC, handle, lock, txq, workitem */
#ifdef WLC_HIGH_ONLY
rpc_info_t *rpc; /* RPC handle */
rpc_tp_info_t *rpc_th; /* RPC transport handle */
wlc_rpc_ctx_t rpc_dispatch_ctx;
bool rpcq_dispatched; /* Avoid scheduling multiple tasks */
spinlock_t rpcq_lock; /* Lock for the queue */
rpc_buf_t *rpcq_head; /* RPC Q */
rpc_buf_t *rpcq_tail; /* Points to the last buf */
bool txq_dispatched; /* Avoid scheduling multiple tasks */
spinlock_t txq_lock; /* Lock for the queue */
struct sk_buff *txq_head; /* TX Q */
struct sk_buff *txq_tail; /* Points to the last buf */
wl_task_t txq_task; /* work queue for wl_start() */
#endif /* WLC_HIGH_ONLY */
uint stats_id; /* the current set of stats */
/* ping-pong stats counters updated by Linux watchdog */
struct net_device_stats stats_watchdog[2];
struct proc_dir_entry *proc_entry;
char *ioctlbuf;
unsigned int ioctlbuf_sz;
wl_ioctl_t ioc;
int proc_state;
bool ioctl_in_progress;
struct wl_firmware fw;
};
#define WL_PROC_IDLE (0)
#define WL_PROC_HAVE_IOC (1)
#define WL_PROC_HAVE_BUF (2)
#ifndef WLC_HIGH_ONLY
#define WL_LOCK(wl) spin_lock_bh(&(wl)->lock)
#define WL_UNLOCK(wl) spin_unlock_bh(&(wl)->lock)
/* locking from inside wl_isr */
#define WL_ISRLOCK(wl, flags) do {spin_lock(&(wl)->isr_lock); (void)(flags);} while (0)
#define WL_ISRUNLOCK(wl, flags) do {spin_unlock(&(wl)->isr_lock); (void)(flags);} while (0)
/* locking under WL_LOCK() to synchronize with wl_isr */
#define INT_LOCK(wl, flags) spin_lock_irqsave(&(wl)->isr_lock, flags)
#define INT_UNLOCK(wl, flags) spin_unlock_irqrestore(&(wl)->isr_lock, flags)
#else /* BCMSDIO */
#define WL_LOCK(wl) down(&(wl)->sem)
#define WL_UNLOCK(wl) up(&(wl)->sem)
#define WL_ISRLOCK(wl)
#define WL_ISRUNLOCK(wl)
#endif /* WLC_HIGH_ONLY */
/* handle forward declaration */
typedef struct wl_info wl_info_t;
#ifndef PCI_D0
#define PCI_D0 0
#endif
#ifndef PCI_D3hot
#define PCI_D3hot 3
#endif
/* exported functions */
extern irqreturn_t wl_isr(int irq, void *dev_id);
extern int __devinit wl_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *ent);
extern void wl_free(wl_info_t * wl);
extern int wl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
extern int wl_ucode_data_init(wl_info_t * wl);
extern void wl_ucode_data_free(void);
#ifdef WLC_LOW
extern void wl_ucode_free_buf(void *);
extern int wl_ucode_init_buf(wl_info_t * wl, void **pbuf, uint32 idx);
extern int wl_ucode_init_uint(wl_info_t * wl, uint32 * data, uint32 idx);
#endif /* WLC_LOW */
#endif /* _wl_mac80211_h_ */

38
drivers/staging/brcm80211/sys/wl_ucode.h Normal file
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <typedefs.h>
typedef struct d11init {
uint16 addr;
uint16 size;
uint32 value;
} d11init_t;
extern d11init_t *d11lcn0bsinitvals24;
extern d11init_t *d11lcn0initvals24;
extern d11init_t *d11lcn1bsinitvals24;
extern d11init_t *d11lcn1initvals24;
extern d11init_t *d11lcn2bsinitvals24;
extern d11init_t *d11lcn2initvals24;
extern d11init_t *d11n0absinitvals16;
extern d11init_t *d11n0bsinitvals16;
extern d11init_t *d11n0initvals16;
extern uint32 *bcm43xx_16_mimo;
extern uint32 bcm43xx_16_mimosz;
extern uint32 *bcm43xx_24_lcn;
extern uint32 bcm43xx_24_lcnsz;
extern uint32 *bcm43xx_bommajor;
extern uint32 *bcm43xx_bomminor;

89
drivers/staging/brcm80211/sys/wl_ucode_loader.c Normal file
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
typedef struct wl_info wl_info_t;
#include <typedefs.h>
#include <d11ucode_ext.h>
#include <wl_ucode.h>
extern int wl_ucode_init_buf(wl_info_t * wl, void **pbuf, unsigned int idx);
extern int wl_ucode_init_uint(wl_info_t * wl, unsigned *data, unsigned int idx);
extern int wl_ucode_data_init(wl_info_t * wl);
extern void wl_ucode_data_free(void);
extern void wl_ucode_free_buf(void *);
d11init_t *d11lcn0bsinitvals24;
d11init_t *d11lcn0initvals24;
d11init_t *d11lcn1bsinitvals24;
d11init_t *d11lcn1initvals24;
d11init_t *d11lcn2bsinitvals24;
d11init_t *d11lcn2initvals24;
d11init_t *d11n0absinitvals16;
d11init_t *d11n0bsinitvals16;
d11init_t *d11n0initvals16;
uint32 *bcm43xx_16_mimo;
uint32 bcm43xx_16_mimosz;
uint32 *bcm43xx_24_lcn;
uint32 bcm43xx_24_lcnsz;
uint32 *bcm43xx_bommajor;
uint32 *bcm43xx_bomminor;
int wl_ucode_data_init(wl_info_t * wl)
{
wl_ucode_init_buf(wl, (void **)&d11lcn0bsinitvals24,
D11LCN0BSINITVALS24);
wl_ucode_init_buf(wl, (void **)&d11lcn0initvals24, D11LCN0INITVALS24);
wl_ucode_init_buf(wl, (void **)&d11lcn1bsinitvals24,
D11LCN1BSINITVALS24);
wl_ucode_init_buf(wl, (void **)&d11lcn1initvals24, D11LCN1INITVALS24);
wl_ucode_init_buf(wl, (void **)&d11lcn2bsinitvals24,
D11LCN2BSINITVALS24);
wl_ucode_init_buf(wl, (void **)&d11lcn2initvals24, D11LCN2INITVALS24);
wl_ucode_init_buf(wl, (void **)&d11n0absinitvals16, D11N0ABSINITVALS16);
wl_ucode_init_buf(wl, (void **)&d11n0bsinitvals16, D11N0BSINITVALS16);
wl_ucode_init_buf(wl, (void **)&d11n0initvals16, D11N0INITVALS16);
wl_ucode_init_buf(wl, (void **)&bcm43xx_16_mimo,
D11UCODE_OVERSIGHT16_MIMO);
wl_ucode_init_uint(wl, &bcm43xx_16_mimosz, D11UCODE_OVERSIGHT16_MIMOSZ);
wl_ucode_init_buf(wl, (void **)&bcm43xx_24_lcn,
D11UCODE_OVERSIGHT24_LCN);
wl_ucode_init_uint(wl, &bcm43xx_24_lcnsz, D11UCODE_OVERSIGHT24_LCNSZ);
wl_ucode_init_buf(wl, (void **)&bcm43xx_bommajor,
D11UCODE_OVERSIGHT_BOMMAJOR);
wl_ucode_init_buf(wl, (void **)&bcm43xx_bomminor,
D11UCODE_OVERSIGHT_BOMMINOR);
return 0;
}
void wl_ucode_data_free(void)
{
wl_ucode_free_buf((void *)d11lcn0bsinitvals24);
wl_ucode_free_buf((void *)d11lcn0initvals24);
wl_ucode_free_buf((void *)d11lcn1bsinitvals24);
wl_ucode_free_buf((void *)d11lcn1initvals24);
wl_ucode_free_buf((void *)d11lcn2bsinitvals24);
wl_ucode_free_buf((void *)d11lcn2initvals24);
wl_ucode_free_buf((void *)d11n0absinitvals16);
wl_ucode_free_buf((void *)d11n0bsinitvals16);
wl_ucode_free_buf((void *)d11n0initvals16);
wl_ucode_free_buf((void *)bcm43xx_16_mimo);
wl_ucode_free_buf((void *)bcm43xx_24_lcn);
wl_ucode_free_buf((void *)bcm43xx_bommajor);
wl_ucode_free_buf((void *)bcm43xx_bomminor);
return;
}

383
drivers/staging/brcm80211/sys/wlc_alloc.c Normal file
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@ -0,0 +1,383 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <wlc_cfg.h>
#include <typedefs.h>
#include <bcmdefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <siutils.h>
#include <proto/802.11.h>
#include <proto/802.11e.h>
#include <proto/wpa.h>
#include <wlioctl.h>
#include <bcmwpa.h>
#include <d11.h>
#include <wlc_rate.h>
#include <wlc_pub.h>
#include <wlc_key.h>
#include <wlc_bsscfg.h>
#include <wlc_mac80211.h>
#include <wlc_alloc.h>
static wlc_pub_t *wlc_pub_malloc(osl_t * osh, uint unit, uint * err,
uint devid);
static void wlc_pub_mfree(osl_t * osh, wlc_pub_t * pub);
static void wlc_tunables_init(wlc_tunables_t * tunables, uint devid);
void *wlc_calloc(osl_t * osh, uint unit, uint size)
{
void *item;
if ((item = MALLOC(osh, size)) == NULL)
WL_ERROR(("wl%d: %s: out of memory, malloced %d bytes\n",
unit, __func__, MALLOCED(osh)));
else
bzero((char *)item, size);
return item;
}
void BCMATTACHFN(wlc_tunables_init) (wlc_tunables_t * tunables, uint devid) {
tunables->ntxd = NTXD;
tunables->nrxd = NRXD;
tunables->rxbufsz = RXBUFSZ;
tunables->nrxbufpost = NRXBUFPOST;
tunables->maxscb = MAXSCB;
tunables->ampdunummpdu = AMPDU_NUM_MPDU;
tunables->maxpktcb = MAXPKTCB;
tunables->maxucodebss = WLC_MAX_UCODE_BSS;
tunables->maxucodebss4 = WLC_MAX_UCODE_BSS4;
tunables->maxbss = MAXBSS;
tunables->datahiwat = WLC_DATAHIWAT;
tunables->ampdudatahiwat = WLC_AMPDUDATAHIWAT;
tunables->rxbnd = RXBND;
tunables->txsbnd = TXSBND;
#if defined(WLC_HIGH_ONLY) && defined(NTXD_USB_4319)
if (devid == BCM4319_CHIP_ID) {
tunables->ntxd = NTXD_USB_4319;
}
#endif /* WLC_HIGH_ONLY */
}
static wlc_pub_t *BCMATTACHFN(wlc_pub_malloc) (osl_t * osh, uint unit,
uint * err, uint devid) {
wlc_pub_t *pub;
if ((pub =
(wlc_pub_t *) wlc_calloc(osh, unit, sizeof(wlc_pub_t))) == NULL) {
*err = 1001;
goto fail;
}
if ((pub->tunables = (wlc_tunables_t *)
wlc_calloc(osh, unit, sizeof(wlc_tunables_t))) == NULL) {
*err = 1028;
goto fail;
}
/* need to init the tunables now */
wlc_tunables_init(pub->tunables, devid);
if ((pub->multicast = (struct ether_addr *)
wlc_calloc(osh, unit,
(sizeof(struct ether_addr) * MAXMULTILIST))) == NULL) {
*err = 1003;
goto fail;
}
return pub;
fail:
wlc_pub_mfree(osh, pub);
return NULL;
}
static void BCMATTACHFN(wlc_pub_mfree) (osl_t * osh, wlc_pub_t * pub) {
if (pub == NULL)
return;
if (pub->multicast)
MFREE(osh, pub->multicast,
(sizeof(struct ether_addr) * MAXMULTILIST));
if (pub->tunables) {
MFREE(osh, pub->tunables, sizeof(wlc_tunables_t));
pub->tunables = NULL;
}
MFREE(osh, pub, sizeof(wlc_pub_t));
}
wlc_bsscfg_t *wlc_bsscfg_malloc(osl_t * osh, uint unit)
{
wlc_bsscfg_t *cfg;
if ((cfg =
(wlc_bsscfg_t *) wlc_calloc(osh, unit,
sizeof(wlc_bsscfg_t))) == NULL)
goto fail;
if ((cfg->current_bss = (wlc_bss_info_t *)
wlc_calloc(osh, unit, sizeof(wlc_bss_info_t))) == NULL)
goto fail;
return cfg;
fail:
wlc_bsscfg_mfree(osh, cfg);
return NULL;
}
void wlc_bsscfg_mfree(osl_t * osh, wlc_bsscfg_t * cfg)
{
if (cfg == NULL)
return;
if (cfg->maclist) {
MFREE(osh, cfg->maclist,
(int)(OFFSETOF(struct maclist, ea) +
cfg->nmac * ETHER_ADDR_LEN));
cfg->maclist = NULL;
}
if (cfg->current_bss != NULL) {
wlc_bss_info_t *current_bss = cfg->current_bss;
if (current_bss->bcn_prb != NULL)
MFREE(osh, current_bss->bcn_prb,
current_bss->bcn_prb_len);
MFREE(osh, current_bss, sizeof(wlc_bss_info_t));
cfg->current_bss = NULL;
}
MFREE(osh, cfg, sizeof(wlc_bsscfg_t));
}
void wlc_bsscfg_ID_assign(wlc_info_t * wlc, wlc_bsscfg_t * bsscfg)
{
bsscfg->ID = wlc->next_bsscfg_ID;
wlc->next_bsscfg_ID++;
}
/*
* The common driver entry routine. Error codes should be unique
*/
wlc_info_t *BCMATTACHFN(wlc_attach_malloc) (osl_t * osh, uint unit, uint * err,
uint devid) {
wlc_info_t *wlc;
if ((wlc =
(wlc_info_t *) wlc_calloc(osh, unit,
sizeof(wlc_info_t))) == NULL) {
*err = 1002;
goto fail;
}
wlc->hwrxoff = WL_HWRXOFF;
/* allocate wlc_pub_t state structure */
if ((wlc->pub = wlc_pub_malloc(osh, unit, err, devid)) == NULL) {
*err = 1003;
goto fail;
}
wlc->pub->wlc = wlc;
/* allocate wlc_hw_info_t state structure */
if ((wlc->hw = (wlc_hw_info_t *)
wlc_calloc(osh, unit, sizeof(wlc_hw_info_t))) == NULL) {
*err = 1005;
goto fail;
}
wlc->hw->wlc = wlc;
#ifdef WLC_LOW
if ((wlc->hw->bandstate[0] = (wlc_hwband_t *)
wlc_calloc(osh, unit, (sizeof(wlc_hwband_t) * MAXBANDS))) == NULL) {
*err = 1006;
goto fail;
} else {
int i;
for (i = 1; i < MAXBANDS; i++) {
wlc->hw->bandstate[i] = (wlc_hwband_t *)
((uintptr) wlc->hw->bandstate[0] +
(sizeof(wlc_hwband_t) * i));
}
}
#endif /* WLC_LOW */
if ((wlc->modulecb = (modulecb_t *)
wlc_calloc(osh, unit,
sizeof(modulecb_t) * WLC_MAXMODULES)) == NULL) {
*err = 1009;
goto fail;
}
if ((wlc->default_bss = (wlc_bss_info_t *)
wlc_calloc(osh, unit, sizeof(wlc_bss_info_t))) == NULL) {
*err = 1010;
goto fail;
}
if ((wlc->cfg = wlc_bsscfg_malloc(osh, unit)) == NULL) {
*err = 1011;
goto fail;
}
wlc_bsscfg_ID_assign(wlc, wlc->cfg);
if ((wlc->pkt_callback = (pkt_cb_t *)
wlc_calloc(osh, unit,
(sizeof(pkt_cb_t) *
(wlc->pub->tunables->maxpktcb + 1)))) == NULL) {
*err = 1013;
goto fail;
}
if ((wlc->wsec_def_keys[0] = (wsec_key_t *)
wlc_calloc(osh, unit,
(sizeof(wsec_key_t) * WLC_DEFAULT_KEYS))) == NULL) {
*err = 1015;
goto fail;
} else {
int i;
for (i = 1; i < WLC_DEFAULT_KEYS; i++) {
wlc->wsec_def_keys[i] = (wsec_key_t *)
((uintptr) wlc->wsec_def_keys[0] +
(sizeof(wsec_key_t) * i));
}
}
if ((wlc->protection = (wlc_protection_t *)
wlc_calloc(osh, unit, sizeof(wlc_protection_t))) == NULL) {
*err = 1016;
goto fail;
}
if ((wlc->stf = (wlc_stf_t *)
wlc_calloc(osh, unit, sizeof(wlc_stf_t))) == NULL) {
*err = 1017;
goto fail;
}
if ((wlc->bandstate[0] = (wlcband_t *)
wlc_calloc(osh, unit, (sizeof(wlcband_t) * MAXBANDS))) == NULL) {
*err = 1025;
goto fail;
} else {
int i;
for (i = 1; i < MAXBANDS; i++) {
wlc->bandstate[i] =
(wlcband_t *) ((uintptr) wlc->bandstate[0] +
(sizeof(wlcband_t) * i));
}
}
if ((wlc->corestate = (wlccore_t *)
wlc_calloc(osh, unit, sizeof(wlccore_t))) == NULL) {
*err = 1026;
goto fail;
}
if ((wlc->corestate->macstat_snapshot = (macstat_t *)
wlc_calloc(osh, unit, sizeof(macstat_t))) == NULL) {
*err = 1027;
goto fail;
}
return wlc;
fail:
wlc_detach_mfree(wlc, osh);
return NULL;
}
void BCMATTACHFN(wlc_detach_mfree) (wlc_info_t * wlc, osl_t * osh) {
if (wlc == NULL)
return;
if (wlc->modulecb) {
MFREE(osh, wlc->modulecb, sizeof(modulecb_t) * WLC_MAXMODULES);
wlc->modulecb = NULL;
}
if (wlc->default_bss) {
MFREE(osh, wlc->default_bss, sizeof(wlc_bss_info_t));
wlc->default_bss = NULL;
}
if (wlc->cfg) {
wlc_bsscfg_mfree(osh, wlc->cfg);
wlc->cfg = NULL;
}
if (wlc->pkt_callback && wlc->pub && wlc->pub->tunables) {
MFREE(osh,
wlc->pkt_callback,
sizeof(pkt_cb_t) * (wlc->pub->tunables->maxpktcb + 1));
wlc->pkt_callback = NULL;
}
if (wlc->wsec_def_keys[0])
MFREE(osh, wlc->wsec_def_keys[0],
(sizeof(wsec_key_t) * WLC_DEFAULT_KEYS));
if (wlc->protection) {
MFREE(osh, wlc->protection, sizeof(wlc_protection_t));
wlc->protection = NULL;
}
if (wlc->stf) {
MFREE(osh, wlc->stf, sizeof(wlc_stf_t));
wlc->stf = NULL;
}
if (wlc->bandstate[0])
MFREE(osh, wlc->bandstate[0], (sizeof(wlcband_t) * MAXBANDS));
if (wlc->corestate) {
if (wlc->corestate->macstat_snapshot) {
MFREE(osh, wlc->corestate->macstat_snapshot,
sizeof(macstat_t));
wlc->corestate->macstat_snapshot = NULL;
}
MFREE(osh, wlc->corestate, sizeof(wlccore_t));
wlc->corestate = NULL;
}
if (wlc->pub) {
/* free pub struct */
wlc_pub_mfree(osh, wlc->pub);
wlc->pub = NULL;
}
if (wlc->hw) {
#ifdef WLC_LOW
if (wlc->hw->bandstate[0]) {
MFREE(osh, wlc->hw->bandstate[0],
(sizeof(wlc_hwband_t) * MAXBANDS));
wlc->hw->bandstate[0] = NULL;
}
#endif
/* free hw struct */
MFREE(osh, wlc->hw, sizeof(wlc_hw_info_t));
wlc->hw = NULL;
}
/* free the wlc */
MFREE(osh, wlc, sizeof(wlc_info_t));
wlc = NULL;
}

25
drivers/staging/brcm80211/sys/wlc_alloc.h Normal file
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@ -0,0 +1,25 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
extern void *wlc_calloc(osl_t * osh, uint unit, uint size);
extern wlc_info_t *wlc_attach_malloc(osl_t * osh, uint unit, uint * err,
uint devid);
extern void wlc_detach_mfree(wlc_info_t * wlc, osl_t * osh);
struct wlc_bsscfg;
extern struct wlc_bsscfg *wlc_bsscfg_malloc(osl_t * osh, uint unit);
extern void wlc_bsscfg_mfree(osl_t * osh, struct wlc_bsscfg *cfg);

1417
drivers/staging/brcm80211/sys/wlc_ampdu.c Normal file
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File diff suppressed because it is too large Load Diff

40
drivers/staging/brcm80211/sys/wlc_ampdu.h Normal file
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@ -0,0 +1,40 @@
/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_ampdu_h_
#define _wlc_ampdu_h_
extern ampdu_info_t *wlc_ampdu_attach(wlc_info_t * wlc);
extern void wlc_ampdu_detach(ampdu_info_t * ampdu);
extern bool wlc_ampdu_cap(ampdu_info_t * ampdu);
extern int wlc_ampdu_set(ampdu_info_t * ampdu, bool on);
extern int wlc_sendampdu(ampdu_info_t * ampdu, wlc_txq_info_t * qi, void **aggp,
int prec);
extern void wlc_ampdu_dotxstatus(ampdu_info_t * ampdu, struct scb *scb, void *p,
tx_status_t * txs);
extern void wlc_ampdu_reset(ampdu_info_t * ampdu);
extern void wlc_ampdu_macaddr_upd(wlc_info_t * wlc);
extern void wlc_ampdu_shm_upd(ampdu_info_t * ampdu);
extern uint8 wlc_ampdu_null_delim_cnt(ampdu_info_t * ampdu, struct scb *scb,
ratespec_t rspec, int phylen);
extern void scb_ampdu_cleanup(ampdu_info_t * ampdu, struct scb *scb);
#ifdef WLC_HIGH_ONLY
extern void wlc_ampdu_txstatus_complete(ampdu_info_t * ampdu, uint32 s1,
uint32 s2);
#endif
#endif /* _wlc_ampdu_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <wlc_cfg.h>
#ifdef WLANTSEL
#include <typedefs.h>
#include <qmath.h>
#include <bcmdefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <siutils.h>
#include <bcmendian.h>
#include <wlioctl.h>
#include <wlc_phy_radio.h>
#include <bitfuncs.h>
#include <proto/802.11.h>
#include <d11.h>
#include <wlc_rate.h>
#include <wlc_key.h>
#include <wlc_pub.h>
#include <wlc_bsscfg.h>
#include <wl_dbg.h>
#include <wlc_mac80211.h>
#include <wlc_bmac.h>
#include <wlc_phy_hal.h>
#include <wl_export.h>
#include <wlc_antsel.h>
#include <wlc_phy_shim.h>
/* useful macros */
#define WLC_ANTSEL_11N_0(ant) ((((ant) & ANT_SELCFG_MASK) >> 4) & 0xf)
#define WLC_ANTSEL_11N_1(ant) (((ant) & ANT_SELCFG_MASK) & 0xf)
#define WLC_ANTIDX_11N(ant) (((WLC_ANTSEL_11N_0(ant)) << 2) + (WLC_ANTSEL_11N_1(ant)))
#define WLC_ANT_ISAUTO_11N(ant) (((ant) & ANT_SELCFG_AUTO) == ANT_SELCFG_AUTO)
#define WLC_ANTSEL_11N(ant) ((ant) & ANT_SELCFG_MASK)
/* antenna switch */
/* defines for no boardlevel antenna diversity */
#define ANT_SELCFG_DEF_2x2 0x01 /* default antenna configuration */
/* 2x3 antdiv defines and tables for GPIO communication */
#define ANT_SELCFG_NUM_2x3 3
#define ANT_SELCFG_DEF_2x3 0x01 /* default antenna configuration */
/* 2x4 antdiv rev4 defines and tables for GPIO communication */
#define ANT_SELCFG_NUM_2x4 4
#define ANT_SELCFG_DEF_2x4 0x02 /* default antenna configuration */
/* static functions */
static int wlc_antsel_cfgupd(antsel_info_t * asi, wlc_antselcfg_t * antsel);
static uint8 wlc_antsel_id2antcfg(antsel_info_t * asi, uint8 id);
static uint16 wlc_antsel_antcfg2antsel(antsel_info_t * asi, uint8 ant_cfg);
static void wlc_antsel_init_cfg(antsel_info_t * asi, wlc_antselcfg_t * antsel,
bool auto_sel);
const uint16 mimo_2x4_div_antselpat_tbl[] = {
0, 0, 0x9, 0xa, /* ant0: 0 ant1: 2,3 */
0, 0, 0x5, 0x6, /* ant0: 1 ant1: 2,3 */
0, 0, 0, 0, /* n.a. */
0, 0, 0, 0 /* n.a. */
};
const uint8 mimo_2x4_div_antselid_tbl[16] = {
0, 0, 0, 0, 0, 2, 3, 0,
0, 0, 1, 0, 0, 0, 0, 0 /* pat to antselid */
};
const uint16 mimo_2x3_div_antselpat_tbl[] = {
16, 0, 1, 16, /* ant0: 0 ant1: 1,2 */
16, 16, 16, 16, /* n.a. */
16, 2, 16, 16, /* ant0: 2 ant1: 1 */
16, 16, 16, 16 /* n.a. */
};
const uint8 mimo_2x3_div_antselid_tbl[16] = {
0, 1, 2, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 /* pat to antselid */
};
antsel_info_t *BCMNMIATTACHFN(wlc_antsel_attach) (wlc_info_t * wlc, osl_t * osh,
wlc_pub_t * pub,
wlc_hw_info_t * wlc_hw) {
antsel_info_t *asi;
if (!(asi = (antsel_info_t *) MALLOC(osh, sizeof(antsel_info_t)))) {
WL_ERROR(("wl%d: wlc_antsel_attach: out of mem, malloced %d bytes\n", pub->unit, MALLOCED(osh)));
return NULL;
}
bzero((char *)asi, sizeof(antsel_info_t));
asi->wlc = wlc;
asi->pub = pub;
asi->antsel_type = ANTSEL_NA;
asi->antsel_avail = FALSE;
asi->antsel_antswitch = (uint8) getintvar(asi->pub->vars, "antswitch");
if ((asi->pub->sromrev >= 4) && (asi->antsel_antswitch != 0)) {
switch (asi->antsel_antswitch) {
case ANTSWITCH_TYPE_1:
case ANTSWITCH_TYPE_2:
case ANTSWITCH_TYPE_3:
/* 4321/2 board with 2x3 switch logic */
asi->antsel_type = ANTSEL_2x3;
/* Antenna selection availability */
if (((uint16) getintvar(asi->pub->vars, "aa2g") == 7) ||
((uint16) getintvar(asi->pub->vars, "aa5g") == 7)) {
asi->antsel_avail = TRUE;
} else
if (((uint16) getintvar(asi->pub->vars, "aa2g") ==
3)
|| ((uint16) getintvar(asi->pub->vars, "aa5g")
== 3)) {
asi->antsel_avail = FALSE;
} else {
asi->antsel_avail = FALSE;
WL_ERROR(("wlc_antsel_attach: 2o3 board cfg invalid\n"));
ASSERT(0);
}
break;
default:
break;
}
} else if ((asi->pub->sromrev == 4) &&
((uint16) getintvar(asi->pub->vars, "aa2g") == 7) &&
((uint16) getintvar(asi->pub->vars, "aa5g") == 0)) {
/* hack to match old 4321CB2 cards with 2of3 antenna switch */
asi->antsel_type = ANTSEL_2x3;
asi->antsel_avail = TRUE;
} else if (asi->pub->boardflags2 & BFL2_2X4_DIV) {
asi->antsel_type = ANTSEL_2x4;
asi->antsel_avail = TRUE;
}
/* Set the antenna selection type for the low driver */
wlc_bmac_antsel_type_set(wlc_hw, asi->antsel_type);
/* Init (auto/manual) antenna selection */
wlc_antsel_init_cfg(asi, &asi->antcfg_11n, TRUE);
wlc_antsel_init_cfg(asi, &asi->antcfg_cur, TRUE);
return asi;
}
void BCMATTACHFN(wlc_antsel_detach) (antsel_info_t * asi) {
if (!asi)
return;
MFREE(asi->pub->osh, asi, sizeof(antsel_info_t));
}
void wlc_antsel_init(antsel_info_t * asi)
{
if ((asi->antsel_type == ANTSEL_2x3) ||
(asi->antsel_type == ANTSEL_2x4))
wlc_antsel_cfgupd(asi, &asi->antcfg_11n);
}
/* boardlevel antenna selection: init antenna selection structure */
static void
wlc_antsel_init_cfg(antsel_info_t * asi, wlc_antselcfg_t * antsel,
bool auto_sel)
{
if (asi->antsel_type == ANTSEL_2x3) {
uint8 antcfg_def = ANT_SELCFG_DEF_2x3 |
((asi->antsel_avail && auto_sel) ? ANT_SELCFG_AUTO : 0);
antsel->ant_config[ANT_SELCFG_TX_DEF] = antcfg_def;
antsel->ant_config[ANT_SELCFG_TX_UNICAST] = antcfg_def;
antsel->ant_config[ANT_SELCFG_RX_DEF] = antcfg_def;
antsel->ant_config[ANT_SELCFG_RX_UNICAST] = antcfg_def;
antsel->num_antcfg = ANT_SELCFG_NUM_2x3;
} else if (asi->antsel_type == ANTSEL_2x4) {
antsel->ant_config[ANT_SELCFG_TX_DEF] = ANT_SELCFG_DEF_2x4;
antsel->ant_config[ANT_SELCFG_TX_UNICAST] = ANT_SELCFG_DEF_2x4;
antsel->ant_config[ANT_SELCFG_RX_DEF] = ANT_SELCFG_DEF_2x4;
antsel->ant_config[ANT_SELCFG_RX_UNICAST] = ANT_SELCFG_DEF_2x4;
antsel->num_antcfg = ANT_SELCFG_NUM_2x4;
} else { /* no antenna selection available */
antsel->ant_config[ANT_SELCFG_TX_DEF] = ANT_SELCFG_DEF_2x2;
antsel->ant_config[ANT_SELCFG_TX_UNICAST] = ANT_SELCFG_DEF_2x2;
antsel->ant_config[ANT_SELCFG_RX_DEF] = ANT_SELCFG_DEF_2x2;
antsel->ant_config[ANT_SELCFG_RX_UNICAST] = ANT_SELCFG_DEF_2x2;
antsel->num_antcfg = 0;
}
}
void BCMFASTPATH
wlc_antsel_antcfg_get(antsel_info_t * asi, bool usedef, bool sel,
uint8 antselid, uint8 fbantselid, uint8 * antcfg,
uint8 * fbantcfg)
{
uint8 ant;
/* if use default, assign it and return */
if (usedef) {
*antcfg = asi->antcfg_11n.ant_config[ANT_SELCFG_TX_DEF];
*fbantcfg = *antcfg;
return;
}
if (!sel) {
*antcfg = asi->antcfg_11n.ant_config[ANT_SELCFG_TX_UNICAST];
*fbantcfg = *antcfg;
} else {
ant = asi->antcfg_11n.ant_config[ANT_SELCFG_TX_UNICAST];
if ((ant & ANT_SELCFG_AUTO) == ANT_SELCFG_AUTO) {
*antcfg = wlc_antsel_id2antcfg(asi, antselid);
*fbantcfg = wlc_antsel_id2antcfg(asi, fbantselid);
} else {
*antcfg =
asi->antcfg_11n.ant_config[ANT_SELCFG_TX_UNICAST];
*fbantcfg = *antcfg;
}
}
return;
}
/* boardlevel antenna selection: convert mimo_antsel (ucode interface) to id */
uint8 wlc_antsel_antsel2id(antsel_info_t * asi, uint16 antsel)
{
uint8 antselid = 0;
if (asi->antsel_type == ANTSEL_2x4) {
/* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */
antselid = mimo_2x4_div_antselid_tbl[(antsel & 0xf)];
return antselid;
} else if (asi->antsel_type == ANTSEL_2x3) {
/* 2x3 antenna selection, 3 cfgs: 0-1 0-2 2-1 */
antselid = mimo_2x3_div_antselid_tbl[(antsel & 0xf)];
return antselid;
}
return antselid;
}
/* boardlevel antenna selection: convert id to ant_cfg */
static uint8 wlc_antsel_id2antcfg(antsel_info_t * asi, uint8 id)
{
uint8 antcfg = ANT_SELCFG_DEF_2x2;
if (asi->antsel_type == ANTSEL_2x4) {
/* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */
antcfg = (((id & 0x2) << 3) | ((id & 0x1) + 2));
return antcfg;
} else if (asi->antsel_type == ANTSEL_2x3) {
/* 2x3 antenna selection, 3 cfgs: 0-1 0-2 2-1 */
antcfg = (((id & 0x02) << 4) | ((id & 0x1) + 1));
return antcfg;
}
return antcfg;
}
/* boardlevel antenna selection: convert ant_cfg to mimo_antsel (ucode interface) */
static uint16 wlc_antsel_antcfg2antsel(antsel_info_t * asi, uint8 ant_cfg)
{
uint8 idx = WLC_ANTIDX_11N(WLC_ANTSEL_11N(ant_cfg));
uint16 mimo_antsel = 0;
if (asi->antsel_type == ANTSEL_2x4) {
/* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */
mimo_antsel = (mimo_2x4_div_antselpat_tbl[idx] & 0xf);
return mimo_antsel;
} else if (asi->antsel_type == ANTSEL_2x3) {
/* 2x3 antenna selection, 3 cfgs: 0-1 0-2 2-1 */
mimo_antsel = (mimo_2x3_div_antselpat_tbl[idx] & 0xf);
return mimo_antsel;
}
return mimo_antsel;
}
/* boardlevel antenna selection: ucode interface control */
static int wlc_antsel_cfgupd(antsel_info_t * asi, wlc_antselcfg_t * antsel)
{
wlc_info_t *wlc = asi->wlc;
uint8 ant_cfg;
uint16 mimo_antsel;
ASSERT(asi->antsel_type != ANTSEL_NA);
/* 1) Update TX antconfig for all frames that are not unicast data
* (aka default TX)
*/
ant_cfg = antsel->ant_config[ANT_SELCFG_TX_DEF];
mimo_antsel = wlc_antsel_antcfg2antsel(asi, ant_cfg);
wlc_write_shm(wlc, M_MIMO_ANTSEL_TXDFLT, mimo_antsel);
/* Update driver stats for currently selected default tx/rx antenna config */
asi->antcfg_cur.ant_config[ANT_SELCFG_TX_DEF] = ant_cfg;
/* 2) Update RX antconfig for all frames that are not unicast data
* (aka default RX)
*/
ant_cfg = antsel->ant_config[ANT_SELCFG_RX_DEF];
mimo_antsel = wlc_antsel_antcfg2antsel(asi, ant_cfg);
wlc_write_shm(wlc, M_MIMO_ANTSEL_RXDFLT, mimo_antsel);
/* Update driver stats for currently selected default tx/rx antenna config */
asi->antcfg_cur.ant_config[ANT_SELCFG_RX_DEF] = ant_cfg;
return 0;
}
#endif /* WLANTSEL */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_antsel_h_
#define _wlc_antsel_h_
extern antsel_info_t *wlc_antsel_attach(wlc_info_t * wlc, osl_t * osh,
wlc_pub_t * pub,
wlc_hw_info_t * wlc_hw);
extern void wlc_antsel_detach(antsel_info_t * asi);
extern void wlc_antsel_init(antsel_info_t * asi);
extern void wlc_antsel_antcfg_get(antsel_info_t * asi, bool usedef, bool sel,
uint8 id, uint8 fbid, uint8 * antcfg,
uint8 * fbantcfg);
extern uint8 wlc_antsel_antsel2id(antsel_info_t * asi, uint16 antsel);
#endif /* _wlc_antsel_h_ */

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drivers/staging/brcm80211/sys/wlc_bmac.c Normal file
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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/* XXXXX this interface is under wlc.c by design
* http://hwnbu-twiki.broadcom.com/bin/view/Mwgroup/WlBmacDesign
*
* high driver files(e.g. wlc_ampdu.c etc)
* wlc.h/wlc.c
* wlc_bmac.h/wlc_bmac.c
*
* So don't include this in files other than wlc.c, wlc_bmac* wl_rte.c(dongle port) and wl_phy.c
* create wrappers in wlc.c if needed
*/
/* Revision and other info required from BMAC driver for functioning of high ONLY driver */
typedef struct wlc_bmac_revinfo {
uint vendorid; /* PCI vendor id */
uint deviceid; /* device id of chip */
uint boardrev; /* version # of particular board */
uint corerev; /* core revision */
uint sromrev; /* srom revision */
uint chiprev; /* chip revision */
uint chip; /* chip number */
uint chippkg; /* chip package */
uint boardtype; /* board type */
uint boardvendor; /* board vendor */
uint bustype; /* SB_BUS, PCI_BUS */
uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
uint buscorerev; /* buscore rev */
uint32 issim; /* chip is in simulation or emulation */
uint nbands;
struct band_info {
uint bandunit; /* To match on both sides */
uint bandtype; /* To match on both sides */
uint radiorev;
uint phytype;
uint phyrev;
uint anarev;
uint radioid;
bool abgphy_encore;
} band[MAXBANDS];
} wlc_bmac_revinfo_t;
/* dup state between BMAC(wlc_hw_info_t) and HIGH(wlc_info_t) driver */
typedef struct wlc_bmac_state {
uint32 machwcap; /* mac hw capibility */
uint32 preamble_ovr; /* preamble override */
} wlc_bmac_state_t;
enum {
IOV_BMAC_DIAG,
IOV_BMAC_SBGPIOTIMERVAL,
IOV_BMAC_SBGPIOOUT,
IOV_BMAC_CCGPIOCTRL, /* CC GPIOCTRL REG */
IOV_BMAC_CCGPIOOUT, /* CC GPIOOUT REG */
IOV_BMAC_CCGPIOOUTEN, /* CC GPIOOUTEN REG */
IOV_BMAC_CCGPIOIN, /* CC GPIOIN REG */
IOV_BMAC_WPSGPIO, /* WPS push button GPIO pin */
IOV_BMAC_OTPDUMP,
IOV_BMAC_OTPSTAT,
IOV_BMAC_PCIEASPM, /* obfuscation clkreq/aspm control */
IOV_BMAC_PCIEADVCORRMASK, /* advanced correctable error mask */
IOV_BMAC_PCIECLKREQ, /* PCIE 1.1 clockreq enab support */
IOV_BMAC_PCIELCREG, /* PCIE LCREG */
IOV_BMAC_SBGPIOTIMERMASK,
IOV_BMAC_RFDISABLEDLY,
IOV_BMAC_PCIEREG, /* PCIE REG */
IOV_BMAC_PCICFGREG, /* PCI Config register */
IOV_BMAC_PCIESERDESREG, /* PCIE SERDES REG (dev, 0}offset) */
IOV_BMAC_PCIEGPIOOUT, /* PCIEOUT REG */
IOV_BMAC_PCIEGPIOOUTEN, /* PCIEOUTEN REG */
IOV_BMAC_PCIECLKREQENCTRL, /* clkreqenctrl REG (PCIE REV > 6.0 */
IOV_BMAC_DMALPBK,
IOV_BMAC_CCREG,
IOV_BMAC_COREREG,
IOV_BMAC_SDCIS,
IOV_BMAC_SDIO_DRIVE,
IOV_BMAC_OTPW,
IOV_BMAC_NVOTPW,
IOV_BMAC_SROM,
IOV_BMAC_SRCRC,
IOV_BMAC_CIS_SOURCE,
IOV_BMAC_CISVAR,
IOV_BMAC_OTPLOCK,
IOV_BMAC_OTP_CHIPID,
IOV_BMAC_CUSTOMVAR1,
IOV_BMAC_BOARDFLAGS,
IOV_BMAC_BOARDFLAGS2,
IOV_BMAC_WPSLED,
IOV_BMAC_NVRAM_SOURCE,
IOV_BMAC_OTP_RAW_READ,
IOV_BMAC_LAST
};
typedef enum {
BMAC_DUMP_GPIO_ID,
BMAC_DUMP_SI_ID,
BMAC_DUMP_SIREG_ID,
BMAC_DUMP_SICLK_ID,
BMAC_DUMP_CCREG_ID,
BMAC_DUMP_PCIEREG_ID,
BMAC_DUMP_PHYREG_ID,
BMAC_DUMP_PHYTBL_ID,
BMAC_DUMP_PHYTBL2_ID,
BMAC_DUMP_PHY_RADIOREG_ID,
BMAC_DUMP_LAST
} wlc_bmac_dump_id_t;
typedef enum {
WLCHW_STATE_ATTACH,
WLCHW_STATE_CLK,
WLCHW_STATE_UP,
WLCHW_STATE_ASSOC,
WLCHW_STATE_LAST
} wlc_bmac_state_id_t;
extern int wlc_bmac_attach(wlc_info_t * wlc, uint16 vendor, uint16 device,
uint unit, bool piomode, osl_t * osh, void *regsva,
uint bustype, void *btparam);
extern int wlc_bmac_detach(wlc_info_t * wlc);
extern void wlc_bmac_watchdog(void *arg);
extern void wlc_bmac_info_init(wlc_hw_info_t * wlc_hw);
/* up/down, reset, clk */
#ifdef WLC_LOW
extern void wlc_bmac_xtal(wlc_hw_info_t * wlc_hw, bool want);
#endif
extern void wlc_bmac_copyto_objmem(wlc_hw_info_t * wlc_hw,
uint offset, const void *buf, int len,
uint32 sel);
extern void wlc_bmac_copyfrom_objmem(wlc_hw_info_t * wlc_hw, uint offset,
void *buf, int len, uint32 sel);
#define wlc_bmac_copyfrom_shm(wlc_hw, offset, buf, len) \
wlc_bmac_copyfrom_objmem(wlc_hw, offset, buf, len, OBJADDR_SHM_SEL)
#define wlc_bmac_copyto_shm(wlc_hw, offset, buf, len) \
wlc_bmac_copyto_objmem(wlc_hw, offset, buf, len, OBJADDR_SHM_SEL)
extern void wlc_bmac_core_phy_clk(wlc_hw_info_t * wlc_hw, bool clk);
extern void wlc_bmac_core_phypll_reset(wlc_hw_info_t * wlc_hw);
extern void wlc_bmac_core_phypll_ctl(wlc_hw_info_t * wlc_hw, bool on);
extern void wlc_bmac_phyclk_fgc(wlc_hw_info_t * wlc_hw, bool clk);
extern void wlc_bmac_macphyclk_set(wlc_hw_info_t * wlc_hw, bool clk);
extern void wlc_bmac_phy_reset(wlc_hw_info_t * wlc_hw);
extern void wlc_bmac_corereset(wlc_hw_info_t * wlc_hw, uint32 flags);
extern void wlc_bmac_reset(wlc_hw_info_t * wlc_hw);
extern void wlc_bmac_init(wlc_hw_info_t * wlc_hw, chanspec_t chanspec,
bool mute);
extern int wlc_bmac_up_prep(wlc_hw_info_t * wlc_hw);
extern int wlc_bmac_up_finish(wlc_hw_info_t * wlc_hw);
extern int wlc_bmac_down_prep(wlc_hw_info_t * wlc_hw);
extern int wlc_bmac_down_finish(wlc_hw_info_t * wlc_hw);
extern void wlc_bmac_corereset(wlc_hw_info_t * wlc_hw, uint32 flags);
extern void wlc_bmac_switch_macfreq(wlc_hw_info_t * wlc_hw, uint8 spurmode);
/* chanspec, ucode interface */
extern int wlc_bmac_bandtype(wlc_hw_info_t * wlc_hw);
extern void wlc_bmac_set_chanspec(wlc_hw_info_t * wlc_hw, chanspec_t chanspec,
bool mute, struct txpwr_limits *txpwr);
extern void wlc_bmac_txfifo(wlc_hw_info_t * wlc_hw, uint fifo, void *p,
bool commit, uint16 frameid, uint8 txpktpend);
extern int wlc_bmac_xmtfifo_sz_get(wlc_hw_info_t * wlc_hw, uint fifo,
uint * blocks);
extern void wlc_bmac_mhf(wlc_hw_info_t * wlc_hw, uint8 idx, uint16 mask,
uint16 val, int bands);
extern void wlc_bmac_mctrl(wlc_hw_info_t * wlc_hw, uint32 mask, uint32 val);
extern uint16 wlc_bmac_mhf_get(wlc_hw_info_t * wlc_hw, uint8 idx, int bands);
extern int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t * wlc_hw, uint fifo,
uint blocks);
extern void wlc_bmac_txant_set(wlc_hw_info_t * wlc_hw, uint16 phytxant);
extern uint16 wlc_bmac_get_txant(wlc_hw_info_t * wlc_hw);
extern void wlc_bmac_antsel_type_set(wlc_hw_info_t * wlc_hw, uint8 antsel_type);
extern int wlc_bmac_revinfo_get(wlc_hw_info_t * wlc_hw,
wlc_bmac_revinfo_t * revinfo);
extern int wlc_bmac_state_get(wlc_hw_info_t * wlc_hw, wlc_bmac_state_t * state);
extern void wlc_bmac_write_shm(wlc_hw_info_t * wlc_hw, uint offset, uint16 v);
extern uint16 wlc_bmac_read_shm(wlc_hw_info_t * wlc_hw, uint offset);
extern void wlc_bmac_set_shm(wlc_hw_info_t * wlc_hw, uint offset, uint16 v,
int len);
extern void wlc_bmac_write_template_ram(wlc_hw_info_t * wlc_hw, int offset,
int len, void *buf);
extern void wlc_bmac_copyfrom_vars(wlc_hw_info_t * wlc_hw, char **buf,
uint * len);
extern void wlc_bmac_process_ps_switch(wlc_hw_info_t * wlc,
struct ether_addr *ea, int8 ps_on);
extern void wlc_bmac_hw_etheraddr(wlc_hw_info_t * wlc_hw,
struct ether_addr *ea);
extern void wlc_bmac_set_hw_etheraddr(wlc_hw_info_t * wlc_hw,
struct ether_addr *ea);
extern bool wlc_bmac_validate_chip_access(wlc_hw_info_t * wlc_hw);
extern bool wlc_bmac_radio_read_hwdisabled(wlc_hw_info_t * wlc_hw);
extern void wlc_bmac_set_shortslot(wlc_hw_info_t * wlc_hw, bool shortslot);
extern void wlc_bmac_mute(wlc_hw_info_t * wlc_hw, bool want, mbool flags);
extern void wlc_bmac_set_deaf(wlc_hw_info_t * wlc_hw, bool user_flag);
extern void wlc_bmac_band_stf_ss_set(wlc_hw_info_t * wlc_hw, uint8 stf_mode);
extern void wlc_bmac_wait_for_wake(wlc_hw_info_t * wlc_hw);
extern bool wlc_bmac_tx_fifo_suspended(wlc_hw_info_t * wlc_hw, uint tx_fifo);
extern void wlc_bmac_tx_fifo_suspend(wlc_hw_info_t * wlc_hw, uint tx_fifo);
extern void wlc_bmac_tx_fifo_resume(wlc_hw_info_t * wlc_hw, uint tx_fifo);
extern void wlc_ucode_wake_override_set(wlc_hw_info_t * wlc_hw,
uint32 override_bit);
extern void wlc_ucode_wake_override_clear(wlc_hw_info_t * wlc_hw,
uint32 override_bit);
extern void wlc_bmac_set_rcmta(wlc_hw_info_t * wlc_hw, int idx,
const struct ether_addr *addr);
extern void wlc_bmac_set_addrmatch(wlc_hw_info_t * wlc_hw, int match_reg_offset,
const struct ether_addr *addr);
extern void wlc_bmac_write_hw_bcntemplates(wlc_hw_info_t * wlc_hw, void *bcn,
int len, bool both);
extern void wlc_bmac_read_tsf(wlc_hw_info_t * wlc_hw, uint32 * tsf_l_ptr,
uint32 * tsf_h_ptr);
extern void wlc_bmac_set_cwmin(wlc_hw_info_t * wlc_hw, uint16 newmin);
extern void wlc_bmac_set_cwmax(wlc_hw_info_t * wlc_hw, uint16 newmax);
extern void wlc_bmac_set_noreset(wlc_hw_info_t * wlc, bool noreset_flag);
extern void wlc_bmac_set_ucode_loaded(wlc_hw_info_t * wlc, bool ucode_loaded);
extern void wlc_bmac_retrylimit_upd(wlc_hw_info_t * wlc_hw, uint16 SRL,
uint16 LRL);
extern void wlc_bmac_fifoerrors(wlc_hw_info_t * wlc_hw);
#ifdef WLC_HIGH_ONLY
extern void wlc_bmac_dngl_reboot(rpc_info_t *);
extern void wlc_bmac_dngl_rpc_agg(rpc_info_t *, uint16 agg);
extern void wlc_bmac_dngl_rpc_msglevel(rpc_info_t *, uint16 level);
extern void wlc_bmac_dngl_rpc_txq_wm_set(rpc_info_t * rpc, uint32 wm);
extern void wlc_bmac_dngl_rpc_txq_wm_get(rpc_info_t * rpc, uint32 * wm);
extern void wlc_bmac_dngl_rpc_agg_limit_set(rpc_info_t * rpc, uint32 val);
extern void wlc_bmac_dngl_rpc_agg_limit_get(rpc_info_t * rpc, uint32 * pval);
extern int wlc_bmac_debug_template(wlc_hw_info_t * wlc_hw);
#endif
/* API for BMAC driver (e.g. wlc_phy.c etc) */
extern void wlc_bmac_bw_set(wlc_hw_info_t * wlc_hw, uint16 bw);
extern void wlc_bmac_pllreq(wlc_hw_info_t * wlc_hw, bool set, mbool req_bit);
extern void wlc_bmac_set_clk(wlc_hw_info_t * wlc_hw, bool on);
extern bool wlc_bmac_taclear(wlc_hw_info_t * wlc_hw, bool ta_ok);
extern void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw);
extern void wlc_bmac_dump(wlc_hw_info_t * wlc_hw, struct bcmstrbuf *b,
wlc_bmac_dump_id_t dump_id);
extern void wlc_gpio_fast_deinit(wlc_hw_info_t * wlc_hw);
extern bool wlc_bmac_radio_hw(wlc_hw_info_t * wlc_hw, bool enable);
extern uint16 wlc_bmac_rate_shm_offset(wlc_hw_info_t * wlc_hw, uint8 rate);
extern void wlc_bmac_assert_type_set(wlc_hw_info_t * wlc_hw, uint32 type);
extern void wlc_bmac_set_txpwr_percent(wlc_hw_info_t * wlc_hw, uint8 val);
extern void wlc_bmac_blink_sync(wlc_hw_info_t * wlc_hw, uint32 led_pins);
extern void wlc_bmac_ifsctl_edcrs_set(wlc_hw_info_t * wlc_hw, bool abie,
bool isht);
extern void wlc_bmac_antsel_set(wlc_hw_info_t * wlc_hw, uint32 antsel_avail);

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _WLC_BSSCFG_H_
#define _WLC_BSSCFG_H_
#include <wlc_types.h>
/* Check if a particular BSS config is AP or STA */
#define BSSCFG_AP(cfg) (0)
#define BSSCFG_STA(cfg) (1)
#define BSSCFG_IBSS(cfg) (!(cfg)->BSS)
/* forward declarations */
typedef struct wlc_bsscfg wlc_bsscfg_t;
#include <wlc_rate.h>
#define NTXRATE 64 /* # tx MPDUs rate is reported for */
#define MAXMACLIST 64 /* max # source MAC matches */
#define BCN_TEMPLATE_COUNT 2
/* Iterator for "associated" STA bss configs: (wlc_info_t *wlc, int idx, wlc_bsscfg_t *cfg) */
#define FOREACH_AS_STA(wlc, idx, cfg) \
for (idx = 0; (int) idx < WLC_MAXBSSCFG; idx++) \
if ((cfg = (wlc)->bsscfg[idx]) && BSSCFG_STA(cfg) && cfg->associated)
/* As above for all non-NULL BSS configs */
#define FOREACH_BSS(wlc, idx, cfg) \
for (idx = 0; (int) idx < WLC_MAXBSSCFG; idx++) \
if ((cfg = (wlc)->bsscfg[idx]))
/* BSS configuration state */
struct wlc_bsscfg {
struct wlc_info *wlc; /* wlc to which this bsscfg belongs to. */
bool up; /* is this configuration up operational */
bool enable; /* is this configuration enabled */
bool associated; /* is BSS in ASSOCIATED state */
bool BSS; /* infraustructure or adhac */
bool dtim_programmed;
#ifdef LATER
bool _ap; /* is this configuration an AP */
struct wlc_if *wlcif; /* virtual interface, NULL for primary bsscfg */
void *sup; /* pointer to supplicant state */
int8 sup_type; /* type of supplicant */
bool sup_enable_wpa; /* supplicant WPA on/off */
void *authenticator; /* pointer to authenticator state */
bool sup_auth_pending; /* flag for auth timeout */
#endif
uint8 SSID_len; /* the length of SSID */
uint8 SSID[DOT11_MAX_SSID_LEN]; /* SSID string */
struct scb *bcmc_scb[MAXBANDS]; /* one bcmc_scb per band */
int8 _idx; /* the index of this bsscfg,
* assigned at wlc_bsscfg_alloc()
*/
/* MAC filter */
uint nmac; /* # of entries on maclist array */
int macmode; /* allow/deny stations on maclist array */
struct ether_addr *maclist; /* list of source MAC addrs to match */
/* security */
uint32 wsec; /* wireless security bitvec */
int16 auth; /* 802.11 authentication: Open, Shared Key, WPA */
int16 openshared; /* try Open auth first, then Shared Key */
bool wsec_restrict; /* drop unencrypted packets if wsec is enabled */
bool eap_restrict; /* restrict data until 802.1X auth succeeds */
uint16 WPA_auth; /* WPA: authenticated key management */
bool wpa2_preauth; /* default is TRUE, wpa_cap sets value */
bool wsec_portopen; /* indicates keys are plumbed */
wsec_iv_t wpa_none_txiv; /* global txiv for WPA_NONE, tkip and aes */
int wsec_index; /* 0-3: default tx key, -1: not set */
wsec_key_t *bss_def_keys[WLC_DEFAULT_KEYS]; /* default key storage */
/* TKIP countermeasures */
bool tkip_countermeasures; /* flags TKIP no-assoc period */
uint32 tk_cm_dt; /* detect timer */
uint32 tk_cm_bt; /* blocking timer */
uint32 tk_cm_bt_tmstmp; /* Timestamp when TKIP BT is activated */
bool tk_cm_activate; /* activate countermeasures after EAPOL-Key sent */
struct ether_addr BSSID; /* BSSID (associated) */
struct ether_addr cur_etheraddr; /* h/w address */
uint16 bcmc_fid; /* the last BCMC FID queued to TX_BCMC_FIFO */
uint16 bcmc_fid_shm; /* the last BCMC FID written to shared mem */
uint32 flags; /* WLC_BSSCFG flags; see below */
uint8 *bcn; /* AP beacon */
uint bcn_len; /* AP beacon length */
bool ar_disassoc; /* disassociated in associated recreation */
int auth_atmptd; /* auth type (open/shared) attempted */
pmkid_cand_t pmkid_cand[MAXPMKID]; /* PMKID candidate list */
uint npmkid_cand; /* num PMKID candidates */
pmkid_t pmkid[MAXPMKID]; /* PMKID cache */
uint npmkid; /* num cached PMKIDs */
wlc_bss_info_t *target_bss; /* BSS parms during tran. to ASSOCIATED state */
wlc_bss_info_t *current_bss; /* BSS parms in ASSOCIATED state */
/* PM states */
bool PMawakebcn; /* bcn recvd during current waking state */
bool PMpending; /* waiting for tx status with PM indicated set */
bool priorPMstate; /* Detecting PM state transitions */
bool PSpoll; /* whether there is an outstanding PS-Poll frame */
/* BSSID entry in RCMTA, use the wsec key management infrastructure to
* manage the RCMTA entries.
*/
wsec_key_t *rcmta;
/* 'unique' ID of this bsscfg, assigned at bsscfg allocation */
uint16 ID;
uint txrspecidx; /* index into tx rate circular buffer */
ratespec_t txrspec[NTXRATE][2]; /* circular buffer of prev MPDUs tx rates */
};
#define WLC_BSSCFG_11N_DISABLE 0x1000 /* Do not advertise .11n IEs for this BSS */
#define WLC_BSSCFG_HW_BCN 0x20 /* The BSS is generating beacons in HW */
#define HWBCN_ENAB(cfg) (((cfg)->flags & WLC_BSSCFG_HW_BCN) != 0)
#define HWPRB_ENAB(cfg) (((cfg)->flags & WLC_BSSCFG_HW_PRB) != 0)
extern void wlc_bsscfg_ID_assign(struct wlc_info *wlc, wlc_bsscfg_t * bsscfg);
/* Extend N_ENAB to per-BSS */
#define BSS_N_ENAB(wlc, cfg) \
(N_ENAB((wlc)->pub) && !((cfg)->flags & WLC_BSSCFG_11N_DISABLE))
#define MBSS_BCN_ENAB(cfg) 0
#define MBSS_PRB_ENAB(cfg) 0
#define SOFTBCN_ENAB(pub) (0)
#define SOFTPRB_ENAB(pub) (0)
#define wlc_bsscfg_tx_check(a) do { } while (0);
#endif /* _WLC_BSSCFG_H_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _wlc_cfg_h_
#define _wlc_cfg_h_
#define NBANDS(wlc) ((wlc)->pub->_nbands)
#define NBANDS_PUB(pub) ((pub)->_nbands)
#define NBANDS_HW(hw) ((hw)->_nbands)
#define IS_SINGLEBAND_5G(device) 0
/* Keep WLC_HIGH_ONLY, WLC_SPLIT for USB extension later on */
#if !defined(WLC_LOW)
#define WLC_HIGH_ONLY
#endif
#if !defined(WLC_LOW)
#define WLC_SPLIT
#endif
/* **** Core type/rev defaults **** */
#define D11_DEFAULT 0x0fffffb0 /* Supported D11 revs: 4, 5, 7-27
* also need to update wlc.h MAXCOREREV
*/
#define NPHY_DEFAULT 0x000001ff /* Supported nphy revs:
* 0 4321a0
* 1 4321a1
* 2 4321b0/b1/c0/c1
* 3 4322a0
* 4 4322a1
* 5 4716a0
* 6 43222a0, 43224a0
* 7 43226a0
* 8 5357a0, 43236a0
*/
#define LCNPHY_DEFAULT 0x00000007 /* Supported lcnphy revs:
* 0 4313a0, 4336a0, 4330a0
* 1
* 2 4330a0
*/
#define SSLPNPHY_DEFAULT 0x0000000f /* Supported sslpnphy revs:
* 0 4329a0/k0
* 1 4329b0/4329C0
* 2 4319a0
* 3 5356a0
*/
#ifdef BCMSDIO
#define D11CONF 0x100000
#define SSLPNCONF 2
#define GCCONF 0
#define ACCONF 0
#define NCONF 0
#define LPCONF 0
#define LCNCONF 0
#define NTXD 32
#define NRXD 16
#define NRXBUFPOST 8
#define WLC_DATAHIWAT 32
#define RXBND 8
#define MAXPKTCB 64
#define AMPDU_NUM_MPDU 8
#endif
/* For undefined values, use defaults */
#ifndef D11CONF
#define D11CONF D11_DEFAULT
#endif
#ifndef NCONF
#define NCONF NPHY_DEFAULT
#endif
#ifndef LCNCONF
#define LCNCONF LCNPHY_DEFAULT
#endif
#ifndef SSLPNCONF
#define SSLPNCONF SSLPNPHY_DEFAULT
#endif
#define BAND2G
#define BAND5G
#define WLANTSEL 1
/********************************************************************
* Phy/Core Configuration. Defines macros to to check core phy/rev *
* compile-time configuration. Defines default core support. *
* ******************************************************************
*/
/* Basic macros to check a configuration bitmask */
#define CONF_HAS(config, val) ((config) & (1 << (val)))
#define CONF_MSK(config, mask) ((config) & (mask))
#define MSK_RANGE(low, hi) ((1 << ((hi)+1)) - (1 << (low)))
#define CONF_RANGE(config, low, hi) (CONF_MSK(config, MSK_RANGE(low, high)))
#define CONF_IS(config, val) ((config) == (1 << (val)))
#define CONF_GE(config, val) ((config) & (0-(1 << (val))))
#define CONF_GT(config, val) ((config) & (0-2*(1 << (val))))
#define CONF_LT(config, val) ((config) & ((1 << (val))-1))
#define CONF_LE(config, val) ((config) & (2*(1 << (val))-1))
/* Wrappers for some of the above, specific to config constants */
#define NCONF_HAS(val) CONF_HAS(NCONF, val)
#define NCONF_MSK(mask) CONF_MSK(NCONF, mask)
#define NCONF_IS(val) CONF_IS(NCONF, val)
#define NCONF_GE(val) CONF_GE(NCONF, val)
#define NCONF_GT(val) CONF_GT(NCONF, val)
#define NCONF_LT(val) CONF_LT(NCONF, val)
#define NCONF_LE(val) CONF_LE(NCONF, val)
#define LCNCONF_HAS(val) CONF_HAS(LCNCONF, val)
#define LCNCONF_MSK(mask) CONF_MSK(LCNCONF, mask)
#define LCNCONF_IS(val) CONF_IS(LCNCONF, val)
#define LCNCONF_GE(val) CONF_GE(LCNCONF, val)
#define LCNCONF_GT(val) CONF_GT(LCNCONF, val)
#define LCNCONF_LT(val) CONF_LT(LCNCONF, val)
#define LCNCONF_LE(val) CONF_LE(LCNCONF, val)
#define D11CONF_HAS(val) CONF_HAS(D11CONF, val)
#define D11CONF_MSK(mask) CONF_MSK(D11CONF, mask)
#define D11CONF_IS(val) CONF_IS(D11CONF, val)
#define D11CONF_GE(val) CONF_GE(D11CONF, val)
#define D11CONF_GT(val) CONF_GT(D11CONF, val)
#define D11CONF_LT(val) CONF_LT(D11CONF, val)
#define D11CONF_LE(val) CONF_LE(D11CONF, val)
#define PHYCONF_HAS(val) CONF_HAS(PHYTYPE, val)
#define PHYCONF_IS(val) CONF_IS(PHYTYPE, val)
#define NREV_IS(var, val) (NCONF_HAS(val) && (NCONF_IS(val) || ((var) == (val))))
#define NREV_GE(var, val) (NCONF_GE(val) && (!NCONF_LT(val) || ((var) >= (val))))
#define NREV_GT(var, val) (NCONF_GT(val) && (!NCONF_LE(val) || ((var) > (val))))
#define NREV_LT(var, val) (NCONF_LT(val) && (!NCONF_GE(val) || ((var) < (val))))
#define NREV_LE(var, val) (NCONF_LE(val) && (!NCONF_GT(val) || ((var) <= (val))))
#define LCNREV_IS(var, val) (LCNCONF_HAS(val) && (LCNCONF_IS(val) || ((var) == (val))))
#define LCNREV_GE(var, val) (LCNCONF_GE(val) && (!LCNCONF_LT(val) || ((var) >= (val))))
#define LCNREV_GT(var, val) (LCNCONF_GT(val) && (!LCNCONF_LE(val) || ((var) > (val))))
#define LCNREV_LT(var, val) (LCNCONF_LT(val) && (!LCNCONF_GE(val) || ((var) < (val))))
#define LCNREV_LE(var, val) (LCNCONF_LE(val) && (!LCNCONF_GT(val) || ((var) <= (val))))
#define D11REV_IS(var, val) (D11CONF_HAS(val) && (D11CONF_IS(val) || ((var) == (val))))
#define D11REV_GE(var, val) (D11CONF_GE(val) && (!D11CONF_LT(val) || ((var) >= (val))))
#define D11REV_GT(var, val) (D11CONF_GT(val) && (!D11CONF_LE(val) || ((var) > (val))))
#define D11REV_LT(var, val) (D11CONF_LT(val) && (!D11CONF_GE(val) || ((var) < (val))))
#define D11REV_LE(var, val) (D11CONF_LE(val) && (!D11CONF_GT(val) || ((var) <= (val))))
#define PHYTYPE_IS(var, val) (PHYCONF_HAS(val) && (PHYCONF_IS(val) || ((var) == (val))))
/* Finally, early-exit from switch case if anyone wants it... */
#define CASECHECK(config, val) if (!(CONF_HAS(config, val))) break
#define CASEMSK(config, mask) if (!(CONF_MSK(config, mask))) break
#if (D11CONF ^ (D11CONF & D11_DEFAULT))
#error "Unsupported MAC revision configured"
#endif
#if (NCONF ^ (NCONF & NPHY_DEFAULT))
#error "Unsupported NPHY revision configured"
#endif
#if (LCNCONF ^ (LCNCONF & LCNPHY_DEFAULT))
#error "Unsupported LPPHY revision configured"
#endif
/* *** Consistency checks *** */
#if !D11CONF
#error "No MAC revisions configured!"
#endif
#if !NCONF && !LCNCONF && !SSLPNCONF
#error "No PHY configured!"
#endif
/* Set up PHYTYPE automatically: (depends on PHY_TYPE_X, from d11.h) */
#define _PHYCONF_N (1 << PHY_TYPE_N)
#if LCNCONF
#define _PHYCONF_LCN (1 << PHY_TYPE_LCN)
#else
#define _PHYCONF_LCN 0
#endif /* LCNCONF */
#if SSLPNCONF
#define _PHYCONF_SSLPN (1 << PHY_TYPE_SSN)
#else
#define _PHYCONF_SSLPN 0
#endif /* SSLPNCONF */
#define PHYTYPE (_PHYCONF_N | _PHYCONF_LCN | _PHYCONF_SSLPN)
/* Utility macro to identify 802.11n (HT) capable PHYs */
#define PHYTYPE_11N_CAP(phytype) \
(PHYTYPE_IS(phytype, PHY_TYPE_N) || \
PHYTYPE_IS(phytype, PHY_TYPE_LCN) || \
PHYTYPE_IS(phytype, PHY_TYPE_SSN))
/* Last but not least: shorter wlc-specific var checks */
#define WLCISNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_N)
#define WLCISLCNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_LCN)
#define WLCISSSLPNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_SSN)
#define WLC_PHY_11N_CAP(band) PHYTYPE_11N_CAP((band)->phytype)
/**********************************************************************
* ------------- End of Core phy/rev configuration. ----------------- *
* ********************************************************************
*/
/*************************************************
* Defaults for tunables (e.g. sizing constants)
*
* For each new tunable, add a member to the end
* of wlc_tunables_t in wlc_pub.h to enable
* runtime checks of tunable values. (Directly
* using the macros in code invalidates ROM code)
*
* ***********************************************
*/
#ifndef NTXD
#define NTXD 256 /* Max # of entries in Tx FIFO based on 4kb page size */
#endif /* NTXD */
#ifndef NRXD
#define NRXD 256 /* Max # of entries in Rx FIFO based on 4kb page size */
#endif /* NRXD */
#ifndef NRXBUFPOST
#define NRXBUFPOST 32 /* try to keep this # rbufs posted to the chip */
#endif /* NRXBUFPOST */
#ifndef MAXSCB /* station control blocks in cache */
#define MAXSCB 32 /* Maximum SCBs in cache for STA */
#endif /* MAXSCB */
#ifndef AMPDU_NUM_MPDU
#define AMPDU_NUM_MPDU 16 /* max allowed number of mpdus in an ampdu (2 streams) */
#endif /* AMPDU_NUM_MPDU */
#ifndef AMPDU_NUM_MPDU_3STREAMS
#define AMPDU_NUM_MPDU_3STREAMS 32 /* max allowed number of mpdus in an ampdu for 3+ streams */
#endif /* AMPDU_NUM_MPDU_3STREAMS */
/* Count of packet callback structures. either of following
* 1. Set to the number of SCBs since a STA
* can queue up a rate callback for each IBSS STA it knows about, and an AP can
* queue up an "are you there?" Null Data callback for each associated STA
* 2. controlled by tunable config file
*/
#ifndef MAXPKTCB
#define MAXPKTCB MAXSCB /* Max number of packet callbacks */
#endif /* MAXPKTCB */
#ifndef CTFPOOLSZ
#define CTFPOOLSZ 128
#endif /* CTFPOOLSZ */
/* NetBSD also needs to keep track of this */
#define WLC_MAX_UCODE_BSS (16) /* Number of BSS handled in ucode bcn/prb */
#define WLC_MAX_UCODE_BSS4 (4) /* Number of BSS handled in sw bcn/prb */
#ifndef WLC_MAXBSSCFG
#define WLC_MAXBSSCFG (1) /* max # BSS configs */
#endif /* WLC_MAXBSSCFG */
#ifndef MAXBSS
#define MAXBSS 64 /* max # available networks */
#endif /* MAXBSS */
#ifndef WLC_DATAHIWAT
#define WLC_DATAHIWAT 50 /* data msg txq hiwat mark */
#endif /* WLC_DATAHIWAT */
#ifndef WLC_AMPDUDATAHIWAT
#define WLC_AMPDUDATAHIWAT 255
#endif /* WLC_AMPDUDATAHIWAT */
/* bounded rx loops */
#ifndef RXBND
#define RXBND 8 /* max # frames to process in wlc_recv() */
#endif /* RXBND */
#ifndef TXSBND
#define TXSBND 8 /* max # tx status to process in wlc_txstatus() */
#endif /* TXSBND */
#define BAND_5G(bt) ((bt) == WLC_BAND_5G)
#define BAND_2G(bt) ((bt) == WLC_BAND_2G)
#define WLBANDINITDATA(_data) _data
#define WLBANDINITFN(_fn) _fn
#define WLANTSEL_ENAB(wlc) 1
#endif /* _wlc_cfg_h_ */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _WLC_CHANNEL_H_
#define _WLC_CHANNEL_H_
#include <wlc_phy_hal.h>
#define WLC_TXPWR_DB_FACTOR 4 /* conversion for phy txpwr cacluations that use .25 dB units */
struct wlc_info;
/* maxpwr mapping to 5GHz band channels:
* maxpwr[0] - channels [34-48]
* maxpwr[1] - channels [52-60]
* maxpwr[2] - channels [62-64]
* maxpwr[3] - channels [100-140]
* maxpwr[4] - channels [149-165]
*/
#define BAND_5G_PWR_LVLS 5 /* 5 power levels for 5G */
/* power level in group of 2.4GHz band channels:
* maxpwr[0] - CCK channels [1]
* maxpwr[1] - CCK channels [2-10]
* maxpwr[2] - CCK channels [11-14]
* maxpwr[3] - OFDM channels [1]
* maxpwr[4] - OFDM channels [2-10]
* maxpwr[5] - OFDM channels [11-14]
*/
/* macro to get 2.4 GHz channel group index for tx power */
#define CHANNEL_POWER_IDX_2G_CCK(c) (((c) < 2) ? 0 : (((c) < 11) ? 1 : 2)) /* cck index */
#define CHANNEL_POWER_IDX_2G_OFDM(c) (((c) < 2) ? 3 : (((c) < 11) ? 4 : 5)) /* ofdm index */
/* macro to get 5 GHz channel group index for tx power */
#define CHANNEL_POWER_IDX_5G(c) \
(((c) < 52) ? 0 : (((c) < 62) ? 1 :(((c) < 100) ? 2 : (((c) < 149) ? 3 : 4))))
#define WLC_MAXPWR_TBL_SIZE 6 /* max of BAND_5G_PWR_LVLS and 6 for 2.4 GHz */
#define WLC_MAXPWR_MIMO_TBL_SIZE 14 /* max of BAND_5G_PWR_LVLS and 14 for 2.4 GHz */
/* locale channel and power info. */
typedef struct {
uint32 valid_channels;
uint8 radar_channels; /* List of radar sensitive channels */
uint8 restricted_channels; /* List of channels used only if APs are detected */
int8 maxpwr[WLC_MAXPWR_TBL_SIZE]; /* Max tx pwr in qdBm for each sub-band */
int8 pub_maxpwr[BAND_5G_PWR_LVLS]; /* Country IE advertised max tx pwr in dBm
* per sub-band
*/
uint8 flags;
} locale_info_t;
/* bits for locale_info flags */
#define WLC_PEAK_CONDUCTED 0x00 /* Peak for locals */
#define WLC_EIRP 0x01 /* Flag for EIRP */
#define WLC_DFS_TPC 0x02 /* Flag for DFS TPC */
#define WLC_NO_OFDM 0x04 /* Flag for No OFDM */
#define WLC_NO_40MHZ 0x08 /* Flag for No MIMO 40MHz */
#define WLC_NO_MIMO 0x10 /* Flag for No MIMO, 20 or 40 MHz */
#define WLC_RADAR_TYPE_EU 0x20 /* Flag for EU */
#define WLC_DFS_FCC WLC_DFS_TPC /* Flag for DFS FCC */
#define WLC_DFS_EU (WLC_DFS_TPC | WLC_RADAR_TYPE_EU) /* Flag for DFS EU */
#define ISDFS_EU(fl) (((fl) & WLC_DFS_EU) == WLC_DFS_EU)
/* locale per-channel tx power limits for MIMO frames
* maxpwr arrays are index by channel for 2.4 GHz limits, and
* by sub-band for 5 GHz limits using CHANNEL_POWER_IDX_5G(channel)
*/
typedef struct {
int8 maxpwr20[WLC_MAXPWR_MIMO_TBL_SIZE]; /* tx 20 MHz power limits, qdBm units */
int8 maxpwr40[WLC_MAXPWR_MIMO_TBL_SIZE]; /* tx 40 MHz power limits, qdBm units */
uint8 flags;
} locale_mimo_info_t;
extern const chanvec_t chanvec_all_2G;
extern const chanvec_t chanvec_all_5G;
/*
* Country names and abbreviations with locale defined from ISO 3166
*/
struct country_info {
const uint8 locale_2G; /* 2.4G band locale */
const uint8 locale_5G; /* 5G band locale */
const uint8 locale_mimo_2G; /* 2.4G mimo info */
const uint8 locale_mimo_5G; /* 5G mimo info */
};
typedef struct country_info country_info_t;
typedef struct wlc_cm_info wlc_cm_info_t;
extern wlc_cm_info_t *wlc_channel_mgr_attach(struct wlc_info *wlc);
extern void wlc_channel_mgr_detach(wlc_cm_info_t * wlc_cm);
extern int wlc_set_countrycode(wlc_cm_info_t * wlc_cm, const char *ccode);
extern int wlc_set_countrycode_rev(wlc_cm_info_t * wlc_cm,
const char *country_abbrev,
const char *ccode, int regrev);
extern const char *wlc_channel_country_abbrev(wlc_cm_info_t * wlc_cm);
extern uint8 wlc_channel_locale_flags(wlc_cm_info_t * wlc_cm);
extern uint8 wlc_channel_locale_flags_in_band(wlc_cm_info_t * wlc_cm,
uint bandunit);
extern void wlc_quiet_channels_reset(wlc_cm_info_t * wlc_cm);
extern bool wlc_quiet_chanspec(wlc_cm_info_t * wlc_cm, chanspec_t chspec);
#define VALID_CHANNEL20_DB(wlc, val) wlc_valid_channel20_db((wlc)->cmi, val)
#define VALID_CHANNEL20_IN_BAND(wlc, bandunit, val) \
wlc_valid_channel20_in_band((wlc)->cmi, bandunit, val)
#define VALID_CHANNEL20(wlc, val) wlc_valid_channel20((wlc)->cmi, val)
#define VALID_40CHANSPEC_IN_BAND(wlc, bandunit) wlc_valid_40chanspec_in_band((wlc)->cmi, bandunit)
extern bool wlc_valid_chanspec(wlc_cm_info_t * wlc_cm, chanspec_t chspec);
extern bool wlc_valid_chanspec_db(wlc_cm_info_t * wlc_cm, chanspec_t chspec);
extern bool wlc_valid_channel20_db(wlc_cm_info_t * wlc_cm, uint val);
extern bool wlc_valid_channel20_in_band(wlc_cm_info_t * wlc_cm, uint bandunit,
uint val);
extern bool wlc_valid_channel20(wlc_cm_info_t * wlc_cm, uint val);
extern bool wlc_valid_40chanspec_in_band(wlc_cm_info_t * wlc_cm, uint bandunit);
extern void wlc_channel_reg_limits(wlc_cm_info_t * wlc_cm,
chanspec_t chanspec,
struct txpwr_limits *txpwr);
extern void wlc_channel_set_chanspec(wlc_cm_info_t * wlc_cm,
chanspec_t chanspec,
uint8 local_constraint_qdbm);
extern int wlc_channel_set_txpower_limit(wlc_cm_info_t * wlc_cm,
uint8 local_constraint_qdbm);
extern const country_info_t *wlc_country_lookup(struct wlc_info *wlc,
const char *ccode);
extern void wlc_locale_get_channels(const locale_info_t * locale,
chanvec_t * valid_channels);
extern const locale_info_t *wlc_get_locale_2g(uint8 locale_idx);
extern const locale_info_t *wlc_get_locale_5g(uint8 locale_idx);
extern bool wlc_japan(struct wlc_info *wlc);
extern uint8 wlc_get_regclass(wlc_cm_info_t * wlc_cm, chanspec_t chanspec);
extern bool wlc_channel_get_chanvec(struct wlc_info *wlc,
const char *country_abbrev, int bandtype,
chanvec_t * channels);
#endif /* _WLC_CHANNEL_H */

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/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <typedefs.h>
#include <bcmutils.h>
#include <siutils.h>
#include <bcmendian.h>
#include <wlioctl.h>
#include <wl_dbg.h>
#include <wlc_cfg.h>
#include <wlc_pub.h>
#include <wlc_key.h>
#include <wl_export.h>
#include <wlc_event.h>
#include <d11.h>
#include <wlc_rate.h>
#include <wlc_mac80211.h>
#ifdef MSGTRACE
#include <msgtrace.h>
#endif
/* Local prototypes */
static void wlc_timer_cb(void *arg);
/* Private data structures */
struct wlc_eventq {
wlc_event_t *head;
wlc_event_t *tail;
struct wlc_info *wlc;
void *wl;
wlc_pub_t *pub;
bool tpending;
bool workpending;
struct wl_timer *timer;
wlc_eventq_cb_t cb;
uint8 event_inds_mask[ROUNDUP(WLC_E_LAST, NBBY) / NBBY];
};
/*
* Export functions
*/
wlc_eventq_t *BCMATTACHFN(wlc_eventq_attach) (wlc_pub_t * pub,
struct wlc_info * wlc, void *wl,
wlc_eventq_cb_t cb) {
wlc_eventq_t *eq;
eq = (wlc_eventq_t *) MALLOC(pub->osh, sizeof(wlc_eventq_t));
if (eq == NULL)
return NULL;
bzero(eq, sizeof(wlc_eventq_t));
eq->cb = cb;
eq->wlc = wlc;
eq->wl = wl;
eq->pub = pub;
if (!(eq->timer = wl_init_timer(eq->wl, wlc_timer_cb, eq, "eventq"))) {
WL_ERROR(("wl%d: wlc_eventq_attach: timer failed\n",
pub->unit));
MFREE(eq->pub->osh, eq, sizeof(wlc_eventq_t));
return NULL;
}
return eq;
}
int BCMATTACHFN(wlc_eventq_detach) (wlc_eventq_t * eq) {
/* Clean up pending events */
wlc_eventq_down(eq);
if (eq->timer) {
if (eq->tpending) {
wl_del_timer(eq->wl, eq->timer);
eq->tpending = FALSE;
}
wl_free_timer(eq->wl, eq->timer);
eq->timer = NULL;
}
ASSERT(wlc_eventq_avail(eq) == FALSE);
MFREE(eq->pub->osh, eq, sizeof(wlc_eventq_t));
return 0;
}
int BCMUNINITFN(wlc_eventq_down) (wlc_eventq_t * eq) {
int callbacks = 0;
if (eq->tpending && !eq->workpending) {
if (!wl_del_timer(eq->wl, eq->timer))
callbacks++;
ASSERT(wlc_eventq_avail(eq) == TRUE);
ASSERT(eq->workpending == FALSE);
eq->workpending = TRUE;
if (eq->cb)
eq->cb(eq->wlc);
ASSERT(eq->workpending == TRUE);
eq->workpending = FALSE;
eq->tpending = FALSE;
} else {
ASSERT(eq->workpending || wlc_eventq_avail(eq) == FALSE);
}
return callbacks;
}
wlc_event_t *wlc_event_alloc(wlc_eventq_t * eq)
{
wlc_event_t *e;
e = MALLOC(eq->pub->osh, sizeof(wlc_event_t));
if (e == NULL)
return NULL;
bzero(e, sizeof(wlc_event_t));
return e;
}
void wlc_event_free(wlc_eventq_t * eq, wlc_event_t * e)
{
ASSERT(e->data == NULL);
ASSERT(e->next == NULL);
MFREE(eq->pub->osh, e, sizeof(wlc_event_t));
}
void wlc_eventq_enq(wlc_eventq_t * eq, wlc_event_t * e)
{
ASSERT(e->next == NULL);
e->next = NULL;
if (eq->tail) {
eq->tail->next = e;
eq->tail = e;
} else
eq->head = eq->tail = e;
if (!eq->tpending) {
eq->tpending = TRUE;
/* Use a zero-delay timer to trigger
* delayed processing of the event.
*/
wl_add_timer(eq->wl, eq->timer, 0, 0);
}
}
wlc_event_t *wlc_eventq_deq(wlc_eventq_t * eq)
{
wlc_event_t *e;
e = eq->head;
if (e) {
eq->head = e->next;
e->next = NULL;
if (eq->head == NULL)
eq->tail = eq->head;
}
return e;
}
wlc_event_t *wlc_eventq_next(wlc_eventq_t * eq, wlc_event_t * e)
{
#ifdef BCMDBG
wlc_event_t *etmp;
for (etmp = eq->head; etmp; etmp = etmp->next) {
if (etmp == e)
break;
}
ASSERT(etmp != NULL);
#endif
return e->next;
}
int wlc_eventq_cnt(wlc_eventq_t * eq)
{
wlc_event_t *etmp;
int cnt = 0;
for (etmp = eq->head; etmp; etmp = etmp->next)
cnt++;
return cnt;
}
bool wlc_eventq_avail(wlc_eventq_t * eq)
{
return (eq->head != NULL);
}
/*
* Local Functions
*/
static void wlc_timer_cb(void *arg)
{
struct wlc_eventq *eq = (struct wlc_eventq *)arg;
ASSERT(eq->tpending == TRUE);
ASSERT(wlc_eventq_avail(eq) == TRUE);
ASSERT(eq->workpending == FALSE);
eq->workpending = TRUE;
if (eq->cb)
eq->cb(eq->wlc);
ASSERT(wlc_eventq_avail(eq) == FALSE);
ASSERT(eq->tpending == TRUE);
eq->workpending = FALSE;
eq->tpending = FALSE;
}

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