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clk: samsung: add plls used by the s3c2443
The s3c2443 uses different plls that are not present yet. Therefore add the two needed types. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -58,6 +58,72 @@ static long samsung_pll_round_rate(struct clk_hw *hw,
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return rate_table[i - 1].rate;
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}
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/*
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* PLL2126 Clock Type
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*/
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#define PLL2126_MDIV_MASK (0xff)
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#define PLL2126_PDIV_MASK (0x3f)
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#define PLL2126_SDIV_MASK (0x3)
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#define PLL2126_MDIV_SHIFT (16)
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#define PLL2126_PDIV_SHIFT (8)
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#define PLL2126_SDIV_SHIFT (0)
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static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct samsung_clk_pll *pll = to_clk_pll(hw);
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u32 pll_con, mdiv, pdiv, sdiv;
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u64 fvco = parent_rate;
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pll_con = __raw_readl(pll->con_reg);
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mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK;
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pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK;
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sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK;
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fvco *= (mdiv + 8);
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do_div(fvco, (pdiv + 2) << sdiv);
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return (unsigned long)fvco;
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}
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static const struct clk_ops samsung_pll2126_clk_ops = {
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.recalc_rate = samsung_pll2126_recalc_rate,
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};
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/*
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* PLL3000 Clock Type
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*/
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#define PLL3000_MDIV_MASK (0xff)
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#define PLL3000_PDIV_MASK (0x3)
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#define PLL3000_SDIV_MASK (0x3)
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#define PLL3000_MDIV_SHIFT (16)
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#define PLL3000_PDIV_SHIFT (8)
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#define PLL3000_SDIV_SHIFT (0)
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static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct samsung_clk_pll *pll = to_clk_pll(hw);
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u32 pll_con, mdiv, pdiv, sdiv;
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u64 fvco = parent_rate;
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pll_con = __raw_readl(pll->con_reg);
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mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK;
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pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK;
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sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK;
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fvco *= (2 * (mdiv + 8));
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do_div(fvco, pdiv << sdiv);
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return (unsigned long)fvco;
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}
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static const struct clk_ops samsung_pll3000_clk_ops = {
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.recalc_rate = samsung_pll3000_recalc_rate,
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};
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/*
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* PLL35xx Clock Type
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*/
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@ -753,6 +819,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
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}
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switch (pll_clk->type) {
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case pll_2126:
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init.ops = &samsung_pll2126_clk_ops;
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break;
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case pll_3000:
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init.ops = &samsung_pll3000_clk_ops;
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break;
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/* clk_ops for 35xx and 2550 are similar */
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case pll_35xx:
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case pll_2550:
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@ -13,6 +13,8 @@
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#define __SAMSUNG_CLK_PLL_H
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enum samsung_pll_type {
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pll_2126,
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pll_3000,
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pll_35xx,
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pll_36xx,
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pll_2550,
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