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ARM: dts: r8a7742: Add VSP support
Add VSP support to R8A7742 (RZ/G1H) SoC dtsi. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200911080929.15058-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -1686,6 +1686,42 @@
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status = "disabled";
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};
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vsp@fe920000 {
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compatible = "renesas,vsp1";
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reg = <0 0xfe920000 0 0x8000>;
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interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 130>;
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power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
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resets = <&cpg 130>;
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};
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vsp@fe928000 {
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compatible = "renesas,vsp1";
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reg = <0 0xfe928000 0 0x8000>;
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interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 131>;
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power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
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resets = <&cpg 131>;
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};
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vsp@fe930000 {
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compatible = "renesas,vsp1";
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reg = <0 0xfe930000 0 0x8000>;
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interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 128>;
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power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
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resets = <&cpg 128>;
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};
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vsp@fe938000 {
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compatible = "renesas,vsp1";
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reg = <0 0xfe938000 0 0x8000>;
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interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 127>;
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power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
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resets = <&cpg 127>;
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};
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du: display@feb00000 {
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compatible = "renesas,du-r8a7742";
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reg = <0 0xfeb00000 0 0x70000>;
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