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octeontx2-af: Add PTP device id for CN10K and 95O silcons

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CN10K slicon has different device id for PTP device.
Hence this patch updates the driver with new id.
Though ptp driver being a separate driver AF manages
configuring PTP block by all PFs. To manage ptp, AF
driver checks in its probe whether
1. ptp hardware device found on silicon
2. A driver is bound to ptp device
3. The ptp driver probe is successful

In failure of cases 1 and 3, AF proceeds with out ptp
and for case 2 defers the probe. This patch refactors
code also to check for all the PTP device ids given in
ptp device ids table for case 1.

Also added PTP device ID for 95O silicon

Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Subbaraya Sundeep 2021-08-25 17:48:44 +05:30 committed by David S. Miller
parent 275e5d175d
commit a8b90c9d26
1 changed files with 18 additions and 25 deletions
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43
drivers/net/ethernet/marvell/octeontx2/af/ptp.c
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@ -19,12 +19,11 @@
#define PCI_SUBSYS_DEVID_OCTX2_98xx_PTP 0xB100 #define PCI_SUBSYS_DEVID_OCTX2_98xx_PTP 0xB100
#define PCI_SUBSYS_DEVID_OCTX2_96XX_PTP 0xB200 #define PCI_SUBSYS_DEVID_OCTX2_96XX_PTP 0xB200
#define PCI_SUBSYS_DEVID_OCTX2_95XX_PTP 0xB300 #define PCI_SUBSYS_DEVID_OCTX2_95XX_PTP 0xB300
#define PCI_SUBSYS_DEVID_OCTX2_LOKI_PTP 0xB400 #define PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP 0xB400
#define PCI_SUBSYS_DEVID_OCTX2_95MM_PTP 0xB500 #define PCI_SUBSYS_DEVID_OCTX2_95MM_PTP 0xB500
#define PCI_SUBSYS_DEVID_CN10K_A_PTP 0xB900 #define PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP 0xB600
#define PCI_SUBSYS_DEVID_CNF10K_A_PTP 0xBA00
#define PCI_SUBSYS_DEVID_CNF10K_B_PTP 0xBC00
#define PCI_DEVID_OCTEONTX2_RST 0xA085 #define PCI_DEVID_OCTEONTX2_RST 0xA085
#define PCI_DEVID_CN10K_PTP 0xA09E
#define PCI_PTP_BAR_NO 0 #define PCI_PTP_BAR_NO 0
#define PCI_RST_BAR_NO 0 #define PCI_RST_BAR_NO 0
@ -39,6 +38,9 @@
#define RST_MUL_BITS GENMASK_ULL(38, 33) #define RST_MUL_BITS GENMASK_ULL(38, 33)
#define CLOCK_BASE_RATE 50000000ULL #define CLOCK_BASE_RATE 50000000ULL
static struct ptp *first_ptp_block;
static const struct pci_device_id ptp_id_table[];
static u64 get_clock_rate(void) static u64 get_clock_rate(void)
{ {
u64 cfg, ret = CLOCK_BASE_RATE * 16; u64 cfg, ret = CLOCK_BASE_RATE * 16;
@ -74,23 +76,14 @@ error:
struct ptp *ptp_get(void) struct ptp *ptp_get(void)
{ {
struct pci_dev *pdev; struct ptp *ptp = first_ptp_block;
struct ptp *ptp;
/* If the PTP pci device is found on the system and ptp /* Check PTP block is present in hardware */
* driver is bound to it then the PTP pci device is returned if (!pci_dev_present(ptp_id_table))
* to the caller(rvu driver).
*/
pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
PCI_DEVID_OCTEONTX2_PTP, NULL);
if (!pdev)
return ERR_PTR(-ENODEV); return ERR_PTR(-ENODEV);
/* Check driver is bound to PTP block */
ptp = pci_get_drvdata(pdev);
if (!ptp) if (!ptp)
ptp = ERR_PTR(-EPROBE_DEFER); ptp = ERR_PTR(-EPROBE_DEFER);
if (IS_ERR(ptp))
pci_dev_put(pdev);
return ptp; return ptp;
} }
@ -190,6 +183,8 @@ static int ptp_probe(struct pci_dev *pdev,
writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP); writeq(clock_comp, ptp->reg_base + PTP_CLOCK_COMP);
pci_set_drvdata(pdev, ptp); pci_set_drvdata(pdev, ptp);
if (!first_ptp_block)
first_ptp_block = ptp;
return 0; return 0;
@ -204,6 +199,9 @@ error:
* `dev->driver_data`. * `dev->driver_data`.
*/ */
pci_set_drvdata(pdev, ERR_PTR(err)); pci_set_drvdata(pdev, ERR_PTR(err));
if (!first_ptp_block)
first_ptp_block = ERR_PTR(err);
return 0; return 0;
} }
@ -233,19 +231,14 @@ static const struct pci_device_id ptp_id_table[] = {
PCI_SUBSYS_DEVID_OCTX2_95XX_PTP) }, PCI_SUBSYS_DEVID_OCTX2_95XX_PTP) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
PCI_VENDOR_ID_CAVIUM, PCI_VENDOR_ID_CAVIUM,
PCI_SUBSYS_DEVID_OCTX2_LOKI_PTP) }, PCI_SUBSYS_DEVID_OCTX2_95XXN_PTP) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
PCI_VENDOR_ID_CAVIUM, PCI_VENDOR_ID_CAVIUM,
PCI_SUBSYS_DEVID_OCTX2_95MM_PTP) }, PCI_SUBSYS_DEVID_OCTX2_95MM_PTP) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
PCI_VENDOR_ID_CAVIUM, PCI_VENDOR_ID_CAVIUM,
PCI_SUBSYS_DEVID_CN10K_A_PTP) }, PCI_SUBSYS_DEVID_OCTX2_95XXO_PTP) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP, { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_PTP) },
PCI_VENDOR_ID_CAVIUM,
PCI_SUBSYS_DEVID_CNF10K_A_PTP) },
{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_PTP,
PCI_VENDOR_ID_CAVIUM,
PCI_SUBSYS_DEVID_CNF10K_B_PTP) },
{ 0, } { 0, }
}; };