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Staging: rtl8192su: remove EEPROM_OLD_FORMAT_SUPPORT ifdefs

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Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Bartlomiej Zolnierkiewicz 2009-07-03 16:06:33 +02:00 committed by Greg Kroah-Hartman
parent ee13be2f94
commit a7e3c1d621
5 changed files with 0 additions and 236 deletions
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2
drivers/staging/rtl8192su/Makefile
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@ -12,8 +12,6 @@ EXTRA_CFLAGS += -DRTL8190_Download_Firmware_From_Header=1
EXTRA_CFLAGS += -DRTL8192S_PREPARE_FOR_NORMAL_RELEASE
EXTRA_CFLAGS += -DRTL8192SU_DISABLE_IQK=1
#EXTRA_CFLAGS += -DEEPROM_OLD_FORMAT_SUPPORT
#EXTRA_CFLAGS += -DUSB_RX_AGGREGATION_SUPPORT=0
#EXTRA_CFLAGS += -DUSB_TX_DRIVER_AGGREGATION_ENABLE=0
#EXTRA_CFLAGS += -DRTL8192SU_DISABLE_CCK_RATE=0

26
drivers/staging/rtl8192su/r8192S_hw.h
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@ -1282,17 +1282,11 @@ Default: 00b.
#define EEPROM_Default_TxPower 0x1010
#define EEPROM_Default_HT2T_TxPwr 0x10
#ifdef EEPROM_OLD_FORMAT_SUPPORT
#define EEPROM_Default_TxPowerBase 0x0
#define EEPROM_Default_ThermalMeter 0x12
#define EEPROM_Default_PwDiff 0x4
#else
#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
#define EEPROM_Default_ThermalMeter 0x12
#define EEPROM_Default_AntTxPowerDiff 0x0
#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
#define EEPROM_Default_TxPowerLevel 0x22
#endif
#define EEPROM_CHANNEL_PLAN_FCC 0x0
#define EEPROM_CHANNEL_PLAN_IC 0x1
@ -1330,25 +1324,6 @@ Default: 00b.
// <Roger_Notes> The followin are for different version of EEPROM contents purpose. 2008.11.22.
#ifdef EEPROM_OLD_FORMAT_SUPPORT
#define EEPROM_PwDiff 0x54 // Difference of gain index between legacy and high throughput OFDM.
#define EEPROM_ThermalMeter 0x55 // Thermal meter default value.
#define EEPROM_Reserved 0x56 // Reserved.
#define EEPROM_CrystalCap 0x57 // Crystal Cap.
#define EEPROM_TxPowerBase 0x58 // Tx Power of serving station.
#define EEPROM_TxPwIndex_CCK_24G 0x59 // 0x59~0x66
#define EEPROM_TxPwIndex_OFDM_24G 0x67 // 0x67~0x74
#define EEPROM_TSSI_A 0x75 //TSSI value of path A.
#define EEPROM_TSSI_B 0x76 //TSSI value of path B.
#define EEPROM_TxPwTkMode 0x77 //Tx Power tracking mode.
#define EEPROM_HT2T_CH1_A 0x78 //HT 2T path A channel 1 Power Index.
#define EEPROM_HT2T_CH7_A 0x79 //HT 2T path A channel 7 Power Index.
#define EEPROM_HT2T_CH13_A 0x7a //HT 2T path A channel 13 Power Index.
#define EEPROM_HT2T_CH1_B 0x7b //HT 2T path B channel 1 Power Index.
#define EEPROM_HT2T_CH7_B 0x7c //HT 2T path B channel 7 Power Index.
#define EEPROM_HT2T_CH13_B 0x7d //HT 2T path B channel 13 Power Index.
#define EEPROM_BoardType 0x7e //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU
#else
#define EEPROM_BoardType 0x54 //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU
#define EEPROM_TxPwIndex 0x55 //0x55-0x66, Tx Power index.
#define EEPROM_PwDiff 0x67 // Difference of gain index between legacy and high throughput OFDM.
@ -1366,7 +1341,6 @@ Default: 00b.
#define EEPROM_TX_PWR_OFDM_DIFF 0x71// OFDM Tx Power Index Difference
#define EEPROM_TX_PWR_BAND_EDGE 0x73// TX Power offset at band-edge channel
#define TX_PWR_BAND_EDGE_CHK 0x79// Check if band-edge scheme is enabled
#endif
#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
#define EEPROM_USB_Default_OPTIONAL_FUNC 0x8
#define EEPROM_USB_Default_PHY_PARAM 0x0

5
drivers/staging/rtl8192su/r8192S_phy.c
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@ -2639,10 +2639,6 @@ PHY_GetTxPowerLevel8192S(
//
// if(priv->epromtype == EPROM_93c46)
{
#ifdef EEPROM_OLD_FORMAT_SUPPORT
powerlevel = priv->TxPowerLevelCCK[index];
powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[index];
#else
//
// Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx
// Power must be calculated by the antenna diff.
@ -2821,7 +2817,6 @@ PHY_GetTxPowerLevel8192S(
// Notify Tx power difference for B/C/D to A!!!
rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
#endif
}
//

6
drivers/staging/rtl8192su/r8192U.h
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@ -1662,11 +1662,6 @@ typedef struct r8192_priv
bool bDmDisableProtect;
bool bIgnoreDiffRateTxPowerOffset;
#ifdef EEPROM_OLD_FORMAT_SUPPORT
u8 EEPROMTxPowerLevelCCK24G[14]; // CCK 2.4G channel 1~14
//u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
//u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
#else
// For EEPROM TX Power Index like 8190 series
u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
@ -1678,7 +1673,6 @@ typedef struct r8192_priv
u8 RfCckChnlAreaTxPwr[2][3];
u8 RfOfdmChnlAreaTxPwr1T[2][3];
u8 RfOfdmChnlAreaTxPwr2T[2][3];
#endif
// Add For EEPROM Efuse switch and Efuse Shadow map Setting
bool EepromOrEfuse;

197
drivers/staging/rtl8192su/r8192U_core.c
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@ -5056,26 +5056,6 @@ rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(struct net_device* dev)
priv->EEPROMTxPwrTkMode = EEPROM_Default_TxPwrTkMode;
#ifdef EEPROM_OLD_FORMAT_SUPPORT
for(i=0; i<6; i++)
{
priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr;
}
for(i=0; i<14; i++)
{
priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
}
//
// Update HAL variables.
//
memcpy( priv->TxPowerLevelOFDM24G, priv->EEPROMTxPowerLevelOFDM24G, 14);
memcpy( priv->TxPowerLevelCCK, priv->EEPROMTxPowerLevelCCK24G, 14);
//RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("HAL CCK 2.4G TxPwr: \n"), priv->TxPowerLevelCCK, 14);
//RT_PRINT_DATA(COMP_INIT|COMP_EFUSE, DBG_LOUD, ("HAL OFDM 2.4G TxPwr: \n"), priv->TxPowerLevelOFDM24G, 14);
#else
for (rf_path = 0; rf_path < 2; rf_path++)
{
@ -5125,7 +5105,6 @@ rtl8192SU_ConfigAdapterInfo8192SForAutoLoadFail(struct net_device* dev)
//priv->RfTxPwrLevelOfdm1T[0][i] ,
//priv->RfTxPwrLevelOfdm2T[0][i] );
}
#endif
//
// Update remained HAL variables.
@ -5349,50 +5328,8 @@ static void rtl8192SU_ReadAdapterInfo8192SEEPROM(struct net_device* dev)
RT_TRACE(COMP_INIT, "BoardType = %#x\n", priv->EEPROMBoardType);
#ifdef EEPROM_OLD_FORMAT_SUPPORT
//
// Buffer TxPwIdx(i.e., from offset 0x58~0x75, total 30Bytes)
//
if(bLoad_From_EEPOM)
{
for(i = 0; i < 30; i += 2)
{
tmpValue = eprom_read(dev, (u16) ((EEPROM_TxPowerBase+i)>>1));
*((u16 *)(&tmpBuffer[i])) = tmpValue;
}
}
//
// Update CCK, OFDM Tx Power Index from above buffer.
//
if(bLoad_From_EEPOM)
{
for(i=0; i<14; i++)
{
priv->EEPROMTxPowerLevelCCK24G[i] = (u8)tmpBuffer[i+1];
priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)tmpBuffer[i+15];
}
}
else
{
for(i=0; i<14; i++)
{
priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
}
}
for(i=0; i<14; i++)
{
RT_TRACE(COMP_INIT, "CCK 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelCCK24G[i]);
RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, priv->EEPROMTxPowerLevelOFDM24G[i]);
}
#else
// Please add code in the section!!!!
// And merge tx power difference section.
#endif
//
// Get TSSI value for each path.
@ -5422,47 +5359,10 @@ static void rtl8192SU_ReadAdapterInfo8192SEEPROM(struct net_device* dev)
RT_TRACE(COMP_INIT, "TSSI_A = %#x, TSSI_B = %#x\n", priv->EEPROMTSSI_A, priv->EEPROMTSSI_B);
RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
#ifdef EEPROM_OLD_FORMAT_SUPPORT
//
// Get HT 2T Path A and B Power Index.
//
if(bLoad_From_EEPOM)
{
for(i = 0; i < 6; i += 2)
{
tmpValue = eprom_read(dev, (u16) ((EEPROM_HT2T_CH1_A+i)>>1));
*((u16*)(&priv->EEPROMHT2T_TxPwr[i])) = tmpValue;
}
}
else
{ // Default setting for Empty EEPROM
for(i=0; i<6; i++)
{
priv->EEPROMHT2T_TxPwr[i] = EEPROM_Default_HT2T_TxPwr;
}
}
for(i=0; i<6; i++)
{
RT_TRACE(COMP_INIT, "EEPROMHT2T_TxPwr, Index %d = 0x%02x\n", i, priv->EEPROMHT2T_TxPwr[i]);
}
#else
#endif
}
#ifdef EEPROM_OLD_FORMAT_SUPPORT
//
// Update HAL variables.
//
for(i=0; i<14; i++)
{
priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i];
priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK24G[i];
}
#else
#endif
priv->TxPowerDiff = priv->EEPROMPwDiff;
// Antenna B gain offset to antenna A, bit0~3
priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
@ -5750,47 +5650,8 @@ rtl8192SU_ReadAdapterInfo8192SEFuse(struct net_device* dev)
//if(pHalData->EEPROM_Def_Ver == 0)
{
#ifdef EEPROM_OLD_FORMAT_SUPPORT
//
// Get CCK Tx Power Index.
//
if(!priv->AutoloadFailFlag)
{
ReadEFuse(dev, EEPROM_TxPwIndex_CCK_24G, 14, (unsigned char*)CCKTxPwr);
for(i=0; i<14; i++)
{
RT_TRACE(COMP_INIT, "CCK 2.4G Tx Power Level, Index %d = 0x%02x\n", i, CCKTxPwr[i]);
priv->EEPROMTxPowerLevelCCK24G[i] = CCKTxPwr[i];
}
}
else
{ // Default setting for Empty EEPROM
for(i=0; i<14; i++)
priv->EEPROMTxPowerLevelCCK24G[i] = (u8)(EEPROM_Default_TxPower & 0xff);
}
//
// Get OFDM Tx Power Index.
//
if(!priv->AutoloadFailFlag)
{
ReadEFuse(dev, EEPROM_TxPwIndex_OFDM_24G, 14, (unsigned char*)OFDMTxPwr);
for(i=0; i<14; i++)
{
RT_TRACE(COMP_INIT, "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n", i, OFDMTxPwr[i]);
priv->EEPROMTxPowerLevelOFDM24G[i] = OFDMTxPwr[i];
}
}
else
{ // Default setting for Empty EEPROM
usValue = 0x10;
for(i=0; i<14; i++)
priv->EEPROMTxPowerLevelOFDM24G[i] = (u8)usValue;
}
#else
// Please add code in the section!!!!
// And merge tx power difference section.
#endif
//
// Get TSSI value for each path.
@ -5853,18 +5714,7 @@ rtl8192SU_ReadAdapterInfo8192SEFuse(struct net_device* dev)
}
}
#ifdef EEPROM_OLD_FORMAT_SUPPORT
//
// Update HAL variables.
//
for(i=0; i<14; i++)
{
priv->TxPowerLevelOFDM24G[i] = priv->EEPROMTxPowerLevelOFDM24G[i];
priv->TxPowerLevelCCK[i] = priv->EEPROMTxPowerLevelCCK24G[i];
}
#else
#endif
priv->TxPowerDiff = priv->EEPROMPwDiff;
// Antenna B gain offset to antenna A, bit0~3
priv->AntennaTxPwDiff[0] = (priv->EEPROMTxPowerDiff & 0xf);
@ -6254,52 +6104,6 @@ rtl8192SU_ReadAdapterInfo8192SUsb(struct net_device* dev)
RT_TRACE(COMP_INIT, "TxPwrTkMod = %#x\n", priv->EEPROMTxPwrTkMode);
#ifdef EEPROM_OLD_FORMAT_SUPPORT
//
// <Roger_Notes> The following settings are EFUSE version dependence.
// So we need to adjust reading offset.
// 2008.11.22.
//
{
//
// Get HT 2T Path A and B Power Index.
//
//if(!priv->AutoloadFailFlag)
{
for(i=0; i<6; i++)
{
priv->EEPROMHT2T_TxPwr[i] = *(u8 *)&hwinfo[EEPROM_HT2T_CH1_A+i];
}
}
//RT_PRINT_DATA(COMP_EFUSE, "HT2T TxPwr: \n"), pHalData->EEPROMHT2T_TxPwr, 6);
//
// Get CCK and OFDM Tx Power Index.
//
//if(!priv->AutoloadFailFlag)
{
for(i=0; i<14; i++)
{
priv->EEPROMTxPowerLevelCCK24G[i] = *(u8 *)&hwinfo[EEPROM_TxPwIndex_CCK_24G+i];
priv->EEPROMTxPowerLevelOFDM24G[i] = *(u8 *)&hwinfo[EEPROM_TxPwIndex_OFDM_24G+i];
}
}
//RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("CCK 2.4G TxPwr: \n"), pHalData->EEPROMTxPowerLevelCCK24G, 14);
//RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("OFDM 2.4G TxPwr: \n"), pHalData->EEPROMTxPowerLevelOFDM24G, 14);
//
// Update HAL variables.
//
memcpy( priv->TxPowerLevelOFDM24G, priv->EEPROMTxPowerLevelOFDM24G, 14);
memcpy( priv->TxPowerLevelCCK, priv->EEPROMTxPowerLevelCCK24G, 14);
//RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("HAL CCK 2.4G TxPwr: \n"), pHalData->TxPowerLevelCCK, 14);
//RT_PRINT_DATA(COMP_EFUSE, DBG_LOUD, ("HAL OFDM 2.4G TxPwr: \n"), pHalData->TxPowerLevelOFDM24G, 14);
}
#else // Support new version of EFUSE content, 2008.11.22.
{
//
// Buffer TxPwIdx(i.e., from offset 0x55~0x66, total 18Bytes)
@ -6467,7 +6271,6 @@ rtl8192SU_ReadAdapterInfo8192SUsb(struct net_device* dev)
priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][0],
priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_B][1]);
RT_TRACE((COMP_INIT&COMP_DBG), "Band-edge enable flag = %d\n", priv->TxPwrbandEdgeFlag);
#endif
//
// Update remained HAL variables.