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ARM/arm64: KVM: fix use of WnR bit in kvm_is_write_fault()
The ISS encoding for an exception from a Data Abort has a WnR bit[6] that indicates whether the Data Abort was caused by a read or a write instruction. While there are several fields in the encoding that are only valid if the ISV bit[24] is set, WnR is not one of them, so we can read it unconditionally. Instead of fixing both implementations of kvm_is_write_fault() in place, reimplement it just once using kvm_vcpu_dabt_iswrite(), which already does the right thing with respect to the WnR bit. Also fix up the callers to pass 'vcpu' Acked-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -78,17 +78,6 @@ static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
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flush_pmd_entry(pte);
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flush_pmd_entry(pte);
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}
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}
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static inline bool kvm_is_write_fault(unsigned long hsr)
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{
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unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;
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if (hsr_ec == HSR_EC_IABT)
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return false;
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else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR))
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return false;
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else
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return true;
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}
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static inline void kvm_clean_pgd(pgd_t *pgd)
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static inline void kvm_clean_pgd(pgd_t *pgd)
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{
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{
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clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
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clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
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@ -746,6 +746,14 @@ static bool transparent_hugepage_adjust(pfn_t *pfnp, phys_addr_t *ipap)
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return false;
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return false;
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}
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}
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static bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
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{
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if (kvm_vcpu_trap_is_iabt(vcpu))
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return false;
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return kvm_vcpu_dabt_iswrite(vcpu);
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}
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static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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struct kvm_memory_slot *memslot, unsigned long hva,
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struct kvm_memory_slot *memslot, unsigned long hva,
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unsigned long fault_status)
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unsigned long fault_status)
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@ -760,7 +768,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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pfn_t pfn;
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pfn_t pfn;
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pgprot_t mem_type = PAGE_S2;
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pgprot_t mem_type = PAGE_S2;
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write_fault = kvm_is_write_fault(kvm_vcpu_get_hsr(vcpu));
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write_fault = kvm_is_write_fault(vcpu);
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if (fault_status == FSC_PERM && !write_fault) {
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if (fault_status == FSC_PERM && !write_fault) {
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kvm_err("Unexpected L2 read permission error\n");
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kvm_err("Unexpected L2 read permission error\n");
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return -EFAULT;
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return -EFAULT;
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@ -886,7 +894,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
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gfn = fault_ipa >> PAGE_SHIFT;
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gfn = fault_ipa >> PAGE_SHIFT;
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memslot = gfn_to_memslot(vcpu->kvm, gfn);
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memslot = gfn_to_memslot(vcpu->kvm, gfn);
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hva = gfn_to_hva_memslot_prot(memslot, gfn, &writable);
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hva = gfn_to_hva_memslot_prot(memslot, gfn, &writable);
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write_fault = kvm_is_write_fault(kvm_vcpu_get_hsr(vcpu));
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write_fault = kvm_is_write_fault(vcpu);
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if (kvm_is_error_hva(hva) || (write_fault && !writable)) {
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if (kvm_is_error_hva(hva) || (write_fault && !writable)) {
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if (is_iabt) {
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if (is_iabt) {
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/* Prefetch Abort on I/O address */
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/* Prefetch Abort on I/O address */
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@ -93,19 +93,6 @@ void kvm_clear_hyp_idmap(void);
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#define kvm_set_pte(ptep, pte) set_pte(ptep, pte)
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#define kvm_set_pte(ptep, pte) set_pte(ptep, pte)
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#define kvm_set_pmd(pmdp, pmd) set_pmd(pmdp, pmd)
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#define kvm_set_pmd(pmdp, pmd) set_pmd(pmdp, pmd)
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static inline bool kvm_is_write_fault(unsigned long esr)
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{
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unsigned long esr_ec = esr >> ESR_EL2_EC_SHIFT;
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if (esr_ec == ESR_EL2_EC_IABT)
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return false;
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if ((esr & ESR_EL2_ISV) && !(esr & ESR_EL2_WNR))
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return false;
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return true;
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}
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static inline void kvm_clean_pgd(pgd_t *pgd) {}
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static inline void kvm_clean_pgd(pgd_t *pgd) {}
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static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
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static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
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static inline void kvm_clean_pte(pte_t *pte) {}
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static inline void kvm_clean_pte(pte_t *pte) {}
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