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net: dsa: bcm_sf2: Prepare for different register layouts
In preparation for supporting a new device with a slightly different register layout, affecting the SWITCH_REG and SWITCH_CORE address spaces, perform a few preparatory steps: - allow matching the compatible string against a data description - convert the SWITCH_REG register accesses into an indirection table - prepare for supporting a SWITCH_CORE register alignment requirement Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Florian Fainelli
David S. Miller
parent
329b5c58f8
commit
a78e86ed58
@ -1009,10 +1009,49 @@ static const struct dsa_switch_ops bcm_sf2_ops = {
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.port_fdb_del = b53_fdb_del,
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};
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struct bcm_sf2_of_data {
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u32 type;
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const u16 *reg_offsets;
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unsigned int core_reg_align;
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};
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/* Register offsets for the SWITCH_REG_* block */
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static const u16 bcm_sf2_7445_reg_offsets[] = {
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[REG_SWITCH_CNTRL] = 0x00,
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[REG_SWITCH_STATUS] = 0x04,
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[REG_DIR_DATA_WRITE] = 0x08,
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[REG_DIR_DATA_READ] = 0x0C,
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[REG_SWITCH_REVISION] = 0x18,
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[REG_PHY_REVISION] = 0x1C,
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[REG_SPHY_CNTRL] = 0x2C,
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[REG_RGMII_0_CNTRL] = 0x34,
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[REG_RGMII_1_CNTRL] = 0x40,
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[REG_RGMII_2_CNTRL] = 0x4c,
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[REG_LED_0_CNTRL] = 0x90,
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[REG_LED_1_CNTRL] = 0x94,
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[REG_LED_2_CNTRL] = 0x98,
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};
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static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
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.type = BCM7445_DEVICE_ID,
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.core_reg_align = 0,
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.reg_offsets = bcm_sf2_7445_reg_offsets,
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};
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static const struct of_device_id bcm_sf2_of_match[] = {
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{ .compatible = "brcm,bcm7445-switch-v4.0",
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.data = &bcm_sf2_7445_data
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},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
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static int bcm_sf2_sw_probe(struct platform_device *pdev)
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{
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const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
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struct device_node *dn = pdev->dev.of_node;
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const struct of_device_id *of_id = NULL;
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const struct bcm_sf2_of_data *data;
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struct b53_platform_data *pdata;
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struct dsa_switch_ops *ops;
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struct bcm_sf2_priv *priv;
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@ -1040,11 +1079,22 @@ static int bcm_sf2_sw_probe(struct platform_device *pdev)
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if (!pdata)
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return -ENOMEM;
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of_id = of_match_node(bcm_sf2_of_match, dn);
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if (!of_id || !of_id->data)
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return -EINVAL;
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data = of_id->data;
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/* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
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priv->type = data->type;
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priv->reg_offsets = data->reg_offsets;
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priv->core_reg_align = data->core_reg_align;
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/* Auto-detection using standard registers will not work, so
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* provide an indication of what kind of device we are for
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* b53_common to work with
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*/
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pdata->chip_id = BCM7445_DEVICE_ID;
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pdata->chip_id = priv->type;
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dev->pdata = pdata;
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priv->dev = dev;
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@ -1190,11 +1240,6 @@ static int bcm_sf2_resume(struct device *dev)
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static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
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bcm_sf2_suspend, bcm_sf2_resume);
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static const struct of_device_id bcm_sf2_of_match[] = {
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{ .compatible = "brcm,bcm7445-switch-v4.0" },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
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static struct platform_driver bcm_sf2_driver = {
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.probe = bcm_sf2_sw_probe,
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@ -61,6 +61,11 @@ struct bcm_sf2_priv {
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void __iomem *fcb;
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void __iomem *acb;
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/* Register offsets indirection tables */
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u32 type;
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const u16 *reg_offsets;
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unsigned int core_reg_align;
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/* spinlock protecting access to the indirect registers */
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spinlock_t indir_lock;
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@ -104,6 +109,11 @@ static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds)
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return dev->priv;
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}
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static inline u32 bcm_sf2_mangle_addr(struct bcm_sf2_priv *priv, u32 off)
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{
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return off << priv->core_reg_align;
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}
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#define SF2_IO_MACRO(name) \
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static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
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{ \
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@ -153,8 +163,28 @@ static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
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priv->irq##which##_mask |= (mask); \
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} \
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SF2_IO_MACRO(core);
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SF2_IO_MACRO(reg);
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static inline u32 core_readl(struct bcm_sf2_priv *priv, u32 off)
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{
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u32 tmp = bcm_sf2_mangle_addr(priv, off);
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return __raw_readl(priv->core + tmp);
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}
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static inline void core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off)
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{
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u32 tmp = bcm_sf2_mangle_addr(priv, off);
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__raw_writel(val, priv->core + tmp);
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}
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static inline u32 reg_readl(struct bcm_sf2_priv *priv, u16 off)
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{
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return __raw_readl(priv->reg + priv->reg_offsets[off]);
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}
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static inline void reg_writel(struct bcm_sf2_priv *priv, u32 val, u16 off)
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{
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__raw_writel(val, priv->reg + priv->reg_offsets[off]);
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}
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SF2_IO64_MACRO(core);
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SF2_IO_MACRO(intrl2_0);
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SF2_IO_MACRO(intrl2_1);
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@ -12,22 +12,36 @@
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#define __BCM_SF2_REGS_H
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/* Register set relative to 'REG' */
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#define REG_SWITCH_CNTRL 0x00
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enum bcm_sf2_reg_offs {
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REG_SWITCH_CNTRL = 0,
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REG_SWITCH_STATUS,
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REG_DIR_DATA_WRITE,
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REG_DIR_DATA_READ,
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REG_SWITCH_REVISION,
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REG_PHY_REVISION,
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REG_SPHY_CNTRL,
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REG_RGMII_0_CNTRL,
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REG_RGMII_1_CNTRL,
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REG_RGMII_2_CNTRL,
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REG_LED_0_CNTRL,
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REG_LED_1_CNTRL,
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REG_LED_2_CNTRL,
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REG_SWITCH_REG_MAX,
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};
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/* Relative to REG_SWITCH_CNTRL */
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#define MDIO_MASTER_SEL (1 << 0)
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#define REG_SWITCH_STATUS 0x04
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#define REG_DIR_DATA_WRITE 0x08
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#define REG_DIR_DATA_READ 0x0C
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#define REG_SWITCH_REVISION 0x18
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/* Relative to REG_SWITCH_REVISION */
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#define SF2_REV_MASK 0xffff
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#define SWITCH_TOP_REV_SHIFT 16
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#define SWITCH_TOP_REV_MASK 0xffff
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#define REG_PHY_REVISION 0x1C
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/* Relative to REG_PHY_REVISION */
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#define PHY_REVISION_MASK 0xffff
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#define REG_SPHY_CNTRL 0x2C
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/* Relative to REG_SPHY_CNTRL */
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#define IDDQ_BIAS (1 << 0)
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#define EXT_PWR_DOWN (1 << 1)
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#define FORCE_DLL_EN (1 << 2)
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@ -37,13 +51,8 @@
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#define PHY_PHYAD_SHIFT 8
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#define PHY_PHYAD_MASK 0x1F
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#define REG_RGMII_0_BASE 0x34
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#define REG_RGMII_CNTRL 0x00
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#define REG_RGMII_IB_STATUS 0x04
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#define REG_RGMII_RX_CLOCK_DELAY_CNTRL 0x08
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#define REG_RGMII_CNTRL_SIZE 0x0C
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#define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_BASE + \
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((x) * REG_RGMII_CNTRL_SIZE))
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#define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x))
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/* Relative to REG_RGMII_CNTRL */
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#define RGMII_MODE_EN (1 << 0)
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#define ID_MODE_DIS (1 << 1)
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@ -61,8 +70,8 @@
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#define LPI_COUNT_SHIFT 9
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#define LPI_COUNT_MASK 0x3F
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#define REG_LED_CNTRL_BASE 0x90
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#define REG_LED_CNTRL(x) (REG_LED_CNTRL_BASE + (x) * 4)
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#define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x))
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#define SPDLNK_SRC_SEL (1 << 24)
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/* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
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