renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2025-01-16 09:34:22 +08:00
Code

media: omap3isp: add CSI1 support

Browse Source 
CSI-2 PHY power management is only needed for major version 15 of the ISP.
Additionally, set the CCP2 PHY for previous ISP versions as well.

These changes are necessary for CCP2 support.

Signed-off-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
Pavel Machek 2017-07-13 06:36:59 -04:00 committed by Mauro Carvalho Chehab
parent 3a738c3fd8
commit a6b687df8a
2 changed files with 13 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/media/platform/omap3isp/ispccp2.c
View File

@ -1141,6 +1141,7 @@ int omap3isp_ccp2_init(struct isp_device *isp)
"Could not get regulator vdds_csib\n");
ccp2->vdds_csib = NULL;
}
ccp2->phy = &isp->isp_csiphy2;
} else if (isp->revision == ISP_REVISION_15_0) {
ccp2->phy = &isp->isp_csiphy1;
}

19
drivers/media/platform/omap3isp/ispcsiphy.c
View File

@ -292,13 +292,16 @@ int omap3isp_csiphy_acquire(struct isp_csiphy *phy)
if (rval < 0)
goto done;
rval = csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_ON);
if (rval) {
regulator_disable(phy->vdd);
goto done;
if (phy->isp->revision == ISP_REVISION_15_0) {
rval = csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_ON);
if (rval) {
regulator_disable(phy->vdd);
goto done;
}
csiphy_power_autoswitch_enable(phy, true);
}
csiphy_power_autoswitch_enable(phy, true);
phy->phy_in_use = 1;
done:
@ -317,8 +320,10 @@ void omap3isp_csiphy_release(struct isp_csiphy *phy)
csiphy_routing_cfg(phy, buscfg->interface, false,
buscfg->bus.ccp2.phy_layer);
csiphy_power_autoswitch_enable(phy, false);
csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_OFF);
if (phy->isp->revision == ISP_REVISION_15_0) {
csiphy_power_autoswitch_enable(phy, false);
csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_OFF);
}
regulator_disable(phy->vdd);
phy->phy_in_use = 0;
}