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Staging: sxg: Add Rev B support in the Sahara SXG driver
This patch makes the Sahara SXG driver use Rev B firmware instead of Rev A. The firmware version is 1.71 Signed-off-by: Michael Miles <mmiles@alacritech.com> Signed-off-by: Mithlesh Thukral <mithlesh@linsyssoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mithlesh Thukral
Greg Kroah-Hartman
parent
497ef3c5f1
commit
a536efcc76
@ -81,14 +81,14 @@
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#include "sxg.h"
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#include "sxgdbg.h"
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#include "sxgphycode.h"
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#include "sxgphycode-1.2.h"
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#define SXG_UCODE_DBG 0 /* Turn on for debugging */
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#ifdef SXG_UCODE_DBG
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#include "saharadbgdownload.c"
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#include "saharadbgdownloadB.c"
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#include "saharadbgdownload-1.71.c"
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#include "saharadbgdownloadB-1.10.c"
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#else
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#include "saharadownload.c"
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#include "saharadownloadB.c"
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#include "saharadownload-1.55.c"
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#include "saharadownloadB-1.8.c"
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#endif
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static int sxg_allocate_buffer_memory(struct adapter_t *adapter, u32 Size,
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@ -410,22 +410,42 @@ static bool sxg_download_microcode(struct adapter_t *adapter,
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DBG_ERROR("sxg: %s ENTER\n", __func__);
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switch (UcodeSel) {
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case SXG_UCODE_SAHARA: /* Sahara operational ucode */
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numSections = SNumSections;
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for (i = 0; i < numSections; i++) {
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sectionSize[i] = SSectionSize[i];
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sectionStart[i] = SSectionStart[i];
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}
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break;
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default:
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printk(KERN_ERR KBUILD_MODNAME
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": Woah, big error with the microcode!\n");
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break;
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case SXG_UCODE_SYSTEM: // System (operational) ucode
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switch (adapter->asictype) {
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case SAHARA_REV_A:
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DBG_ERROR("%s SAHARA CARD REVISION A\n",
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__func__);
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numSections = SNumSections;
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for (i = 0; i < numSections; i++) {
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sectionSize[i] =
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SSectionSize[i];
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sectionStart[i] =
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SSectionStart[i];
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}
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break;
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case SAHARA_REV_B:
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DBG_ERROR("%s SAHARA CARD REVISION B\n",
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__func__);
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numSections = SBNumSections;
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for (i = 0; i < numSections; i++) {
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sectionSize[i] =
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SBSectionSize[i];
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sectionStart[i] =
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SBSectionStart[i];
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}
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break;
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}
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break;
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default:
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printk(KERN_ERR KBUILD_MODNAME
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": Woah, big error with the microcode!\n");
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break;
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}
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DBG_ERROR("sxg: RESET THE CARD\n");
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/* First, reset the card */
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WRITE_REG(HwRegs->Reset, 0xDEAD, FLUSH);
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udelay(50);
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/*
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* Download each section of the microcode as specified in
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@ -436,13 +456,21 @@ static bool sxg_download_microcode(struct adapter_t *adapter,
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for (Section = 0; Section < numSections; Section++) {
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DBG_ERROR("sxg: SECTION # %d\n", Section);
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switch (UcodeSel) {
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case SXG_UCODE_SAHARA:
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Instruction = (u32 *) & SaharaUCode[Section][0];
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case SXG_UCODE_SYSTEM:
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switch (adapter->asictype) {
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case SAHARA_REV_A:
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Instruction = (u32 *) & SaharaUCode[Section][0];
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break;
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case SAHARA_REV_B:
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Instruction = (u32 *) & SaharaUCodeB[Section][0];
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break;
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}
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break;
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default:
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ASSERT(0);
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break;
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}
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BaseAddress = sectionStart[Section];
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/* Size in instructions */
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ThisSectionSize = sectionSize[Section] / 12;
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@ -481,12 +509,21 @@ static bool sxg_download_microcode(struct adapter_t *adapter,
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for (Section = 0; Section < numSections; Section++) {
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DBG_ERROR("sxg: check SECTION # %d\n", Section);
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switch (UcodeSel) {
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case SXG_UCODE_SAHARA:
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Instruction = (u32 *) & SaharaUCode[Section][0];
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break;
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default:
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ASSERT(0);
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break;
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case SXG_UCODE_SYSTEM:
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switch (adapter->asictype) {
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case SAHARA_REV_A:
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Instruction = (u32 *) &
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SaharaUCode[Section][0];
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break;
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case SAHARA_REV_B:
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Instruction = (u32 *) &
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SaharaUCodeB[Section][0];
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break;
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}
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break;
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default:
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ASSERT(0);
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break;
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}
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BaseAddress = sectionStart[Section];
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/* Size in instructions */
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@ -555,7 +592,7 @@ static bool sxg_download_microcode(struct adapter_t *adapter,
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* synchronize with the card so it can scribble on the memory
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* that contained 0xCAFE from the "CardUp" step above
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*/
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if (UcodeSel == SXG_UCODE_SAHARA) {
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if (UcodeSel == SXG_UCODE_SYSTEM) {
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WRITE_REG(adapter->UcodeRegs[0].LoadSync, 0, FLUSH);
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}
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@ -891,6 +928,7 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
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u32 status = 0;
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ulong mmio_start = 0;
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ulong mmio_len = 0;
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unsigned char revision_id;
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DBG_ERROR("sxg: %s 2.6 VERSION ENTER jiffies[%lx] cpu %d\n",
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__func__, jiffies, smp_processor_id());
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@ -915,6 +953,8 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
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printk(KERN_INFO "%s\n", SXG_DRV_VERSION);
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}
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pci_read_config_byte(pcidev, PCI_REVISION_ID, &revision_id);
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if (!(err = pci_set_dma_mask(pcidev, DMA_64BIT_MASK))) {
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DBG_ERROR("pci_set_dma_mask(DMA_64BIT_MASK) successful\n");
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} else {
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@ -950,6 +990,15 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
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pci_set_drvdata(pcidev, netdev);
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adapter = netdev_priv(netdev);
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if (revision_id == 1) {
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adapter->asictype = SAHARA_REV_A;
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} else if (revision_id == 2) {
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adapter->asictype = SAHARA_REV_B;
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} else {
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ASSERT(0);
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DBG_ERROR("%s Unexpected revision ID %x\n", __FUNCTION__, revision_id);
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goto err_out_exit_sxg_probe;
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}
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adapter->netdev = netdev;
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adapter->pcidev = pcidev;
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@ -1054,7 +1103,7 @@ static int sxg_entry_probe(struct pci_dev *pcidev,
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}
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DBG_ERROR("sxg: %s ENTER sxg_download_microcode\n", __func__);
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if (sxg_download_microcode(adapter, SXG_UCODE_SAHARA)) {
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if (sxg_download_microcode(adapter, SXG_UCODE_SYSTEM)) {
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DBG_ERROR("sxg: %s ENTER sxg_adapter_set_hwaddr\n",
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__func__);
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sxg_read_config(adapter);
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@ -1762,9 +1811,6 @@ static struct sk_buff *sxg_slow_receive(struct adapter_t *adapter,
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if (Event->Status & EVENT_STATUS_RCVERR) {
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SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RcvError",
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Event, Event->Status, Event->HostHandle, 0);
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/* XXXTODO - Remove this print later */
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DBG_ERROR("SXG: Receive error %x\n", *(u32 *)
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SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr));
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sxg_process_rcv_error(adapter, *(u32 *)
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SXG_RECEIVE_DATA_LOCATION
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(RcvDataBufferHdr));
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@ -2144,7 +2190,7 @@ static int sxg_entry_open(struct net_device *dev)
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* The microcode expects it to be downloaded on every open.
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*/
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DBG_ERROR("sxg: %s ENTER sxg_download_microcode\n", __FUNCTION__);
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if (sxg_download_microcode(adapter, SXG_UCODE_SAHARA)) {
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if (sxg_download_microcode(adapter, SXG_UCODE_SYSTEM)) {
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DBG_ERROR("sxg: %s ENTER sxg_adapter_set_hwaddr\n",
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__FUNCTION__);
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sxg_read_config(adapter);
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@ -2639,7 +2685,8 @@ static int sxg_dumb_sgl(struct sxg_x64_sgl *pSgl,
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* the start of the next 64k boundary and continue
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*/
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if (SXG_INVALID_SGL(phys_addr,skb->data_len))
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if ((adapter->asictype == SAHARA_REV_A) &&
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(SXG_INVALID_SGL(phys_addr,skb->data_len)))
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{
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spin_unlock_irqrestore(&adapter->XmtZeroLock, flags);
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/* Silently drop this packet */
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@ -2725,6 +2772,7 @@ static int sxg_initialize_link(struct adapter_t *adapter)
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u32 Value;
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u32 ConfigData;
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u32 MaxFrame;
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u32 AxgMacReg1;
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int status;
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SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "InitLink",
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@ -2771,24 +2819,27 @@ static int sxg_initialize_link(struct adapter_t *adapter)
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WRITE_REG(HwRegs->MacConfig0, 0, TRUE);
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/* Configure MAC */
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WRITE_REG(HwRegs->MacConfig1, (
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/* Allow sending of pause */
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AXGMAC_CFG1_XMT_PAUSE |
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/* Enable XMT */
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AXGMAC_CFG1_XMT_EN |
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/* Enable detection of pause */
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AXGMAC_CFG1_RCV_PAUSE |
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/* Enable receive */
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AXGMAC_CFG1_RCV_EN |
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/* short frame detection */
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AXGMAC_CFG1_SHORT_ASSERT |
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/* Verify frame length */
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AXGMAC_CFG1_CHECK_LEN |
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/* Generate FCS */
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AXGMAC_CFG1_GEN_FCS |
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/* Pad frames to 64 bytes */
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AXGMAC_CFG1_PAD_64),
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TRUE);
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AxgMacReg1 = ( /* Enable XMT */
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AXGMAC_CFG1_XMT_EN |
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/* Enable receive */
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AXGMAC_CFG1_RCV_EN |
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/* short frame detection */
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AXGMAC_CFG1_SHORT_ASSERT |
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/* Verify frame length */
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AXGMAC_CFG1_CHECK_LEN |
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/* Generate FCS */
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AXGMAC_CFG1_GEN_FCS |
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/* Pad frames to 64 bytes */
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AXGMAC_CFG1_PAD_64);
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if (adapter->XmtFcEnabled) {
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AxgMacReg1 |= AXGMAC_CFG1_XMT_PAUSE; /* Allow sending of pause */
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}
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if (adapter->RcvFcEnabled) {
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AxgMacReg1 |= AXGMAC_CFG1_RCV_PAUSE; /* Enable detection of pause */
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}
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WRITE_REG(HwRegs->MacConfig1, AxgMacReg1, TRUE);
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/* Set AXGMAC max frame length if jumbo. Not needed for standard MTU */
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if (adapter->JumboEnabled) {
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@ -2806,13 +2857,20 @@ static int sxg_initialize_link(struct adapter_t *adapter)
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* This value happens to be the default value for this register, so we
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* really don't have to do this.
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*/
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WRITE_REG(HwRegs->MacAmiimConfig, 0x0000003E, TRUE);
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if (adapter->asictype == SAHARA_REV_B) {
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WRITE_REG(HwRegs->MacAmiimConfig, 0x0000001F, TRUE);
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} else {
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WRITE_REG(HwRegs->MacAmiimConfig, 0x0000003E, TRUE);
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}
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/* Power up and enable PHY and XAUI/XGXS/Serdes logic */
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WRITE_REG(HwRegs->LinkStatus,
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(LS_PHY_CLR_RESET |
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LS_XGXS_ENABLE |
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LS_XGXS_CTL | LS_PHY_CLK_EN | LS_ATTN_ALARM), TRUE);
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(LS_PHY_CLR_RESET |
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LS_XGXS_ENABLE |
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LS_XGXS_CTL |
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LS_PHY_CLK_EN |
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LS_ATTN_ALARM),
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TRUE);
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DBG_ERROR("After Power Up and enable PHY in sxg_initialize_link\n");
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/*
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@ -2886,6 +2944,11 @@ static int sxg_initialize_link(struct adapter_t *adapter)
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RCV_CONFIG_TZIPV4 |
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RCV_CONFIG_HASH_16 |
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RCV_CONFIG_SOCKET | RCV_CONFIG_BUFSIZE(MaxFrame));
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if (adapter->asictype == SAHARA_REV_B) {
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ConfigData |= (RCV_CONFIG_HIPRICTL |
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RCV_CONFIG_NEWSTATUSFMT);
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}
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WRITE_REG(HwRegs->RcvConfig, ConfigData, TRUE);
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WRITE_REG(HwRegs->XmtConfig, XMT_CONFIG_ENABLE, TRUE);
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@ -2994,7 +3057,16 @@ static void sxg_link_event(struct adapter_t *adapter)
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sxg_link_state(adapter, SXG_LINK_DOWN);
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/* ASSERT(0); */
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}
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ASSERT(Value & LASI_STATUS_LS_ALARM);
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/*
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* We used to assert that the LASI_LS_ALARM bit was set, as
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* it should be. But there appears to be cases during
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* initialization (when the PHY is reset and re-initialized)
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* when we get a link alarm, but the status bit is 0 when we
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* read it. Rather than trying to assure this never happens
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* (and nver being certain), just ignore it.
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* ASSERT(Value & LASI_STATUS_LS_ALARM);
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*/
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/* Now get and set the link state */
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LinkState = sxg_get_link_state(adapter);
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@ -4118,6 +4190,9 @@ static int sxg_initialize_adapter(struct adapter_t *adapter)
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*/
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adapter->Dead = FALSE;
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adapter->PingOutstanding = FALSE;
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adapter->XmtFcEnabled = TRUE;
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adapter->RcvFcEnabled = TRUE;
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adapter->State = SXG_STATE_RUNNING;
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SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "XInit",
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@ -369,9 +369,9 @@ enum SXG_LINK_STATE {
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/* Microcode file selection codes */
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enum SXG_UCODE_SEL {
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SXG_UCODE_SAHARA, /* Sahara ucode */
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SXG_UCODE_SDIAGCPU, /* Sahara CPU diagnostic ucode */
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SXG_UCODE_SDIAGSYS /* Sahara system diagnostic ucode */
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SXG_UCODE_SYSTEM, /* System (operational) uucode */
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SXG_UCODE_SDIAGCPU, /* System CPU diagnostic ucode */
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SXG_UCODE_SDIAGSYS /* System diagnostic ucode */
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};
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@ -537,6 +537,7 @@ struct adapter_t {
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u32 memorylength;
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u32 drambase;
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u32 dramlength;
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enum asic_type asictype; /* type of ASIC (chip) */
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unsigned int activated;
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u32 intrregistered;
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unsigned int isp_initialized;
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@ -680,6 +681,8 @@ struct adapter_t {
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u32 RssEnabled:1; /* RSS Enabled */
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u32 FailOnBadEeprom:1; /* Fail on Bad Eeprom */
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u32 DiagStart:1; /* Init adapter for diagnostic start */
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u32 XmtFcEnabled:1;
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u32 RcvFcEnabled:1;
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/* Stats */
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u32 PendingRcvCount; /* Outstanding rcv indications */
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u32 PendingXmtCount; /* Outstanding send requests */
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@ -150,13 +150,16 @@ struct sxg_ucode_regs {
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/* Disable interrupt aggregation on xmt */
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#define SXG_AGG_XMT_DISABLE 0x80000000
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/* The Microcode supports up to 8 RSS queues */
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#define SXG_MAX_RSS 8
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/* The Microcode supports up to 16 RSS queues (RevB) */
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#define SXG_MAX_RSS 16
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#define SXG_MAX_RSS_REVA 8
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#define SXG_MAX_RSS_TABLE_SIZE 256 /* 256-byte max */
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#define SXG_RSS_TCP6 0x00000001 /* RSS TCP over IPv6 */
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#define SXG_RSS_TCP4 0x00000002 /* RSS TCP over IPv4 */
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#define SXG_RSS_REVA_TCP6 0x00000001 /* RSS TCP over IPv6 */
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#define SXG_RSS_REVA_TCP4 0x00000002 /* RSS TCP over IPv4 */
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#define SXG_RSS_IP 0x00000001 /* RSS TCP over IPv6 */
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#define SXG_RSS_TCP 0x00000002 /* RSS TCP over IPv4 */
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#define SXG_RSS_LEGACY 0x00000004 /* Line-base interrupts */
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#define SXG_RSS_TABLE_SIZE 0x0000FF00 /* Table size mask */
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@ -18,6 +18,22 @@
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/* PCI Device ID */
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#define SXG_DEVICE_ID 0x0009 /* Sahara Device ID */
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/* Type of ASIC in use */
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enum asic_type {
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SAHARA_REV_A,
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SAHARA_REV_B
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};
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/* Type of Xcvr in fiber card */
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enum xcvr_type {
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XCVR_UNKNOWN,
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XCVR_NONE,
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XCVR_SR,
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XCVR_LR,
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XCVR_LRM,
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XCVR_CR
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};
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/*
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* Subsystem IDs.
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*
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@ -265,9 +281,11 @@ struct sxg_hw_regs {
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#define RCV_CONFIG_HASH_4 0x00020000 /* Hash depth 4 */
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#define RCV_CONFIG_HASH_2 0x00030000 /* Hash depth 2 */
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/* Buffer length bits 15:4. ie multiple of 16. */
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#define RCV_CONFIG_BUFLEN_MASK 0x0000FFF0
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#define RCV_CONFIG_BUFLEN_MASK 0x0000FFE0
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/* Disable socket detection on attn */
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#define RCV_CONFIG_SKT_DIS 0x00000008
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#define RCV_CONFIG_HIPRICTL 0x00000002 /* Ctrl frames on high-prioirty RcvQ */
|
||||
#define RCV_CONFIG_NEWSTATUSFMT 0x00000001 /* Use RevB status format */
|
||||
/*
|
||||
* Macro to determine RCV_CONFIG_BUFLEN based on maximum frame size.
|
||||
* We add 18 bytes for Sahara receive status and padding, plus 4 bytes for CRC,
|
||||
@ -640,6 +658,9 @@ struct sxg_hw_regs {
|
||||
/* PHY_XS_LANE_STATUS register bit definitions */
|
||||
#define XS_LANE_ALIGN 0x1000 /* XS transmit lanes aligned */
|
||||
|
||||
#define XCVR_VENDOR_LEN 16 /* xcvr vendor len */
|
||||
#define XCVR_MODEL_LEN 16 /* xcvr model len */
|
||||
|
||||
/* PHY Microcode download data structure */
|
||||
struct phy_ucode {
|
||||
ushort Addr;
|
||||
@ -970,6 +991,10 @@ struct adapt_userinfo {
|
||||
/* u32 LinkState; */
|
||||
u32 LinkSpeed; /* not currently needed */
|
||||
u32 LinkDuplex; /* not currently needed */
|
||||
enum xcvr_type XcvrType; /* type of xcvr on fiber card */
|
||||
/* fiber card xcvr vendor */
|
||||
unsigned char XcvrVendor[XCVR_VENDOR_LEN];
|
||||
unsigned char XcvrMode[XCVR_MODEL_LEN];
|
||||
u32 Port; /* not currently needed */
|
||||
u32 PhysPort; /* not currently needed */
|
||||
ushort PciLanes;
|
||||
@ -984,11 +1009,7 @@ struct adapt_userinfo {
|
||||
|
||||
/* Miscellaneous Hardware definitions */
|
||||
|
||||
/* Type of ASIC in use */
|
||||
enum ASIC_TYPE{
|
||||
SAHARA_REV_A,
|
||||
SAHARA_REV_B
|
||||
};
|
||||
/* Hardware Type definitions */
|
||||
|
||||
/* Sahara (ASIC level) defines */
|
||||
#define SAHARA_GRAM_SIZE 0x020000 /* GRAM size - 128 KB */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user