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https://github.com/edk2-porting/linux-next.git
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IIO: Ingenic JZ47xx: Add support for JZ4770 SoC ADC.
Add support for the ADC hardware present on Ingenic JZ4770 SoC. Signed-off-by: Artur Rojek <contact@artur-rojek.eu> Tested-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
parent
b23bf21f55
commit
a515d64885
@ -25,9 +25,13 @@
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#define JZ_ADC_REG_ADSDAT 0x20
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#define JZ_ADC_REG_ADSDAT 0x20
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#define JZ_ADC_REG_ADCLK 0x28
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#define JZ_ADC_REG_ADCLK 0x28
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#define JZ_ADC_REG_ENABLE_PD BIT(7)
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#define JZ_ADC_REG_CFG_AUX_MD (BIT(0) | BIT(1))
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#define JZ_ADC_REG_CFG_BAT_MD BIT(4)
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#define JZ_ADC_REG_CFG_BAT_MD BIT(4)
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#define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0
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#define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0
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#define JZ_ADC_REG_ADCLK_CLKDIV10US_LSB 16
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#define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB 16
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#define JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB 8
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#define JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB 16
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#define JZ_ADC_AUX_VREF 3300
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#define JZ_ADC_AUX_VREF 3300
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#define JZ_ADC_AUX_VREF_BITS 12
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#define JZ_ADC_AUX_VREF_BITS 12
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@ -37,6 +41,8 @@
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#define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS 10
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#define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS 10
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#define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986)
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#define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986)
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#define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12
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#define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12
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#define JZ4770_ADC_BATTERY_VREF 6600
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#define JZ4770_ADC_BATTERY_VREF_BITS 12
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struct ingenic_adc;
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struct ingenic_adc;
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@ -47,6 +53,8 @@ struct ingenic_adc_soc_data {
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size_t battery_raw_avail_size;
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size_t battery_raw_avail_size;
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const int *battery_scale_avail;
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const int *battery_scale_avail;
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size_t battery_scale_avail_size;
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size_t battery_scale_avail_size;
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unsigned int battery_vref_mode: 1;
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unsigned int has_aux2: 1;
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int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
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int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
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};
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};
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@ -54,6 +62,7 @@ struct ingenic_adc {
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void __iomem *base;
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void __iomem *base;
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struct clk *clk;
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struct clk *clk;
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struct mutex lock;
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struct mutex lock;
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struct mutex aux_lock;
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const struct ingenic_adc_soc_data *soc_data;
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const struct ingenic_adc_soc_data *soc_data;
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bool low_vref_mode;
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bool low_vref_mode;
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};
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};
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@ -120,6 +129,8 @@ static int ingenic_adc_write_raw(struct iio_dev *iio_dev,
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case IIO_CHAN_INFO_SCALE:
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case IIO_CHAN_INFO_SCALE:
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switch (chan->channel) {
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switch (chan->channel) {
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case INGENIC_ADC_BATTERY:
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case INGENIC_ADC_BATTERY:
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if (!adc->soc_data->battery_vref_mode)
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return -EINVAL;
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if (val > JZ_ADC_BATTERY_LOW_VREF) {
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if (val > JZ_ADC_BATTERY_LOW_VREF) {
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ingenic_adc_set_config(adc,
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ingenic_adc_set_config(adc,
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JZ_ADC_REG_CFG_BAT_MD,
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JZ_ADC_REG_CFG_BAT_MD,
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@ -158,6 +169,14 @@ static const int jz4740_adc_battery_scale_avail[] = {
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JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
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JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
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};
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};
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static const int jz4770_adc_battery_raw_avail[] = {
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0, 1, (1 << JZ4770_ADC_BATTERY_VREF_BITS) - 1,
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};
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static const int jz4770_adc_battery_scale_avail[] = {
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JZ4770_ADC_BATTERY_VREF, JZ4770_ADC_BATTERY_VREF_BITS,
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};
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static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
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static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
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{
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{
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struct clk *parent_clk;
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struct clk *parent_clk;
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@ -187,7 +206,45 @@ static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
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/* We also need a divider that produces a 10us clock. */
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/* We also need a divider that produces a 10us clock. */
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div_10us = DIV_ROUND_UP(rate, 100000);
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div_10us = DIV_ROUND_UP(rate, 100000);
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writel(((div_10us - 1) << JZ_ADC_REG_ADCLK_CLKDIV10US_LSB) |
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writel(((div_10us - 1) << JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB) |
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(div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
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adc->base + JZ_ADC_REG_ADCLK);
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return 0;
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}
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static int jz4770_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
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{
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struct clk *parent_clk;
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unsigned long parent_rate, rate;
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unsigned int div_main, div_ms, div_10us;
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parent_clk = clk_get_parent(adc->clk);
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if (!parent_clk) {
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dev_err(dev, "ADC clock has no parent\n");
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return -ENODEV;
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}
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parent_rate = clk_get_rate(parent_clk);
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/*
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* The JZ4770 ADC works at 20 kHz to 200 kHz.
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* We pick the highest rate possible.
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*/
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div_main = DIV_ROUND_UP(parent_rate, 200000);
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div_main = clamp(div_main, 1u, 256u);
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rate = parent_rate / div_main;
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if (rate < 20000 || rate > 200000) {
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dev_err(dev, "No valid divider for ADC main clock\n");
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return -EINVAL;
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}
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/* We also need a divider that produces a 10us clock. */
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div_10us = DIV_ROUND_UP(rate, 10000);
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/* And another, which produces a 1ms clock. */
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div_ms = DIV_ROUND_UP(rate, 1000);
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writel(((div_ms - 1) << JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB) |
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((div_10us - 1) << JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB) |
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(div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
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(div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
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adc->base + JZ_ADC_REG_ADCLK);
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adc->base + JZ_ADC_REG_ADCLK);
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@ -201,6 +258,8 @@ static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {
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.battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
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.battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
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.battery_scale_avail = jz4725b_adc_battery_scale_avail,
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.battery_scale_avail = jz4725b_adc_battery_scale_avail,
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.battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
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.battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
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.battery_vref_mode = true,
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.has_aux2 = false,
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.init_clk_div = jz4725b_adc_init_clk_div,
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.init_clk_div = jz4725b_adc_init_clk_div,
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};
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};
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@ -211,9 +270,23 @@ static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
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.battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
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.battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
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.battery_scale_avail = jz4740_adc_battery_scale_avail,
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.battery_scale_avail = jz4740_adc_battery_scale_avail,
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.battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
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.battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
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.battery_vref_mode = true,
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.has_aux2 = false,
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.init_clk_div = NULL, /* no ADCLK register on JZ4740 */
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.init_clk_div = NULL, /* no ADCLK register on JZ4740 */
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};
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};
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static const struct ingenic_adc_soc_data jz4770_adc_soc_data = {
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.battery_high_vref = JZ4770_ADC_BATTERY_VREF,
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.battery_high_vref_bits = JZ4770_ADC_BATTERY_VREF_BITS,
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.battery_raw_avail = jz4770_adc_battery_raw_avail,
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.battery_raw_avail_size = ARRAY_SIZE(jz4770_adc_battery_raw_avail),
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.battery_scale_avail = jz4770_adc_battery_scale_avail,
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.battery_scale_avail_size = ARRAY_SIZE(jz4770_adc_battery_scale_avail),
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.battery_vref_mode = false,
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.has_aux2 = true,
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.init_clk_div = jz4770_adc_init_clk_div,
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};
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static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
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static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
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struct iio_chan_spec const *chan,
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struct iio_chan_spec const *chan,
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const int **vals,
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const int **vals,
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@ -239,6 +312,42 @@ static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
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};
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};
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}
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}
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static int ingenic_adc_read_chan_info_raw(struct ingenic_adc *adc,
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struct iio_chan_spec const *chan,
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int *val)
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{
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int bit, ret, engine = (chan->channel == INGENIC_ADC_BATTERY);
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/* We cannot sample AUX/AUX2 in parallel. */
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mutex_lock(&adc->aux_lock);
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if (adc->soc_data->has_aux2 && engine == 0) {
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bit = BIT(chan->channel == INGENIC_ADC_AUX2);
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ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_AUX_MD, bit);
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}
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clk_enable(adc->clk);
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ret = ingenic_adc_capture(adc, engine);
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if (ret)
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goto out;
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switch (chan->channel) {
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case INGENIC_ADC_AUX:
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case INGENIC_ADC_AUX2:
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*val = readw(adc->base + JZ_ADC_REG_ADSDAT);
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break;
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case INGENIC_ADC_BATTERY:
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*val = readw(adc->base + JZ_ADC_REG_ADBDAT);
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break;
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}
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ret = IIO_VAL_INT;
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out:
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clk_disable(adc->clk);
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mutex_unlock(&adc->aux_lock);
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return ret;
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}
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static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
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static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
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struct iio_chan_spec const *chan,
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struct iio_chan_spec const *chan,
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int *val,
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int *val,
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@ -246,32 +355,14 @@ static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
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long m)
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long m)
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{
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{
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struct ingenic_adc *adc = iio_priv(iio_dev);
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struct ingenic_adc *adc = iio_priv(iio_dev);
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int ret;
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switch (m) {
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switch (m) {
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case IIO_CHAN_INFO_RAW:
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case IIO_CHAN_INFO_RAW:
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clk_enable(adc->clk);
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return ingenic_adc_read_chan_info_raw(adc, chan, val);
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ret = ingenic_adc_capture(adc, chan->channel);
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if (ret) {
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clk_disable(adc->clk);
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return ret;
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}
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switch (chan->channel) {
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case INGENIC_ADC_AUX:
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*val = readw(adc->base + JZ_ADC_REG_ADSDAT);
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break;
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case INGENIC_ADC_BATTERY:
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*val = readw(adc->base + JZ_ADC_REG_ADBDAT);
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break;
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}
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clk_disable(adc->clk);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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case IIO_CHAN_INFO_SCALE:
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switch (chan->channel) {
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switch (chan->channel) {
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case INGENIC_ADC_AUX:
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case INGENIC_ADC_AUX:
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case INGENIC_ADC_AUX2:
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*val = JZ_ADC_AUX_VREF;
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*val = JZ_ADC_AUX_VREF;
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*val2 = JZ_ADC_AUX_VREF_BITS;
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*val2 = JZ_ADC_AUX_VREF_BITS;
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break;
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break;
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@ -322,6 +413,14 @@ static const struct iio_chan_spec ingenic_channels[] = {
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.indexed = 1,
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.indexed = 1,
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.channel = INGENIC_ADC_BATTERY,
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.channel = INGENIC_ADC_BATTERY,
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},
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},
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{ /* Must always be last in the array. */
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.extend_name = "aux2",
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.type = IIO_VOLTAGE,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_SCALE),
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.indexed = 1,
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.channel = INGENIC_ADC_AUX2,
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},
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};
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};
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static int ingenic_adc_probe(struct platform_device *pdev)
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static int ingenic_adc_probe(struct platform_device *pdev)
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@ -343,6 +442,7 @@ static int ingenic_adc_probe(struct platform_device *pdev)
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adc = iio_priv(iio_dev);
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adc = iio_priv(iio_dev);
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mutex_init(&adc->lock);
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mutex_init(&adc->lock);
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mutex_init(&adc->aux_lock);
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adc->soc_data = soc_data;
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adc->soc_data = soc_data;
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mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -374,6 +474,7 @@ static int ingenic_adc_probe(struct platform_device *pdev)
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/* Put hardware in a known passive state. */
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/* Put hardware in a known passive state. */
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writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);
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writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);
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writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
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writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
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usleep_range(2000, 3000); /* Must wait at least 2ms. */
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clk_disable(adc->clk);
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clk_disable(adc->clk);
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ret = devm_add_action_or_reset(dev, ingenic_adc_clk_cleanup, adc->clk);
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ret = devm_add_action_or_reset(dev, ingenic_adc_clk_cleanup, adc->clk);
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@ -387,6 +488,9 @@ static int ingenic_adc_probe(struct platform_device *pdev)
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iio_dev->modes = INDIO_DIRECT_MODE;
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iio_dev->modes = INDIO_DIRECT_MODE;
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iio_dev->channels = ingenic_channels;
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iio_dev->channels = ingenic_channels;
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iio_dev->num_channels = ARRAY_SIZE(ingenic_channels);
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iio_dev->num_channels = ARRAY_SIZE(ingenic_channels);
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/* Remove AUX2 from the list of supported channels. */
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if (!adc->soc_data->has_aux2)
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iio_dev->num_channels -= 1;
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iio_dev->info = &ingenic_adc_info;
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iio_dev->info = &ingenic_adc_info;
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ret = devm_iio_device_register(dev, iio_dev);
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ret = devm_iio_device_register(dev, iio_dev);
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@ -400,6 +504,7 @@ static int ingenic_adc_probe(struct platform_device *pdev)
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static const struct of_device_id ingenic_adc_of_match[] = {
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static const struct of_device_id ingenic_adc_of_match[] = {
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{ .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, },
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{ .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, },
|
||||||
{ .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, },
|
{ .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, },
|
||||||
|
{ .compatible = "ingenic,jz4770-adc", .data = &jz4770_adc_soc_data, },
|
||||||
{ },
|
{ },
|
||||||
};
|
};
|
||||||
MODULE_DEVICE_TABLE(of, ingenic_adc_of_match);
|
MODULE_DEVICE_TABLE(of, ingenic_adc_of_match);
|
||||||
|
Loading…
Reference in New Issue
Block a user