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firewire: add CSR PRIORITY_BUDGET support
If supported by the OHCI controller, implement the PRIORITY_BUDGET register, which is required for nodes that can use asynchronous priority arbitration. To allow the core to determine what features the lowlevel device supports, add a new card driver callback. Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
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@ -1126,6 +1126,20 @@ static void handle_registers(struct fw_card *card, struct fw_request *request,
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rcode = RCODE_TYPE_ERROR;
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break;
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case CSR_PRIORITY_BUDGET:
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if (!(card->driver->get_features(card) &
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FEATURE_PRIORITY_BUDGET))
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rcode = RCODE_ADDRESS_ERROR;
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else if (tcode == TCODE_READ_QUADLET_REQUEST)
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*data = cpu_to_be32(card->driver->
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read_csr_reg(card, CSR_PRIORITY_BUDGET));
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else if (tcode == TCODE_WRITE_QUADLET_REQUEST)
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card->driver->write_csr_reg(card, CSR_PRIORITY_BUDGET,
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be32_to_cpu(*data));
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else
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rcode = RCODE_TYPE_ERROR;
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break;
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case CSR_BROADCAST_CHANNEL:
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if (tcode == TCODE_READ_QUADLET_REQUEST)
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*data = cpu_to_be32(card->broadcast_channel);
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@ -38,6 +38,8 @@ struct fw_packet;
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#define BROADCAST_CHANNEL_INITIAL (1 << 31 | 31)
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#define BROADCAST_CHANNEL_VALID (1 << 30)
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#define FEATURE_PRIORITY_BUDGET 0x01
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struct fw_card_driver {
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/*
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* Enable the given card with the given initial config rom.
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@ -78,6 +80,8 @@ struct fw_card_driver {
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u32 (*read_csr_reg)(struct fw_card *card, int csr_offset);
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void (*write_csr_reg)(struct fw_card *card, int csr_offset, u32 value);
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unsigned int (*get_features)(struct fw_card *card);
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struct fw_iso_context *
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(*allocate_iso_context)(struct fw_card *card,
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int type, int channel, size_t header_size);
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@ -170,6 +170,7 @@ struct fw_ohci {
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int generation;
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int request_generation; /* for timestamping incoming requests */
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unsigned quirks;
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unsigned int pri_req_max;
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u32 bus_time;
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/*
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@ -1738,6 +1739,11 @@ static int ohci_enable(struct fw_card *card,
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reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
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ohci->bus_time = seconds & ~0x3f;
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/* Get implemented bits of the priority arbitration request counter. */
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reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
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ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
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reg_write(ohci, OHCI1394_FairnessControl, 0);
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ar_context_run(&ohci->ar_request_ctx);
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ar_context_run(&ohci->ar_response_ctx);
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@ -2028,6 +2034,10 @@ static u32 ohci_read_csr_reg(struct fw_card *card, int csr_offset)
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value = reg_read(ohci, OHCI1394_ATRetries);
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return (value >> 4) & 0x0ffff00f;
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case CSR_PRIORITY_BUDGET:
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return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
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(ohci->pri_req_max << 8);
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default:
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WARN_ON(1);
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return 0;
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@ -2065,12 +2075,28 @@ static void ohci_write_csr_reg(struct fw_card *card, int csr_offset, u32 value)
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flush_writes(ohci);
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break;
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case CSR_PRIORITY_BUDGET:
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reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
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flush_writes(ohci);
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break;
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default:
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WARN_ON(1);
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break;
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}
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}
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static unsigned int ohci_get_features(struct fw_card *card)
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{
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struct fw_ohci *ohci = fw_ohci(card);
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unsigned int features = 0;
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if (ohci->pri_req_max != 0)
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features |= FEATURE_PRIORITY_BUDGET;
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return features;
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}
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static void copy_iso_headers(struct iso_context *ctx, void *p)
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{
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int i = ctx->header_length;
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@ -2510,6 +2536,7 @@ static const struct fw_card_driver ohci_driver = {
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.enable_phys_dma = ohci_enable_phys_dma,
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.read_csr_reg = ohci_read_csr_reg,
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.write_csr_reg = ohci_write_csr_reg,
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.get_features = ohci_get_features,
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.allocate_iso_context = ohci_allocate_iso_context,
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.free_iso_context = ohci_free_iso_context,
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@ -32,6 +32,7 @@
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#define CSR_CYCLE_TIME 0x200
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#define CSR_BUS_TIME 0x204
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#define CSR_BUSY_TIMEOUT 0x210
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#define CSR_PRIORITY_BUDGET 0x218
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#define CSR_BUS_MANAGER_ID 0x21c
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#define CSR_BANDWIDTH_AVAILABLE 0x220
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#define CSR_CHANNELS_AVAILABLE 0x224
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