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m68knommu: create bit definitions for the version 2 ColdFire cache controller

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The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer 2010-11-09 10:12:29 +10:00
parent 63e83c8a52
commit a12cf0a8c6
8 changed files with 72 additions and 0 deletions
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2
arch/m68k/include/asm/m5206sim.h
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@ -15,6 +15,8 @@
#define CPU_NAME "COLDFIRE(m5206)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 5206 SIM register set addresses.
*/

5
arch/m68k/include/asm/m520xsim.h
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@ -14,6 +14,8 @@
#define CPU_NAME "COLDFIRE(m520x)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 520x SIM register set addresses.
*/
@ -57,6 +59,9 @@
#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
/*
* EPORT and GPIO registers.
*/
#define MCFEPORT_EPDDR 0xFC088002
#define MCFEPORT_EPDR 0xFC088004
#define MCFEPORT_EPPDR 0xFC088005

2
arch/m68k/include/asm/m523xsim.h
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@ -14,6 +14,8 @@
#define CPU_NAME "COLDFIRE(m523x)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 523x SIM register set addresses.
*/

2
arch/m68k/include/asm/m5249sim.h
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@ -14,6 +14,8 @@
#define CPU_NAME "COLDFIRE(m5249)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 5249 SIM register set addresses.
*/

2
arch/m68k/include/asm/m5272sim.h
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@ -15,6 +15,8 @@
#define CPU_NAME "COLDFIRE(m5272)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 5272 SIM register set addresses.
*/

1
arch/m68k/include/asm/m527xsim.h
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@ -14,6 +14,7 @@
#define CPU_NAME "COLDFIRE(m527x)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 5270/5271 SIM register set addresses.

2
arch/m68k/include/asm/m528xsim.h
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@ -14,6 +14,8 @@
#define CPU_NAME "COLDFIRE(m528x)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 5280/5282 SIM register set addresses.
*/

56
arch/m68k/include/asm/m52xxacr.h Normal file
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@ -0,0 +1,56 @@
/****************************************************************************/
/*
* m52xxacr.h -- ColdFire version 2 core cache support
*
* (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
*/
/****************************************************************************/
#ifndef m52xxacr_h
#define m52xxacr_h
/****************************************************************************/
/*
* All varients of the ColdFire using version 2 cores have a similar
* cache setup. Although not absolutely identical the cache register
* definitions are compatible for all of them. Mostly they support a
* configurable cache memory that can be instruction only, data only,
* or split instruction and data. The exception is the very old version 2
* core based parts, like the 5206(e), 5249 and 5272, which are instruction
* cache only. Cache size varies from 2k up to 16k.
*/
/*
* Define the Cache Control register flags.
*/
#define CACR_CENB 0x80000000 /* Enable cache */
#define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */
#define CACR_CFRZ 0x08000000 /* Cache freeze mode */
#define CACR_CINV 0x01000000 /* Invalidate cache */
#define CACR_DISI 0x00800000 /* Disable instruction cache */
#define CACR_DISD 0x00400000 /* Disable data cache */
#define CACR_INVI 0x00200000 /* Invalidate instruction cache */
#define CACR_INVD 0x00100000 /* Invalidate data cache */
#define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */
#define CACR_DCM 0x00000200 /* Default cache mode */
#define CACR_DBWE 0x00000100 /* Buffered write enable */
#define CACR_DWP 0x00000020 /* Write protection */
#define CACR_EUSP 0x00000010 /* Enable separate user a7 */
/*
* Define the Access Control register flags.
*/
#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
#define ACR_ENABLE 0x00008000 /* Enable this ACR */
#define ACR_USER 0x00000000 /* Allow only user accesses */
#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
#define ACR_ANY 0x00004000 /* Allow any access type */
#define ACR_CENB 0x00000000 /* Caching of region enabled */
#define ACR_CDIS 0x00000040 /* Caching of region disabled */
#define ACR_BWE 0x00000020 /* Write buffer enabled */
#define ACR_WPROTECT 0x00000004 /* Write protect region */
/****************************************************************************/
#endif /* m52xxsim_h */