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arm: pxa: Transition pxa27x to clk framework
Transition the PXA27x CPUs to the clock framework. This transition still enables legacy platforms to run without device tree as before, ie relying on platform data encoded in board specific files. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Robert Jarzmik
Mike Turquette
parent
85fe55c11a
commit
9ff25d7b58
@ -621,6 +621,7 @@ config ARCH_PXA
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select ARCH_REQUIRE_GPIOLIB
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select ARM_CPU_SUSPEND if PM
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select AUTO_ZRELADDR
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select COMMON_CLK if PXA27x
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select CLKSRC_OF
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@ -3,16 +3,15 @@
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#
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# Common support (must be linked before board specific support)
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obj-y += clock.o devices.o generic.o irq.o \
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reset.o
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obj-y += devices.o generic.o irq.o reset.o
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obj-$(CONFIG_PM) += pm.o sleep.o standby.o
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# Generic drivers that other drivers may depend upon
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# SoC-specific code
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obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o
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obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o
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obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
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obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock.o clock-pxa2xx.o pxa2xx.o pxa25x.o
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obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o
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obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
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obj-$(CONFIG_CPU_PXA300) += pxa300.o
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obj-$(CONFIG_CPU_PXA320) += pxa320.o
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obj-$(CONFIG_CPU_PXA930) += pxa930.o
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@ -37,7 +37,8 @@
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#include "generic.h"
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#include "devices.h"
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#include "clock.h"
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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void pxa27x_clear_otgph(void)
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{
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@ -73,174 +74,6 @@ void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
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}
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EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa27x_get_clk_frequency_khz(int info)
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{
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unsigned long ccsr, clkcfg;
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unsigned int l, L, m, M, n2, N, S;
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int cccr_a, t, ht, b;
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ccsr = CCSR;
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cccr_a = CCCR & (1 << 25);
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/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
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t = clkcfg & (1 << 0);
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ht = clkcfg & (1 << 2);
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b = clkcfg & (1 << 3);
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l = ccsr & 0x1f;
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n2 = (ccsr>>7) & 0xf;
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m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
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L = l * BASE_CLK;
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N = (L * n2) / 2;
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M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
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S = (b) ? L : (L/2);
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if (info) {
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printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
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L / 1000000, (L % 1000000) / 10000, l );
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printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
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N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
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(t) ? "" : "in" );
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printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
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M / 1000000, (M % 1000000) / 10000, m );
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printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
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S / 1000000, (S % 1000000) / 10000 );
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}
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return (t) ? (N/1000) : (L/1000);
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}
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/*
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* Return the current mem clock frequency as reflected by CCCR[A], B, and L
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*/
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static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
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{
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unsigned long ccsr, clkcfg;
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unsigned int l, L, m, M;
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int cccr_a, b;
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ccsr = CCSR;
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cccr_a = CCCR & (1 << 25);
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/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
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b = clkcfg & (1 << 3);
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l = ccsr & 0x1f;
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m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
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L = l * BASE_CLK;
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M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
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return M;
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}
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static const struct clkops clk_pxa27x_mem_ops = {
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.enable = clk_dummy_enable,
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.disable = clk_dummy_disable,
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.getrate = clk_pxa27x_mem_getrate,
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};
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/*
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* Return the current LCD clock frequency in units of 10kHz as
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*/
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static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
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{
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unsigned long ccsr;
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unsigned int l, L, k, K;
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ccsr = CCSR;
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l = ccsr & 0x1f;
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k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
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L = l * BASE_CLK;
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K = L / k;
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return (K / 10000);
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}
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static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
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{
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return pxa27x_get_lcdclk_frequency_10khz() * 10000;
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}
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static const struct clkops clk_pxa27x_lcd_ops = {
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.enable = clk_pxa2xx_cken_enable,
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.disable = clk_pxa2xx_cken_disable,
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.getrate = clk_pxa27x_lcd_getrate,
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};
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static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
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static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
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static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
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static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
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static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
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static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
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static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
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static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
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static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
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static struct clk_lookup pxa27x_clkregs[] = {
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INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
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INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
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INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
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INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
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INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
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INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
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INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
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INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
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INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
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INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
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INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
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INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
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INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
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INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
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INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
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INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
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INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
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INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
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INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
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INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
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INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
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INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
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INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
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INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
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INIT_CLKREG(&clk_dummy, "pxa27x-gpio", NULL),
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INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
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};
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#ifdef CONFIG_PM
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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@ -460,8 +293,6 @@ static int __init pxa27x_init(void)
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reset_status = RCSR;
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clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
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if ((ret = pxa_init_dma(IRQ_DMA, 32)))
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return ret;
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@ -469,10 +300,17 @@ static int __init pxa27x_init(void)
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register_syscore_ops(&pxa_irq_syscore_ops);
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register_syscore_ops(&pxa2xx_mfp_syscore_ops);
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register_syscore_ops(&pxa2xx_clock_syscore_ops);
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pxa_register_device(&pxa27x_device_gpio, &pxa27x_gpio_info);
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ret = platform_add_devices(devices, ARRAY_SIZE(devices));
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if (!of_have_populated_dt()) {
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ret = clk_register_clkdev(NULL, NULL,
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"pxa27x-gpio");
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if (!ret)
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pxa_register_device(&pxa27x_device_gpio,
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&pxa27x_gpio_info);
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if (!ret)
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ret = platform_add_devices(devices,
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ARRAY_SIZE(devices));
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}
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}
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return ret;
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