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KVM: PPC: BOOKE: allow debug interrupt at "debug level"
Debug interrupt can be either "critical level" or "debug level". There are separate set of save/restore registers used for different level. Example: DSRR0/DSRR1 are used for "debug level" and CSRR0/CSRR1 are used for critical level debug interrupt. Using CPU_FTR_DEBUG_LVL_EXC to decide which interrupt level to be used. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -377,7 +377,11 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
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allowed = vcpu->arch.shared->msr & MSR_DE;
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allowed = allowed && !crit;
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msr_mask = MSR_ME;
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int_class = INT_CLASS_CRIT;
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if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
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int_class = INT_CLASS_DBG;
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else
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int_class = INT_CLASS_CRIT;
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break;
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}
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