mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-21 11:44:01 +08:00
ARM: imx6q: move low-power code out of clock driver
The LPM (Low Power Mode) code that currently sits in imx6q clock driver will be reused by imx6sl. Let's move it into pm-imx6q.c, so that we can keep clock driver SoC specific and reuse pm-imx6q.c on imx6sl. In order to avoid adding another ioremap for CCM block, imx6q_pm_set_ccm_base() is created to let clock driver set up ccm_base for pm code. During the move, the unused CCGR macros get removed. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Shawn Guo
parent
803648db20
commit
9e8147bb5e
@ -14,7 +14,6 @@
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#include <linux/types.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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@ -25,155 +24,6 @@
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#include "common.h"
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#include "hardware.h"
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#define CCR 0x0
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#define BM_CCR_WB_COUNT (0x7 << 16)
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#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
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#define BM_CCR_RBC_EN (0x1 << 27)
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#define CCGR0 0x68
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#define CCGR1 0x6c
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#define CCGR2 0x70
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#define CCGR3 0x74
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#define CCGR4 0x78
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#define CCGR5 0x7c
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#define CCGR6 0x80
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#define CCGR7 0x84
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#define CLPCR 0x54
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#define BP_CLPCR_LPM 0
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#define BM_CLPCR_LPM (0x3 << 0)
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#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
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#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
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#define BM_CLPCR_SBYOS (0x1 << 6)
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#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
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#define BM_CLPCR_VSTBY (0x1 << 8)
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#define BP_CLPCR_STBY_COUNT 9
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#define BM_CLPCR_STBY_COUNT (0x3 << 9)
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#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
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#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
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#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
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#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
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#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
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#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
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#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
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#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
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#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
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#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
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#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
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#define CGPR 0x64
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#define BM_CGPR_CHICKEN_BIT (0x1 << 17)
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static void __iomem *ccm_base;
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void imx6q_set_chicken_bit(void)
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{
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u32 val = readl_relaxed(ccm_base + CGPR);
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val |= BM_CGPR_CHICKEN_BIT;
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writel_relaxed(val, ccm_base + CGPR);
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}
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static void imx6q_enable_rbc(bool enable)
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{
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u32 val;
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static bool last_rbc_mode;
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if (last_rbc_mode == enable)
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return;
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/*
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* need to mask all interrupts in GPC before
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* operating RBC configurations
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*/
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imx_gpc_mask_all();
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/* configure RBC enable bit */
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val = readl_relaxed(ccm_base + CCR);
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val &= ~BM_CCR_RBC_EN;
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val |= enable ? BM_CCR_RBC_EN : 0;
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writel_relaxed(val, ccm_base + CCR);
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/* configure RBC count */
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val = readl_relaxed(ccm_base + CCR);
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val &= ~BM_CCR_RBC_BYPASS_COUNT;
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val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
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writel(val, ccm_base + CCR);
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/*
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* need to delay at least 2 cycles of CKIL(32K)
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* due to hardware design requirement, which is
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* ~61us, here we use 65us for safe
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*/
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udelay(65);
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/* restore GPC interrupt mask settings */
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imx_gpc_restore_all();
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last_rbc_mode = enable;
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}
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static void imx6q_enable_wb(bool enable)
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{
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u32 val;
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static bool last_wb_mode;
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if (last_wb_mode == enable)
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return;
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/* configure well bias enable bit */
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val = readl_relaxed(ccm_base + CLPCR);
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val &= ~BM_CLPCR_WB_PER_AT_LPM;
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val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
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writel_relaxed(val, ccm_base + CLPCR);
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/* configure well bias count */
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val = readl_relaxed(ccm_base + CCR);
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val &= ~BM_CCR_WB_COUNT;
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val |= enable ? BM_CCR_WB_COUNT : 0;
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writel_relaxed(val, ccm_base + CCR);
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last_wb_mode = enable;
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}
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int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
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{
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u32 val = readl_relaxed(ccm_base + CLPCR);
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val &= ~BM_CLPCR_LPM;
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switch (mode) {
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case WAIT_CLOCKED:
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imx6q_enable_wb(false);
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imx6q_enable_rbc(false);
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break;
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case WAIT_UNCLOCKED:
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val |= 0x1 << BP_CLPCR_LPM;
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val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
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break;
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case STOP_POWER_ON:
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val |= 0x2 << BP_CLPCR_LPM;
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break;
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case WAIT_UNCLOCKED_POWER_OFF:
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val |= 0x1 << BP_CLPCR_LPM;
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val &= ~BM_CLPCR_VSTBY;
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val &= ~BM_CLPCR_SBYOS;
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break;
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case STOP_POWER_OFF:
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val |= 0x2 << BP_CLPCR_LPM;
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val |= 0x3 << BP_CLPCR_STBY_COUNT;
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val |= BM_CLPCR_VSTBY;
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val |= BM_CLPCR_SBYOS;
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imx6q_enable_wb(true);
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imx6q_enable_rbc(true);
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break;
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default:
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return -EINVAL;
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}
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writel_relaxed(val, ccm_base + CLPCR);
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return 0;
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}
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static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
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static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
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static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
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@ -384,7 +234,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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np = ccm_node;
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base = of_iomap(np, 0);
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WARN_ON(!base);
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ccm_base = base;
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imx6q_pm_set_ccm_base(base);
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/* name reg shift width parent_names num_parents */
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clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
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@ -627,9 +478,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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if (IS_ENABLED(CONFIG_PCI_IMX6))
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clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
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/* Set initial power mode */
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imx6q_set_lpm(WAIT_CLOCKED);
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
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base = of_iomap(np, 0);
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WARN_ON(!base);
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@ -147,9 +147,11 @@ int imx_cpu_kill(unsigned int cpu);
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#ifdef CONFIG_PM
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void imx6q_pm_init(void);
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void imx6q_pm_set_ccm_base(void __iomem *base);
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void imx5_pm_init(void);
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#else
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static inline void imx6q_pm_init(void) {}
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static inline void imx6q_pm_set_ccm_base(void __iomem *base) {}
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static inline void imx5_pm_init(void) {}
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#endif
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@ -10,9 +10,11 @@
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/suspend.h>
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#include <asm/cacheflush.h>
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#include <asm/proc-fns.h>
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@ -22,6 +24,146 @@
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#include "common.h"
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#include "hardware.h"
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#define CCR 0x0
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#define BM_CCR_WB_COUNT (0x7 << 16)
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#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
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#define BM_CCR_RBC_EN (0x1 << 27)
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#define CLPCR 0x54
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#define BP_CLPCR_LPM 0
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#define BM_CLPCR_LPM (0x3 << 0)
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#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
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#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
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#define BM_CLPCR_SBYOS (0x1 << 6)
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#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
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#define BM_CLPCR_VSTBY (0x1 << 8)
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#define BP_CLPCR_STBY_COUNT 9
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#define BM_CLPCR_STBY_COUNT (0x3 << 9)
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#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
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#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
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#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
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#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
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#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
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#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
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#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
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#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
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#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
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#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
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#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
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#define CGPR 0x64
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#define BM_CGPR_CHICKEN_BIT (0x1 << 17)
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static void __iomem *ccm_base;
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void imx6q_set_chicken_bit(void)
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{
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u32 val = readl_relaxed(ccm_base + CGPR);
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val |= BM_CGPR_CHICKEN_BIT;
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writel_relaxed(val, ccm_base + CGPR);
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}
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static void imx6q_enable_rbc(bool enable)
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{
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u32 val;
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static bool last_rbc_mode;
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if (last_rbc_mode == enable)
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return;
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/*
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* need to mask all interrupts in GPC before
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* operating RBC configurations
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*/
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imx_gpc_mask_all();
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/* configure RBC enable bit */
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val = readl_relaxed(ccm_base + CCR);
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val &= ~BM_CCR_RBC_EN;
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val |= enable ? BM_CCR_RBC_EN : 0;
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writel_relaxed(val, ccm_base + CCR);
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/* configure RBC count */
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val = readl_relaxed(ccm_base + CCR);
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val &= ~BM_CCR_RBC_BYPASS_COUNT;
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val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
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writel(val, ccm_base + CCR);
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/*
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* need to delay at least 2 cycles of CKIL(32K)
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* due to hardware design requirement, which is
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* ~61us, here we use 65us for safe
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*/
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udelay(65);
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/* restore GPC interrupt mask settings */
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imx_gpc_restore_all();
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last_rbc_mode = enable;
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}
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static void imx6q_enable_wb(bool enable)
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{
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u32 val;
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static bool last_wb_mode;
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if (last_wb_mode == enable)
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return;
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/* configure well bias enable bit */
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val = readl_relaxed(ccm_base + CLPCR);
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val &= ~BM_CLPCR_WB_PER_AT_LPM;
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val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
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writel_relaxed(val, ccm_base + CLPCR);
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/* configure well bias count */
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val = readl_relaxed(ccm_base + CCR);
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val &= ~BM_CCR_WB_COUNT;
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val |= enable ? BM_CCR_WB_COUNT : 0;
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writel_relaxed(val, ccm_base + CCR);
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last_wb_mode = enable;
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}
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int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
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{
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u32 val = readl_relaxed(ccm_base + CLPCR);
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val &= ~BM_CLPCR_LPM;
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switch (mode) {
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case WAIT_CLOCKED:
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imx6q_enable_wb(false);
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imx6q_enable_rbc(false);
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break;
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case WAIT_UNCLOCKED:
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val |= 0x1 << BP_CLPCR_LPM;
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val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
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break;
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case STOP_POWER_ON:
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val |= 0x2 << BP_CLPCR_LPM;
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break;
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case WAIT_UNCLOCKED_POWER_OFF:
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val |= 0x1 << BP_CLPCR_LPM;
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val &= ~BM_CLPCR_VSTBY;
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val &= ~BM_CLPCR_SBYOS;
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break;
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case STOP_POWER_OFF:
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val |= 0x2 << BP_CLPCR_LPM;
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val |= 0x3 << BP_CLPCR_STBY_COUNT;
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val |= BM_CLPCR_VSTBY;
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val |= BM_CLPCR_SBYOS;
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imx6q_enable_wb(true);
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imx6q_enable_rbc(true);
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break;
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default:
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return -EINVAL;
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}
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writel_relaxed(val, ccm_base + CLPCR);
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return 0;
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}
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static int imx6q_suspend_finish(unsigned long val)
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{
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cpu_do_idle();
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@ -55,7 +197,17 @@ static const struct platform_suspend_ops imx6q_pm_ops = {
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.valid = suspend_valid_only_mem,
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};
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void __init imx6q_pm_set_ccm_base(void __iomem *base)
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{
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ccm_base = base;
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}
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void __init imx6q_pm_init(void)
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{
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WARN_ON(!ccm_base);
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/* Set initial power mode */
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imx6q_set_lpm(WAIT_CLOCKED);
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suspend_set_ops(&imx6q_pm_ops);
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}
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