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Revert "parisc: Mark cr16 CPU clocksource unstable on all SMP machines"
This reverts commit afdb4a5b1d
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It triggers RCU stalls at boot with a 32-bit kernel.
Signed-off-by: Helge Deller <deller@gmx.de>
Noticed-by: John David Anglin <dave.anglin@bell.net>
Cc: stable@vger.kernel.org # v5.16+
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30c8e80f79
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9dc4241bb1
@ -251,16 +251,30 @@ void __init time_init(void)
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static int __init init_cr16_clocksource(void)
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{
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/*
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* The cr16 interval timers are not syncronized across CPUs, even if
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* they share the same socket.
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* The cr16 interval timers are not syncronized across CPUs on
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* different sockets, so mark them unstable and lower rating on
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* multi-socket SMP systems.
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*/
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if (num_online_cpus() > 1 && !running_on_qemu) {
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/* mark sched_clock unstable */
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clear_sched_clock_stable();
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int cpu;
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unsigned long cpu0_loc;
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cpu0_loc = per_cpu(cpu_data, 0).cpu_loc;
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clocksource_cr16.name = "cr16_unstable";
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clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
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clocksource_cr16.rating = 0;
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for_each_online_cpu(cpu) {
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if (cpu == 0)
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continue;
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if ((cpu0_loc != 0) &&
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(cpu0_loc == per_cpu(cpu_data, cpu).cpu_loc))
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continue;
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/* mark sched_clock unstable */
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clear_sched_clock_stable();
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clocksource_cr16.name = "cr16_unstable";
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clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
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clocksource_cr16.rating = 0;
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break;
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}
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}
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/* register at clocksource framework */
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