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The i.MX fixes for 3.15:

Browse Source 
- A couple of dts changes for the fallout of imx-drm binding update
  - Parent DI clocks to video PLL for better HDMI support
  - PCIe interrupt mapping and GIC node fixes
  - A series of edmqmx6 board fixes
  - Other small and random fixes on imx5 and imx6 dts
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Merge tag 'imx-fixes-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes

The i.MX fixes for 3.15:
 - A couple of dts changes for the fallout of imx-drm binding update
 - Parent DI clocks to video PLL for better HDMI support
 - PCIe interrupt mapping and GIC node fixes
 - A series of edmqmx6 board fixes
 - Other small and random fixes on imx5 and imx6 dts

* tag 'imx-fixes-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: i.MX6: ipu_di_sel clocks can set parent rates
  ARM: imx6q: clk: Parent DI clocks to video PLL via di_pre_sel
  ARM: dts: imx: add required #clock-cells for fixed-clock
  ARM: dts: vybrid: drop address and size cells from GIC node
  ARM: dts: imx6sl-evk: Add an entry for MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11
  ARM: dts: imx53: fix apparent copy/paste error
  ARM: dts: imx6q-gw5xxx: remove dead 'crtcs' property
  ARM: dts: imx53-tx53: add IPU DI ports and endpoints
  ARM: dts: imx6: edmqmx6: add second STMPE
  ARM: dts: imx6: edmqmx6: USB H1 only supports host mode
  ARM: dts: imx6: edmqmx6: Do not use the OTG switch as VBUS regulator
  ARM: dts: imx6: edmqmx6: Fix usbotg id pin
  ARM: dt: microsom: don't set bit 7 for ethernet mux settings
  ARM: imx6q-clk: parent lvds_gate from lvds_sel
  ARM: dts: imx: drop invalid size and address cells properties
  ARM: dts: mx5: fix wrong stmpe-ts bindings
  ARM: dts: imx53-m53evk: Fix memory region description
  ARM: dts: imx53-qsb-common: Fix memory region description
  ARM: dts: imx6: add PCIe interrupt mapping properties

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-04-24 15:30:53 +02:00
commit 9dbb7e2451
19 changed files with 123 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/imx25.dtsi
View File

@ -56,6 +56,7 @@
osc {
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};

1
arch/arm/boot/dts/imx27-apf27.dts
View File

@ -29,6 +29,7 @@
osc26m {
compatible = "fsl,imx-osc26m", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
};

1
arch/arm/boot/dts/imx27.dtsi
View File

@ -48,6 +48,7 @@
osc26m {
compatible = "fsl,imx-osc26m", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
};

4
arch/arm/boot/dts/imx50.dtsi
View File

@ -53,21 +53,25 @@
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <22579200>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};

4
arch/arm/boot/dts/imx51.dtsi
View File

@ -50,21 +50,25 @@
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};

23
arch/arm/boot/dts/imx53-m53evk.dts
View File

@ -17,7 +17,8 @@
compatible = "denx,imx53-m53evk", "fsl,imx53";
memory {
reg = <0x70000000 0x20000000>;
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};
soc {
@ -193,17 +194,17 @@
irq-trigger = <0x1>;
stmpe_touchscreen {
compatible = "stmpe,ts";
compatible = "st,stmpe-ts";
reg = <0>;
ts,sample-time = <4>;
ts,mod-12b = <1>;
ts,ref-sel = <0>;
ts,adc-freq = <1>;
ts,ave-ctrl = <3>;
ts,touch-det-delay = <3>;
ts,settling = <4>;
ts,fraction-z = <7>;
ts,i-drive = <1>;
st,sample-time = <4>;
st,mod-12b = <1>;
st,ref-sel = <0>;
st,adc-freq = <1>;
st,ave-ctrl = <3>;
st,touch-det-delay = <3>;
st,settling = <4>;
st,fraction-z = <7>;
st,i-drive = <1>;
};
};

3
arch/arm/boot/dts/imx53-qsb-common.dtsi
View File

@ -14,7 +14,8 @@
/ {
memory {
reg = <0x70000000 0x40000000>;
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};
display0: display@di0 {

11
arch/arm/boot/dts/imx53-tx53-x03x.dts
View File

@ -25,12 +25,17 @@
soc {
display: display@di0 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgb24_vga1>;
status = "okay";
port {
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
display-timings {
VGA {
clock-frequency = <25200000>;
@ -293,6 +298,10 @@
};
};
&ipu_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp>;

6
arch/arm/boot/dts/imx53.dtsi
View File

@ -70,21 +70,25 @@
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <22579200>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
@ -430,7 +434,7 @@
port {
lvds1_in: endpoint {
remote-endpoint = <&ipu_di0_lvds0>;
remote-endpoint = <&ipu_di1_lvds1>;
};
};
};

48
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
View File

@ -19,7 +19,10 @@
compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
aliases {
gpio7 = &stmpe_gpio;
gpio7 = &stmpe_gpio1;
gpio8 = &stmpe_gpio2;
stmpe-i2c0 = &stmpe1;
stmpe-i2c1 = &stmpe2;
};
memory {
@ -40,13 +43,15 @@
regulator-always-on;
};
reg_usb_otg_vbus: regulator@1 {
reg_usb_otg_switch: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_otg_vbus";
regulator-name = "usb_otg_switch";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio7 12 0>;
regulator-boot-on;
regulator-always-on;
};
reg_usb_host1: regulator@2 {
@ -65,23 +70,23 @@
led-blue {
label = "blue";
gpios = <&stmpe_gpio 8 GPIO_ACTIVE_HIGH>;
gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
led-green {
label = "green";
gpios = <&stmpe_gpio 9 GPIO_ACTIVE_HIGH>;
gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>;
};
led-pink {
label = "pink";
gpios = <&stmpe_gpio 10 GPIO_ACTIVE_HIGH>;
gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>;
};
led-red {
label = "red";
gpios = <&stmpe_gpio 11 GPIO_ACTIVE_HIGH>;
gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>;
};
};
};
@ -99,7 +104,8 @@
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2
&pinctrl_stmpe>;
&pinctrl_stmpe1
&pinctrl_stmpe2>;
status = "okay";
pmic: pfuze100@08 {
@ -205,13 +211,25 @@
};
};
stmpe: stmpe1601@40 {
stmpe1: stmpe1601@40 {
compatible = "st,stmpe1601";
reg = <0x40>;
interrupts = <30 0>;
interrupt-parent = <&gpio3>;
stmpe_gpio: stmpe_gpio {
stmpe_gpio1: stmpe_gpio {
#gpio-cells = <2>;
compatible = "st,stmpe-gpio";
};
};
stmpe2: stmpe1601@44 {
compatible = "st,stmpe1601";
reg = <0x44>;
interrupts = <2 0>;
interrupt-parent = <&gpio5>;
stmpe_gpio2: stmpe_gpio {
#gpio-cells = <2>;
compatible = "st,stmpe-gpio";
};
@ -273,10 +291,14 @@
>;
};
pinctrl_stmpe: stmpegrp {
pinctrl_stmpe1: stmpe1grp {
fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
};
pinctrl_stmpe2: stmpe2grp {
fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
@ -293,7 +315,7 @@
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
@ -344,11 +366,11 @@
&usbh1 {
vbus-supply = <&reg_usb_host1>;
disable-over-current;
dr_mode = "host";
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;

3
arch/arm/boot/dts/imx6q-gw5400-a.dts
View File

@ -487,9 +487,6 @@
&ldb {
status = "okay";
lvds-channel@0 {
crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
};
};
&pcie {

3
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
View File

@ -436,9 +436,6 @@
&ldb {
status = "okay";
lvds-channel@0 {
crtcs = <&ipu1 0>, <&ipu1 1>;
};
};
&pcie {

22
arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
View File

@ -26,25 +26,25 @@
/* GPIO16 -> AR8035 25MHz */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
/* AR8035 pin strapping: IO voltage: pull up */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
/* AR8035 pin strapping: PHYADDR#0: pull down */
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
/* AR8035 pin strapping: PHYADDR#1: pull down */
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
/* AR8035 pin strapping: MODE#1: pull up */
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
/* AR8035 pin strapping: MODE#3: pull up */
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
/* AR8035 pin strapping: MODE#0: pull down */
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
/*
* As the RMII pins are also connected to RGMII

13
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -10,6 +10,8 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
@ -46,8 +48,6 @@
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
@ -59,16 +59,19 @@
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
@ -138,6 +141,12 @@
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>;
interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
status = "disabled";

1
arch/arm/boot/dts/imx6sl-evk.dts
View File

@ -282,6 +282,7 @@
MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000
>;
};

4
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -68,8 +68,6 @@
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
@ -81,11 +79,13 @@
ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};

2
arch/arm/boot/dts/vf610-twr.dts
View File

@ -25,11 +25,13 @@
clocks {
audio_ext {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
enet_ext {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
};

4
arch/arm/boot/dts/vf610.dtsi
View File

@ -45,11 +45,13 @@
sxosc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
fxosc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
@ -72,8 +74,6 @@
intc: interrupt-controller@40002000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
reg = <0x40003000 0x1000>,
<0x40002100 0x100>;

29
arch/arm/mach-imx/clk-imx6q.c
View File

@ -208,8 +208,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
* the "output_enable" bit as a gate, even though it's really just
* enabling clock output.
*/
clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
/* name parent_name reg idx */
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
@ -258,14 +258,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
@ -445,6 +445,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
}
clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
/*
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
* We can not get the 100MHz from the pll2_pfd0_352m.