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soc: fsl: qe: merge qe_ic.h headers into qe_ic.c
The public qe_ic.h header is no longer included by anything but qe_ic.c. Merge both headers into qe_ic.c, and drop the unused constants. Reviewed-by: Timur Tabi <timur@kernel.org> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Li Yang <leoyang.li@nxp.com>
This commit is contained in:
Rasmus Villemoes
Li Yang
parent
882c626d1d
commit
9dab15b1a0
@ -15,6 +15,7 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/irq.h>
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#include <linux/reboot.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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@ -25,9 +26,56 @@
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <soc/fsl/qe/qe.h>
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#include <soc/fsl/qe/qe_ic.h>
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#include "qe_ic.h"
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#define NR_QE_IC_INTS 64
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/* QE IC registers offset */
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#define QEIC_CICR 0x00
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#define QEIC_CIVEC 0x04
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#define QEIC_CIPXCC 0x10
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#define QEIC_CIPYCC 0x14
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#define QEIC_CIPWCC 0x18
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#define QEIC_CIPZCC 0x1c
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#define QEIC_CIMR 0x20
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#define QEIC_CRIMR 0x24
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#define QEIC_CIPRTA 0x30
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#define QEIC_CIPRTB 0x34
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#define QEIC_CHIVEC 0x60
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struct qe_ic {
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/* Control registers offset */
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u32 __iomem *regs;
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/* The remapper for this QEIC */
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struct irq_domain *irqhost;
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/* The "linux" controller struct */
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struct irq_chip hc_irq;
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/* VIRQ numbers of QE high/low irqs */
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unsigned int virq_high;
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unsigned int virq_low;
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};
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/*
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* QE interrupt controller internal structure
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*/
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struct qe_ic_info {
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/* Location of this source at the QIMR register */
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u32 mask;
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/* Mask register offset */
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u32 mask_reg;
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/*
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* For grouped interrupts sources - the interrupt code as
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* appears at the group priority register
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*/
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u8 pri_code;
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/* Group priority register offset */
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u32 pri_reg;
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};
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static DEFINE_RAW_SPINLOCK(qe_ic_lock);
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@ -1,99 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* drivers/soc/fsl/qe/qe_ic.h
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*
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* QUICC ENGINE Interrupt Controller Header
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*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Li Yang <leoli@freescale.com>
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* Based on code from Shlomi Gridish <gridish@freescale.com>
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*/
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#ifndef _POWERPC_SYSDEV_QE_IC_H
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#define _POWERPC_SYSDEV_QE_IC_H
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#include <soc/fsl/qe/qe_ic.h>
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#define NR_QE_IC_INTS 64
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/* QE IC registers offset */
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#define QEIC_CICR 0x00
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#define QEIC_CIVEC 0x04
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#define QEIC_CRIPNR 0x08
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#define QEIC_CIPNR 0x0c
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#define QEIC_CIPXCC 0x10
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#define QEIC_CIPYCC 0x14
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#define QEIC_CIPWCC 0x18
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#define QEIC_CIPZCC 0x1c
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#define QEIC_CIMR 0x20
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#define QEIC_CRIMR 0x24
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#define QEIC_CICNR 0x28
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#define QEIC_CIPRTA 0x30
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#define QEIC_CIPRTB 0x34
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#define QEIC_CRICR 0x3c
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#define QEIC_CHIVEC 0x60
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/* Interrupt priority registers */
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#define CIPCC_SHIFT_PRI0 29
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#define CIPCC_SHIFT_PRI1 26
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#define CIPCC_SHIFT_PRI2 23
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#define CIPCC_SHIFT_PRI3 20
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#define CIPCC_SHIFT_PRI4 13
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#define CIPCC_SHIFT_PRI5 10
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#define CIPCC_SHIFT_PRI6 7
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#define CIPCC_SHIFT_PRI7 4
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/* CICR priority modes */
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#define CICR_GWCC 0x00040000
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#define CICR_GXCC 0x00020000
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#define CICR_GYCC 0x00010000
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#define CICR_GZCC 0x00080000
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#define CICR_GRTA 0x00200000
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#define CICR_GRTB 0x00400000
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#define CICR_HPIT_SHIFT 8
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#define CICR_HPIT_MASK 0x00000300
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#define CICR_HP_SHIFT 24
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#define CICR_HP_MASK 0x3f000000
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/* CICNR */
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#define CICNR_WCC1T_SHIFT 20
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#define CICNR_ZCC1T_SHIFT 28
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#define CICNR_YCC1T_SHIFT 12
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#define CICNR_XCC1T_SHIFT 4
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/* CRICR */
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#define CRICR_RTA1T_SHIFT 20
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#define CRICR_RTB1T_SHIFT 28
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/* Signal indicator */
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#define SIGNAL_MASK 3
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#define SIGNAL_HIGH 2
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#define SIGNAL_LOW 0
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struct qe_ic {
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/* Control registers offset */
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u32 __iomem *regs;
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/* The remapper for this QEIC */
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struct irq_domain *irqhost;
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/* The "linux" controller struct */
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struct irq_chip hc_irq;
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/* VIRQ numbers of QE high/low irqs */
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unsigned int virq_high;
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unsigned int virq_low;
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};
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/*
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* QE interrupt controller internal structure
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*/
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struct qe_ic_info {
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u32 mask; /* location of this source at the QIMR register. */
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u32 mask_reg; /* Mask register offset */
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u8 pri_code; /* for grouped interrupts sources - the interrupt
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code as appears at the group priority register */
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u32 pri_reg; /* Group priority register offset */
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};
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#endif /* _POWERPC_SYSDEV_QE_IC_H */
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@ -1,56 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Authors: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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*
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* Description:
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* QE IC external definitions and structure.
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*/
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#ifndef _ASM_POWERPC_QE_IC_H
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#define _ASM_POWERPC_QE_IC_H
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#include <linux/irq.h>
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struct device_node;
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struct qe_ic;
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#define NUM_OF_QE_IC_GROUPS 6
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/* Flags when we init the QE IC */
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#define QE_IC_SPREADMODE_GRP_W 0x00000001
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#define QE_IC_SPREADMODE_GRP_X 0x00000002
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#define QE_IC_SPREADMODE_GRP_Y 0x00000004
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#define QE_IC_SPREADMODE_GRP_Z 0x00000008
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#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
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#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
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#define QE_IC_LOW_SIGNAL 0x00000100
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#define QE_IC_HIGH_SIGNAL 0x00000200
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#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
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#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
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#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
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#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
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#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
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#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
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#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
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#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
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#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
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#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
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#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
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#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
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#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
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/* QE interrupt sources groups */
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enum qe_ic_grp_id {
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QE_IC_GRP_W = 0, /* QE interrupt controller group W */
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QE_IC_GRP_X, /* QE interrupt controller group X */
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QE_IC_GRP_Y, /* QE interrupt controller group Y */
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QE_IC_GRP_Z, /* QE interrupt controller group Z */
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QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
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QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
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};
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#endif /* _ASM_POWERPC_QE_IC_H */
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