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fsl/usb: Workarourd for USB erratum-A005697
The EHCI specification states the following in the SUSP bit description: In the Suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. However, in NXP USBDR controller, the PORTSCx[SUSP] bit changes immediately when the application sets it and not when the port is actually suspended. So the application must wait for at least 10 milliseconds after a port indicates that it is suspended, to make sure this port has entered suspended state before initiating this port resume using the Force Port Resume bit. This bit is for NXP controller, not EHCI compatible. Signed-off-by: Changming Huang <jerry.huang@nxp.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -286,6 +286,9 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
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if (pdata->has_fsl_erratum_a005275 == 1)
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ehci->has_fsl_hs_errata = 1;
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if (pdata->has_fsl_erratum_a005697 == 1)
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ehci->has_fsl_susp_errata = 1;
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if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
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(pdata->operating_mode == FSL_USB2_DR_OTG))
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if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
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@ -310,6 +310,14 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
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}
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spin_unlock_irq(&ehci->lock);
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if (changed && ehci_has_fsl_susp_errata(ehci))
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/*
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* Wait for at least 10 millisecondes to ensure the controller
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* enter the suspend status before initiating a port resume
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* using the Force Port Resume bit (Not-EHCI compatible).
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*/
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usleep_range(10000, 20000);
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if ((changed && ehci->has_tdi_phy_lpm) || fs_idle_delay) {
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/*
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* Wait for HCD to enter low-power mode or for the bus
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@ -1200,6 +1208,12 @@ int ehci_hub_control(
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wIndex, (temp1 & HOSTPC_PHCD) ?
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"succeeded" : "failed");
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}
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if (ehci_has_fsl_susp_errata(ehci)) {
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/* 10ms for HCD enter suspend */
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spin_unlock_irqrestore(&ehci->lock, flags);
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usleep_range(10000, 20000);
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spin_lock_irqsave(&ehci->lock, flags);
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}
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set_bit(wIndex, &ehci->suspended_ports);
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break;
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case USB_PORT_FEAT_POWER:
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@ -219,6 +219,7 @@ struct ehci_hcd { /* one per controller */
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unsigned no_selective_suspend:1;
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unsigned has_fsl_port_bug:1; /* FreeScale */
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unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */
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unsigned has_fsl_susp_errata:1; /* NXP SUSP quirk */
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unsigned big_endian_mmio:1;
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unsigned big_endian_desc:1;
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unsigned big_endian_capbase:1;
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@ -709,6 +710,13 @@ ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
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#define ehci_has_fsl_hs_errata(e) (0)
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#endif
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/*
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* Some Freescale/NXP processors have an erratum (USB A-005697)
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* in which we need to wait for 10ms for bus to enter suspend mode
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* after setting SUSP bit.
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*/
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#define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
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/*
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* While most USB host controllers implement their registers in
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* little-endian format, a minority (celleb companion chip) implement
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@ -226,6 +226,8 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device *ofdev)
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of_property_read_bool(np, "fsl,usb-erratum-a007792");
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pdata->has_fsl_erratum_a005275 =
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of_property_read_bool(np, "fsl,usb-erratum-a005275");
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pdata->has_fsl_erratum_a005697 =
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of_property_read_bool(np, "fsl,usb_erratum-a005697");
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/*
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* Determine whether phy_clk_valid needs to be checked
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@ -100,6 +100,7 @@ struct fsl_usb2_platform_data {
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unsigned already_suspended:1;
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unsigned has_fsl_erratum_a007792:1;
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unsigned has_fsl_erratum_a005275:1;
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unsigned has_fsl_erratum_a005697:1;
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unsigned check_phy_clk_valid:1;
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/* register save area for suspend/resume */
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