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ALSA: pxa2xx-ac97-lib: support building for several CPUs
Support building of pxa2xx-ac97-lib for several CPUs by making code run-time selected, not only compile-time. [Fixed 3XX->3xx typos in ifdef checks -- broonie.] Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
This commit is contained in:
Dmitry Baryshkov
Jaroslav Kysela
parent
9c63634221
commit
9d1cf39be6
@ -30,9 +30,7 @@ static DEFINE_MUTEX(car_mutex);
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static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
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static volatile long gsr_bits;
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static struct clk *ac97_clk;
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#ifdef CONFIG_PXA27x
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static struct clk *ac97conf_clk;
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#endif
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/*
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* Beware PXA27x bugs:
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@ -52,14 +50,10 @@ unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
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mutex_lock(&car_mutex);
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/* set up primary or secondary codec space */
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
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#else
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if (reg == AC97_GPIO_STATUS)
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if ((cpu_is_pxa21x() || cpu_is_pxa25x()) && reg == AC97_GPIO_STATUS)
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reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
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else
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reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
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#endif
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reg_addr += (reg >> 1);
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/* start read access across the ac97 link */
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@ -96,14 +90,10 @@ void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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mutex_lock(&car_mutex);
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/* set up primary or secondary codec space */
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
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#else
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if (reg == AC97_GPIO_STATUS)
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if ((cpu_is_pxa21x() || cpu_is_pxa25x()) && reg == AC97_GPIO_STATUS)
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reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
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else
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reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
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#endif
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reg_addr += (reg >> 1);
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GSR = GSR_CDONE | GSR_SDONE;
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@ -118,14 +108,33 @@ void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
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bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
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#ifdef CONFIG_PXA25x
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static inline void pxa_ac97_warm_pxa25x(void)
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{
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#ifdef CONFIG_PXA3xx
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int timeout = 100;
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#endif
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gsr_bits = 0;
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GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
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wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
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}
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static inline void pxa_ac97_cold_pxa25x(void)
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{
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GCR &= GCR_COLD_RST; /* clear everything but nCRST */
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GCR &= ~GCR_COLD_RST; /* then assert nCRST */
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gsr_bits = 0;
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GCR = GCR_COLD_RST;
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GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
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wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
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}
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#endif
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#ifdef CONFIG_PXA27x
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static inline void pxa_ac97_warm_pxa27x(void)
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{
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gsr_bits = 0;
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/* warm reset broken on Bulverde,
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so manually keep AC97 reset high */
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pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
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@ -133,16 +142,80 @@ bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
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GCR |= GCR_WARM_RST;
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pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
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udelay(500);
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#elif defined(CONFIG_PXA3xx)
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}
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static inline void pxa_ac97_cold_pxa27x(void)
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{
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GCR &= GCR_COLD_RST; /* clear everything but nCRST */
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GCR &= ~GCR_COLD_RST; /* then assert nCRST */
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gsr_bits = 0;
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/* PXA27x Developers Manual section 13.5.2.2.1 */
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clk_enable(ac97conf_clk);
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udelay(5);
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clk_disable(ac97conf_clk);
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GCR = GCR_COLD_RST;
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udelay(50);
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}
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#endif
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#ifdef CONFIG_PXA3xx
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static inline void pxa_ac97_warm_pxa3xx(void)
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{
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int timeout = 100;
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gsr_bits = 0;
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/* Can't use interrupts */
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GCR |= GCR_WARM_RST;
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while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
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mdelay(1);
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#else
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GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
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wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
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}
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static inline void pxa_ac97_cold_pxa3xx(void)
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{
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int timeout = 1000;
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/* Hold CLKBPB for 100us */
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GCR = 0;
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GCR = GCR_CLKBPB;
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udelay(100);
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GCR = 0;
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GCR &= GCR_COLD_RST; /* clear everything but nCRST */
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GCR &= ~GCR_COLD_RST; /* then assert nCRST */
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gsr_bits = 0;
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/* Can't use interrupts on PXA3xx */
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GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
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GCR = GCR_WARM_RST | GCR_COLD_RST;
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while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
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mdelay(10);
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}
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#endif
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bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
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{
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#ifdef CONFIG_PXA25x
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if (cpu_is_pxa21x() || cpu_is_pxa25x())
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pxa_ac97_warm_pxa25x();
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else
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#endif
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#ifdef CONFIG_PXA27x
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if (cpu_is_pxa27x())
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pxa_ac97_warm_pxa27x();
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else
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#endif
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#ifdef CONFIG_PXA3xx
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if (cpu_is_pxa3xx())
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pxa_ac97_warm_pxa3xx();
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else
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#endif
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BUG();
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if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
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printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
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__func__, gsr_bits);
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@ -156,39 +229,22 @@ EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
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bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
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{
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#ifdef CONFIG_PXA3xx
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int timeout = 1000;
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/* Hold CLKBPB for 100us */
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GCR = 0;
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GCR = GCR_CLKBPB;
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udelay(100);
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GCR = 0;
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#ifdef CONFIG_PXA25x
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if (cpu_is_pxa21x() || cpu_is_pxa25x())
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pxa_ac97_cold_pxa25x();
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else
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#endif
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GCR &= GCR_COLD_RST; /* clear everything but nCRST */
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GCR &= ~GCR_COLD_RST; /* then assert nCRST */
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gsr_bits = 0;
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#ifdef CONFIG_PXA27x
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/* PXA27x Developers Manual section 13.5.2.2.1 */
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clk_enable(ac97conf_clk);
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udelay(5);
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clk_disable(ac97conf_clk);
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GCR = GCR_COLD_RST;
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udelay(50);
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#elif defined(CONFIG_PXA3xx)
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/* Can't use interrupts on PXA3xx */
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GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
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GCR = GCR_WARM_RST | GCR_COLD_RST;
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while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
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mdelay(10);
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#else
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GCR = GCR_COLD_RST;
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GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
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wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
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if (cpu_is_pxa27x())
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pxa_ac97_cold_pxa27x();
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else
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#endif
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#ifdef CONFIG_PXA3xx
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if (cpu_is_pxa3xx())
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pxa_ac97_cold_pxa3xx();
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else
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#endif
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BUG();
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if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
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printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
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@ -219,14 +275,14 @@ static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
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gsr_bits |= status;
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wake_up(&gsr_wq);
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#ifdef CONFIG_PXA27x
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/* Although we don't use those we still need to clear them
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since they tend to spuriously trigger when MMC is used
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(hardware bug? go figure)... */
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if (cpu_is_pxa27x()) {
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MISR = MISR_EOC;
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PISR = PISR_EOC;
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MCSR = MCSR_EOC;
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#endif
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}
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return IRQ_HANDLED;
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}
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@ -245,14 +301,16 @@ EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
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int pxa2xx_ac97_hw_resume(void)
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{
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if (cpu_is_pxa21x() || cpu_is_pxa25x() || cpu_is_pxa27x()) {
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pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
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pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
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pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
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pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
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#ifdef CONFIG_PXA27x
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}
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if (cpu_is_pxa27x()) {
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/* Use GPIO 113 as AC97 Reset on Bulverde */
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pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
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#endif
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}
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clk_enable(ac97_clk);
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return 0;
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}
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@ -267,11 +325,14 @@ int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
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if (ret < 0)
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goto err;
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if (cpu_is_pxa21x() || cpu_is_pxa25x() || cpu_is_pxa27x()) {
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pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
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pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
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pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
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pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
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#ifdef CONFIG_PXA27x
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}
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if (cpu_is_pxa27x()) {
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/* Use GPIO 113 as AC97 Reset on Bulverde */
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pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
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ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
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@ -280,7 +341,7 @@ int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
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ac97conf_clk = NULL;
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goto err_irq;
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}
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#endif
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}
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ac97_clk = clk_get(&dev->dev, "AC97CLK");
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if (IS_ERR(ac97_clk)) {
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@ -293,12 +354,10 @@ int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
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err_irq:
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GCR |= GCR_ACLINK_OFF;
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#ifdef CONFIG_PXA27x
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if (ac97conf_clk) {
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clk_put(ac97conf_clk);
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ac97conf_clk = NULL;
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}
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#endif
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free_irq(IRQ_AC97, NULL);
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err:
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return ret;
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@ -309,10 +368,10 @@ void pxa2xx_ac97_hw_remove(struct platform_device *dev)
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{
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GCR |= GCR_ACLINK_OFF;
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free_irq(IRQ_AC97, NULL);
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#ifdef CONFIG_PXA27x
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if (ac97conf_clk) {
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clk_put(ac97conf_clk);
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ac97conf_clk = NULL;
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#endif
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}
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clk_disable(ac97_clk);
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clk_put(ac97_clk);
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ac97_clk = NULL;
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