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drm/i915: Prepare to consolidate fence writing

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Update the existing architecture specific fence writing routines to
either update the fence to point to a tiled object or to clear them in
preparation to remove the other fence writing routes.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Chris Wilson 2012-04-17 15:31:30 +01:00 committed by Daniel Vetter
parent 1899184547
commit 9ce079e481
1 changed files with 105 additions and 100 deletions
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205
drivers/gpu/drm/i915/i915_gem.c
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@ -2163,121 +2163,142 @@ int i915_gpu_idle(struct drm_device *dev, bool do_retire)
return 0; return 0;
} }
static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj) static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
struct drm_i915_gem_object *obj)
{ {
struct drm_device *dev = obj->base.dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
u32 size = obj->gtt_space->size;
int regnum = obj->fence_reg;
uint64_t val; uint64_t val;
val = (uint64_t)((obj->gtt_offset + size - 4096) & if (obj) {
0xfffff000) << 32; u32 size = obj->gtt_space->size;
val |= obj->gtt_offset & 0xfffff000;
val |= (uint64_t)((obj->stride / 128) - 1) <<
SANDYBRIDGE_FENCE_PITCH_SHIFT;
if (obj->tiling_mode == I915_TILING_Y) val = (uint64_t)((obj->gtt_offset + size - 4096) &
val |= 1 << I965_FENCE_TILING_Y_SHIFT; 0xfffff000) << 32;
val |= I965_FENCE_REG_VALID; val |= obj->gtt_offset & 0xfffff000;
val |= (uint64_t)((obj->stride / 128) - 1) <<
SANDYBRIDGE_FENCE_PITCH_SHIFT;
I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); if (obj->tiling_mode == I915_TILING_Y)
val |= 1 << I965_FENCE_TILING_Y_SHIFT;
val |= I965_FENCE_REG_VALID;
} else
val = 0;
return 0; I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
} }
static int i965_write_fence_reg(struct drm_i915_gem_object *obj) static void i965_write_fence_reg(struct drm_device *dev, int reg,
struct drm_i915_gem_object *obj)
{ {
struct drm_device *dev = obj->base.dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
u32 size = obj->gtt_space->size;
int regnum = obj->fence_reg;
uint64_t val; uint64_t val;
val = (uint64_t)((obj->gtt_offset + size - 4096) & if (obj) {
0xfffff000) << 32; u32 size = obj->gtt_space->size;
val |= obj->gtt_offset & 0xfffff000;
val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
if (obj->tiling_mode == I915_TILING_Y)
val |= 1 << I965_FENCE_TILING_Y_SHIFT;
val |= I965_FENCE_REG_VALID;
I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); val = (uint64_t)((obj->gtt_offset + size - 4096) &
0xfffff000) << 32;
val |= obj->gtt_offset & 0xfffff000;
val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
if (obj->tiling_mode == I915_TILING_Y)
val |= 1 << I965_FENCE_TILING_Y_SHIFT;
val |= I965_FENCE_REG_VALID;
} else
val = 0;
return 0; I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
POSTING_READ(FENCE_REG_965_0 + reg * 8);
} }
static int i915_write_fence_reg(struct drm_i915_gem_object *obj) static void i915_write_fence_reg(struct drm_device *dev, int reg,
struct drm_i915_gem_object *obj)
{ {
struct drm_device *dev = obj->base.dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
u32 size = obj->gtt_space->size; u32 val;
u32 fence_reg, val, pitch_val;
int tile_width;
if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || if (obj) {
(size & -size) != size || u32 size = obj->gtt_space->size;
(obj->gtt_offset & (size - 1)), int pitch_val;
"object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", int tile_width;
obj->gtt_offset, obj->map_and_fenceable, size))
return -EINVAL;
if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
tile_width = 128; (size & -size) != size ||
(obj->gtt_offset & (size - 1)),
"object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
obj->gtt_offset, obj->map_and_fenceable, size);
if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
tile_width = 128;
else
tile_width = 512;
/* Note: pitch better be a power of two tile widths */
pitch_val = obj->stride / tile_width;
pitch_val = ffs(pitch_val) - 1;
val = obj->gtt_offset;
if (obj->tiling_mode == I915_TILING_Y)
val |= 1 << I830_FENCE_TILING_Y_SHIFT;
val |= I915_FENCE_SIZE_BITS(size);
val |= pitch_val << I830_FENCE_PITCH_SHIFT;
val |= I830_FENCE_REG_VALID;
} else
val = 0;
if (reg < 8)
reg = FENCE_REG_830_0 + reg * 4;
else else
tile_width = 512; reg = FENCE_REG_945_8 + (reg - 8) * 4;
/* Note: pitch better be a power of two tile widths */ I915_WRITE(reg, val);
pitch_val = obj->stride / tile_width; POSTING_READ(reg);
pitch_val = ffs(pitch_val) - 1;
val = obj->gtt_offset;
if (obj->tiling_mode == I915_TILING_Y)
val |= 1 << I830_FENCE_TILING_Y_SHIFT;
val |= I915_FENCE_SIZE_BITS(size);
val |= pitch_val << I830_FENCE_PITCH_SHIFT;
val |= I830_FENCE_REG_VALID;
fence_reg = obj->fence_reg;
if (fence_reg < 8)
fence_reg = FENCE_REG_830_0 + fence_reg * 4;
else
fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
I915_WRITE(fence_reg, val);
return 0;
} }
static int i830_write_fence_reg(struct drm_i915_gem_object *obj) static void i830_write_fence_reg(struct drm_device *dev, int reg,
struct drm_i915_gem_object *obj)
{ {
struct drm_device *dev = obj->base.dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
u32 size = obj->gtt_space->size;
int regnum = obj->fence_reg;
uint32_t val; uint32_t val;
uint32_t pitch_val;
if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || if (obj) {
(size & -size) != size || u32 size = obj->gtt_space->size;
(obj->gtt_offset & (size - 1)), uint32_t pitch_val;
"object 0x%08x not 512K or pot-size 0x%08x aligned\n",
obj->gtt_offset, size))
return -EINVAL;
pitch_val = obj->stride / 128; WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
pitch_val = ffs(pitch_val) - 1; (size & -size) != size ||
(obj->gtt_offset & (size - 1)),
"object 0x%08x not 512K or pot-size 0x%08x aligned\n",
obj->gtt_offset, size);
val = obj->gtt_offset; pitch_val = obj->stride / 128;
if (obj->tiling_mode == I915_TILING_Y) pitch_val = ffs(pitch_val) - 1;
val |= 1 << I830_FENCE_TILING_Y_SHIFT;
val |= I830_FENCE_SIZE_BITS(size);
val |= pitch_val << I830_FENCE_PITCH_SHIFT;
val |= I830_FENCE_REG_VALID;
I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); val = obj->gtt_offset;
if (obj->tiling_mode == I915_TILING_Y)
val |= 1 << I830_FENCE_TILING_Y_SHIFT;
val |= I830_FENCE_SIZE_BITS(size);
val |= pitch_val << I830_FENCE_PITCH_SHIFT;
val |= I830_FENCE_REG_VALID;
} else
val = 0;
return 0; I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
POSTING_READ(FENCE_REG_830_0 + reg * 4);
}
static void i915_gem_write_fence(struct drm_device *dev, int reg,
struct drm_i915_gem_object *obj)
{
switch (INTEL_INFO(dev)->gen) {
case 7:
case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
case 5:
case 4: i965_write_fence_reg(dev, reg, obj); break;
case 3: i915_write_fence_reg(dev, reg, obj); break;
case 2: i830_write_fence_reg(dev, reg, obj); break;
default: break;
}
} }
static int static int
@ -2447,24 +2468,8 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
update: update:
obj->tiling_changed = false; obj->tiling_changed = false;
switch (INTEL_INFO(dev)->gen) { i915_gem_write_fence(dev, reg - dev_priv->fence_regs, obj);
case 7: return 0;
case 6:
ret = sandybridge_write_fence_reg(obj);
break;
case 5:
case 4:
ret = i965_write_fence_reg(obj);
break;
case 3:
ret = i915_write_fence_reg(obj);
break;
case 2:
ret = i830_write_fence_reg(obj);
break;
}
return ret;
} }
/** /**