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PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space

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Updating device tree documentation with prefetchable memory
sapce.
Configuration space shifted to 64-bit address space.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Bharat Kumar Gogada 2016-08-09 19:30:09 +05:30 committed by Rob Herring
parent c4dcd205eb
commit 9cbbae2a62
1 changed files with 3 additions and 2 deletions
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Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
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@ -55,9 +55,10 @@ nwl_pcie: pcie@fd0e0000 {
msi-parent = <&nwl_pcie>;
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
<0x0 0xe0000000 0x0 0x1000000>;
<0x80 0x00000000 0x0 0x1000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
pcie_intc: legacy-interrupt-controller {
interrupt-controller;