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docs: PCI: Fix typos
Fix typos in PCI docs. Link: https://lore.kernel.org/r/20231223184720.25645-1-tintinm2017@gmail.com Link: https://lore.kernel.org/r/20231223184412.25598-1-tintinm2017@gmail.com Signed-off-by: Attreyee Mukherjee <tintinm2017@gmail.com> [bhelgaas: squashed, commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> # for "busses" only
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@ -61,7 +61,7 @@ Conditions
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==========
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The use of threaded interrupts is the most likely condition to trigger
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this problem today. Threaded interrupts may not be reenabled after the IRQ
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this problem today. Threaded interrupts may not be re-enabled after the IRQ
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handler wakes. These "one shot" conditions mean that the threaded interrupt
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needs to keep the interrupt line masked until the threaded handler has run.
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Especially when dealing with high data rate interrupts, the thread needs to
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@ -236,7 +236,7 @@ including a full 'lspci -v' so we can add the quirks to the kernel.
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Disabling MSIs below a bridge
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-----------------------------
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Some PCI bridges are not able to route MSIs between busses properly.
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Some PCI bridges are not able to route MSIs between buses properly.
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In this case, MSIs must be disabled on all devices behind the bridge.
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Some bridges allow you to enable MSIs by changing some bits in their
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