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ARM: CSR: PM: save/restore irq status in suspend cycle

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SiRFprimaII will lose power in deepsleep mode except rtc, pmu and sdram
self-refresh. So IRQ controller will lose status in suspend cyle.
This patch saves irq mask/level registers while suspending and restore
them while resuming.

Signed-off-by: Barry Song <baohua.song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Barry Song 2011-09-21 21:40:33 +08:00 committed by Barry Song
parent e5598a855b
commit 9c2a51faab
1 changed files with 40 additions and 0 deletions
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40
arch/arm/mach-prima2/irq.c
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@ -14,6 +14,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/irqdomain.h>
#include <linux/syscore_ops.h>
#define SIRFSOC_INT_RISC_MASK0 0x0018
#define SIRFSOC_INT_RISC_MASK1 0x001C
@ -73,3 +74,42 @@ void __init sirfsoc_of_irq_init(void)
sirfsoc_irq_init();
}
struct sirfsoc_irq_status {
u32 mask0;
u32 mask1;
u32 level0;
u32 level1;
};
static struct sirfsoc_irq_status sirfsoc_irq_st;
static int sirfsoc_irq_suspend(void)
{
sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
return 0;
}
static void sirfsoc_irq_resume(void)
{
writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
}
static struct syscore_ops sirfsoc_irq_syscore_ops = {
.suspend = sirfsoc_irq_suspend,
.resume = sirfsoc_irq_resume,
};
static int __init sirfsoc_irq_pm_init(void)
{
register_syscore_ops(&sirfsoc_irq_syscore_ops);
return 0;
}
device_initcall(sirfsoc_irq_pm_init);