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bnx2x: Fix waiting for reset complete on BCM848x3 PHYs
BCM848x3 requires additional of 50ms after reset done indication, instead of fixed time of 200ms Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -5302,7 +5302,7 @@ static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
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{
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struct bnx2x *bp = params->bp;
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u16 autoneg_val, an_1000_val, an_10_100_val;
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bnx2x_wait_reset_complete(bp, phy);
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bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
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1 << NIG_LATCH_BC_ENABLE_MI_INT);
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@ -5431,6 +5431,7 @@ static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
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/* HW reset */
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bnx2x_ext_phy_hw_reset(bp, params->port);
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bnx2x_wait_reset_complete(bp, phy);
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bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
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return bnx2x_848xx_cmn_config_init(phy, params, vars);
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@ -5453,8 +5454,9 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
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bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
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MISC_REGISTERS_GPIO_OUTPUT_HIGH,
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port);
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msleep(200); /* 100 is not enough */
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bnx2x_wait_reset_complete(bp, phy);
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/* Wait for GPHY to come out of reset */
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msleep(50);
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/* BCM84823 requires that XGXS links up first @ 10G for normal
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behavior */
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temp = vars->line_speed;
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