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https://github.com/edk2-porting/linux-next.git
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i.MX DT changes with new clock for 5.3:
- This is a set of device tree changes with new clocks - adding clock info for i.MX8 GPIO and SNVS RTC device. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJdEY9IAAoJEFBXWFqHsHzONzkH/iQWmmauxY3ONsDhCOiq2xkz agKfN77pgM0005NJl8bP/+wyl6JXozpq31PJrbWPvdZCwElEzBykmWZzyG2cl6Bx ajwsldhBzMoYKvjVH0MD3ldPXoANsvfIQiAyVzPHY/tCBHI6hnaJKWCaQ0fsqg5M vZ0lf5Adqh9MN7lBKWBz1tbOgqCNAVdhRrvLdrTuoQ/asjivqzl3oXXMWzzrc4lK pUGPg1+iqf/MSBVoX8F3ETO9W+GjdjHE0qoGttXf90w2epQZqO5Ta2mfhzyF4fkE pcPGKQTASi+zOcUuzgM97TGfWbeOYhd0kRmInZVZt+Wce2Ju4MO5M0Iyxp6xvJI= =GaZH -----END PGP SIGNATURE----- Merge tag 'imx-dt-clkdep-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX DT changes with new clock for 5.3: - This is a set of device tree changes with new clocks - adding clock info for i.MX8 GPIO and SNVS RTC device. * tag 'imx-dt-clkdep-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8mq: add clock for SNVS RTC node arm64: dts: imx8mm: add clock for SNVS RTC node arm64: dts: imx8mm: add clock for GPIO node clk: imx8m: Add GIC clock dt-bindings: clock: imx8m: Add GIC clock clk: imx8mm: add SNVS clock to clock tree dt-bindings: clock: imx8mm: Add SNVS clock clk: imx8mq: add SNVS clock to clock tree dt-bindings: clock: imx8mq: Add SNVS clock clk: imx8mm: add GPIO clocks to clock tree dt-bindings: clock: imx8mm: Add GPIO clocks Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
9bb03d2644
@ -206,6 +206,7 @@
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reg = <0x30200000 0x10000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -217,6 +218,7 @@
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reg = <0x30210000 0x10000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -228,6 +230,7 @@
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reg = <0x30220000 0x10000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -239,6 +242,7 @@
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reg = <0x30230000 0x10000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -250,6 +254,7 @@
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reg = <0x30240000 0x10000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@ -336,6 +341,8 @@
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offset = <0x34>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
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clock-names = "snvs-rtc";
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};
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snvs_pwrkey: snvs-powerkey {
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@ -433,6 +433,8 @@
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offset = <0x34>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
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clock-names = "snvs-rtc";
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};
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};
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@ -288,6 +288,9 @@ static const char *imx8mm_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pl
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static const char *imx8mm_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
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"sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
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static const char *imx8mm_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll2_100m",
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"sys_pll1_800m", "clk_ext2", "clk_ext4", "audio_pll2_out" };
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static const char *imx8mm_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
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"sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
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@ -558,6 +561,7 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
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clks[IMX8MM_CLK_UART4] = imx8m_clk_composite("uart4", imx8mm_uart4_sels, base + 0xb080);
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clks[IMX8MM_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100);
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clks[IMX8MM_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180);
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clks[IMX8MM_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mm_gic_sels, base + 0xb200);
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clks[IMX8MM_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280);
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clks[IMX8MM_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300);
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clks[IMX8MM_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380);
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@ -590,6 +594,11 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
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clks[IMX8MM_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
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clks[IMX8MM_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
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clks[IMX8MM_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
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clks[IMX8MM_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
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clks[IMX8MM_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
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clks[IMX8MM_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
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clks[IMX8MM_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
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clks[IMX8MM_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
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clks[IMX8MM_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
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clks[IMX8MM_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
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clks[IMX8MM_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
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@ -617,6 +626,7 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
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clks[IMX8MM_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
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clks[IMX8MM_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
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clks[IMX8MM_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
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clks[IMX8MM_CLK_SNVS_ROOT] = imx_clk_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
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clks[IMX8MM_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
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clks[IMX8MM_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
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clks[IMX8MM_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
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@ -192,6 +192,9 @@ static const char * const imx8mq_usb_core_sels[] = {"osc_25m", "sys1_pll_100m",
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static const char * const imx8mq_usb_phy_sels[] = {"osc_25m", "sys1_pll_100m", "sys1_pll_40m", "sys2_pll_100m",
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"sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
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static const char * const imx8mq_gic_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys2_pll_100m",
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"sys2_pll_200m", "clk_ext2", "clk_ext3", "audio_pll2_out" };
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static const char * const imx8mq_ecspi1_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_40m", "sys1_pll_160m",
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"sys1_pll_800m", "sys3_pll2_out", "sys2_pll_250m", "audio_pll2_out", };
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@ -442,6 +445,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
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clks[IMX8MQ_CLK_UART4] = imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080);
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clks[IMX8MQ_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100);
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clks[IMX8MQ_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180);
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clks[IMX8MQ_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mq_gic_sels, base + 0xb200);
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clks[IMX8MQ_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280);
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clks[IMX8MQ_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300);
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clks[IMX8MQ_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mq_pwm1_sels, base + 0xb380);
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@ -507,6 +511,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
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clks[IMX8MQ_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
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clks[IMX8MQ_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
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clks[IMX8MQ_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
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clks[IMX8MQ_CLK_SNVS_ROOT] = imx_clk_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
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clks[IMX8MQ_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
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clks[IMX8MQ_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
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clks[IMX8MQ_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
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@ -239,6 +239,15 @@
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#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222
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#define IMX8MM_CLK_END 223
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#define IMX8MM_CLK_GPIO1_ROOT 223
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#define IMX8MM_CLK_GPIO2_ROOT 224
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#define IMX8MM_CLK_GPIO3_ROOT 225
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#define IMX8MM_CLK_GPIO4_ROOT 226
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#define IMX8MM_CLK_GPIO5_ROOT 227
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#define IMX8MM_CLK_SNVS_ROOT 228
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#define IMX8MM_CLK_GIC 229
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#define IMX8MM_CLK_END 230
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#endif
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@ -400,5 +400,8 @@
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#define IMX8MQ_CLK_GPIO4_ROOT 262
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#define IMX8MQ_CLK_GPIO5_ROOT 263
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#define IMX8MQ_CLK_END 264
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#define IMX8MQ_CLK_SNVS_ROOT 264
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#define IMX8MQ_CLK_GIC 265
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#define IMX8MQ_CLK_END 266
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#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
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