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staging: tidspbridge: add memory consistency to TODO list

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This driver uses ioremap on regular memory to get an uncached mapping,
which causes problems on ARMv6 and higher due to aliasing with the
cached linar kernel mapping.

Make sure this gets fixed before the driver graduates from staging.

Cc: Felipe Contreras <felipe.contreras@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Arnd Bergmann 2010-10-09 16:43:24 +02:00 committed by Greg Kroah-Hartman
parent cbf6baac77
commit 9b24b8f941
1 changed files with 1 additions and 0 deletions
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drivers/staging/tidspbridge/TODO
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@ -13,6 +13,7 @@
* Audit and clean up header files folder
* Use kernel coding style
* checkpatch.pl fixes
* allocate ext_mem_pool from consistent memory instead of using ioremap
Please send any patches to Greg Kroah-Hartman <greg@kroah.com>
and Omar Ramirez Luna <omar.ramirez@ti.com>.