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clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036
The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a ","
between the 3rd and 4th parent names, making them fall together and thus
lookups fail. Fix that.
Fixes: 5190c08b29
("clk: rockchip: add clock controller for rk3036")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -127,7 +127,7 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
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PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
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PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
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PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll" "usb480m" };
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PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
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PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
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PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
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