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https://github.com/edk2-porting/linux-next.git
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drm/radeon/kms: fill in startup/shutdown callbacks for SI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
25a857fbe9
commit
9b136d514e
@ -3468,6 +3468,12 @@ static void si_irq_suspend(struct radeon_device *rdev)
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si_rlc_stop(rdev);
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}
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static void si_irq_fini(struct radeon_device *rdev)
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{
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si_irq_suspend(rdev);
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r600_ih_ring_fini(rdev);
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}
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static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
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{
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u32 wptr, tmp;
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@ -3793,3 +3799,326 @@ restart_ih:
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return IRQ_HANDLED;
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}
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/*
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* startup/shutdown callbacks
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*/
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static int si_startup(struct radeon_device *rdev)
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{
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struct radeon_ring *ring;
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int r;
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if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
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!rdev->rlc_fw || !rdev->mc_fw) {
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r = si_init_microcode(rdev);
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if (r) {
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DRM_ERROR("Failed to load firmware!\n");
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return r;
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}
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}
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r = si_mc_load_microcode(rdev);
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if (r) {
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DRM_ERROR("Failed to load MC firmware!\n");
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return r;
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}
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r = r600_vram_scratch_init(rdev);
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if (r)
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return r;
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si_mc_program(rdev);
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r = si_pcie_gart_enable(rdev);
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if (r)
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return r;
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si_gpu_init(rdev);
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#if 0
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r = evergreen_blit_init(rdev);
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if (r) {
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r600_blit_fini(rdev);
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rdev->asic->copy = NULL;
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dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
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}
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#endif
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/* allocate rlc buffers */
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r = si_rlc_init(rdev);
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if (r) {
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DRM_ERROR("Failed to init rlc BOs!\n");
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return r;
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}
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/* allocate wb buffer */
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r = radeon_wb_init(rdev);
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if (r)
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return r;
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r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
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if (r) {
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dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
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return r;
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}
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r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
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if (r) {
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dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
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return r;
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}
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r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
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if (r) {
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dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
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return r;
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}
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/* Enable IRQ */
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r = si_irq_init(rdev);
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if (r) {
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DRM_ERROR("radeon: IH init failed (%d).\n", r);
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radeon_irq_kms_fini(rdev);
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return r;
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}
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si_irq_set(rdev);
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ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
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CP_RB0_RPTR, CP_RB0_WPTR,
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0, 0xfffff, RADEON_CP_PACKET2);
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if (r)
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return r;
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ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
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CP_RB1_RPTR, CP_RB1_WPTR,
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0, 0xfffff, RADEON_CP_PACKET2);
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if (r)
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return r;
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ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
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CP_RB2_RPTR, CP_RB2_WPTR,
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0, 0xfffff, RADEON_CP_PACKET2);
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if (r)
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return r;
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r = si_cp_load_microcode(rdev);
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if (r)
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return r;
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r = si_cp_resume(rdev);
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if (r)
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return r;
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r = radeon_ib_pool_start(rdev);
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if (r)
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return r;
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r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
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if (r) {
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DRM_ERROR("radeon: failed testing IB (%d) on CP ring 0\n", r);
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rdev->accel_working = false;
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return r;
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}
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r = radeon_ib_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
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if (r) {
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DRM_ERROR("radeon: failed testing IB (%d) on CP ring 1\n", r);
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rdev->accel_working = false;
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return r;
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}
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r = radeon_ib_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
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if (r) {
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DRM_ERROR("radeon: failed testing IB (%d) on CP ring 2\n", r);
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rdev->accel_working = false;
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return r;
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}
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r = radeon_vm_manager_start(rdev);
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if (r)
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return r;
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return 0;
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}
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int si_resume(struct radeon_device *rdev)
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{
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int r;
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/* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
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* posting will perform necessary task to bring back GPU into good
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* shape.
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*/
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/* post card */
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atom_asic_init(rdev->mode_info.atom_context);
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rdev->accel_working = true;
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r = si_startup(rdev);
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if (r) {
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DRM_ERROR("si startup failed on resume\n");
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rdev->accel_working = false;
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return r;
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}
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return r;
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}
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int si_suspend(struct radeon_device *rdev)
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{
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/* FIXME: we should wait for ring to be empty */
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radeon_ib_pool_suspend(rdev);
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radeon_vm_manager_suspend(rdev);
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#if 0
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r600_blit_suspend(rdev);
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#endif
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si_cp_enable(rdev, false);
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
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rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
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rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
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si_irq_suspend(rdev);
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radeon_wb_disable(rdev);
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si_pcie_gart_disable(rdev);
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return 0;
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}
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/* Plan is to move initialization in that function and use
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* helper function so that radeon_device_init pretty much
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* do nothing more than calling asic specific function. This
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* should also allow to remove a bunch of callback function
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* like vram_info.
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*/
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int si_init(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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int r;
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/* This don't do much */
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r = radeon_gem_init(rdev);
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if (r)
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return r;
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/* Read BIOS */
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if (!radeon_get_bios(rdev)) {
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if (ASIC_IS_AVIVO(rdev))
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return -EINVAL;
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}
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/* Must be an ATOMBIOS */
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if (!rdev->is_atom_bios) {
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dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
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return -EINVAL;
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}
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r = radeon_atombios_init(rdev);
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if (r)
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return r;
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/* Post card if necessary */
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if (!radeon_card_posted(rdev)) {
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if (!rdev->bios) {
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dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
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return -EINVAL;
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}
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DRM_INFO("GPU not posted. posting now...\n");
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atom_asic_init(rdev->mode_info.atom_context);
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}
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/* Initialize scratch registers */
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si_scratch_init(rdev);
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/* Initialize surface registers */
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radeon_surface_init(rdev);
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/* Initialize clocks */
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radeon_get_clock_info(rdev->ddev);
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/* Fence driver */
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r = radeon_fence_driver_init(rdev);
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if (r)
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return r;
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/* initialize memory controller */
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r = si_mc_init(rdev);
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if (r)
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return r;
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/* Memory manager */
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r = radeon_bo_init(rdev);
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if (r)
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return r;
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r = radeon_irq_kms_init(rdev);
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if (r)
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return r;
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ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 1024 * 1024);
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ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 1024 * 1024);
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ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 1024 * 1024);
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rdev->ih.ring_obj = NULL;
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r600_ih_ring_init(rdev, 64 * 1024);
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r = r600_pcie_gart_init(rdev);
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if (r)
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return r;
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r = radeon_ib_pool_init(rdev);
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rdev->accel_working = true;
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if (r) {
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dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
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rdev->accel_working = false;
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}
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r = radeon_vm_manager_init(rdev);
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if (r) {
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dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
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}
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r = si_startup(rdev);
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if (r) {
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dev_err(rdev->dev, "disabling GPU acceleration\n");
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si_cp_fini(rdev);
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si_irq_fini(rdev);
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si_rlc_fini(rdev);
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radeon_wb_fini(rdev);
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r100_ib_fini(rdev);
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radeon_vm_manager_fini(rdev);
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radeon_irq_kms_fini(rdev);
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si_pcie_gart_fini(rdev);
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rdev->accel_working = false;
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}
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/* Don't start up if the MC ucode is missing.
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* The default clocks and voltages before the MC ucode
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* is loaded are not suffient for advanced operations.
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*/
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if (!rdev->mc_fw) {
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DRM_ERROR("radeon: MC ucode required for NI+.\n");
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return -EINVAL;
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}
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return 0;
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}
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void si_fini(struct radeon_device *rdev)
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{
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#if 0
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r600_blit_fini(rdev);
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#endif
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si_cp_fini(rdev);
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si_irq_fini(rdev);
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si_rlc_fini(rdev);
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radeon_wb_fini(rdev);
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radeon_vm_manager_fini(rdev);
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r100_ib_fini(rdev);
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radeon_irq_kms_fini(rdev);
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si_pcie_gart_fini(rdev);
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r600_vram_scratch_fini(rdev);
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radeon_gem_fini(rdev);
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radeon_semaphore_driver_fini(rdev);
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radeon_fence_driver_fini(rdev);
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radeon_bo_fini(rdev);
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radeon_atombios_fini(rdev);
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kfree(rdev->bios);
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rdev->bios = NULL;
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}
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