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powerpc/85xx: Cleanup QE initialization for MPC85xxMDS boards
The mpc85xx_mds_setup_arch() function is incomprehensible and unmaintainable. Factor out all QE specific stuff into mpc85xx_mds_qe_init() and mpc85xx_mds_reset_ucc_phys(). Also move QE stuff out of mpc85xx_mds_pic_init(). The diff is unreadable, but only because the code was so. ;-) It should be better now, and less indented. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Anton Vorontsov
Kumar Gala
parent
dee9ad718b
commit
99d8238f5f
@ -177,63 +177,89 @@ static void __init mpc85xx_publish_qe_devices(void)
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of_platform_bus_probe(NULL, mpc85xx_qe_ids, NULL);
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}
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#else
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static void __init mpc85xx_publish_qe_devices(void) { }
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#endif /* CONFIG_QUICC_ENGINE */
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static void __init mpc85xx_mds_setup_arch(void)
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static void __init mpc85xx_mds_reset_ucc_phys(void)
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{
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struct device_node *np;
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static u8 __iomem *bcsr_regs = NULL;
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#ifdef CONFIG_PCI
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struct pci_controller *hose;
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#endif
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dma_addr_t max = 0xffffffff;
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
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static u8 __iomem *bcsr_regs;
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/* Map BCSR area */
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np = of_find_node_by_name(NULL, "bcsr");
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if (np != NULL) {
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struct resource res;
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if (!np)
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return;
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of_address_to_resource(np, 0, &res);
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bcsr_regs = ioremap(res.start, res.end - res.start +1);
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of_node_put(np);
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}
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bcsr_regs = of_iomap(np, 0);
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of_node_put(np);
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if (!bcsr_regs)
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return;
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#ifdef CONFIG_PCI
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for_each_node_by_type(np, "pci") {
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if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
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of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
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struct resource rsrc;
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of_address_to_resource(np, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == 0x8000)
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fsl_add_bridge(np, 1);
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else
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fsl_add_bridge(np, 0);
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if (machine_is(mpc8568_mds)) {
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#define BCSR_UCC1_GETH_EN (0x1 << 7)
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#define BCSR_UCC2_GETH_EN (0x1 << 7)
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#define BCSR_UCC1_MODE_MSK (0x3 << 4)
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#define BCSR_UCC2_MODE_MSK (0x3 << 0)
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hose = pci_find_hose_for_OF_device(np);
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max = min(max, hose->dma_window_base_cur +
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hose->dma_window_size);
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/* Turn off UCC1 & UCC2 */
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clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
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clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
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/* Mode is RGMII, all bits clear */
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clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
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BCSR_UCC2_MODE_MSK);
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/* Turn UCC1 & UCC2 on */
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setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
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setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
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} else if (machine_is(mpc8569_mds)) {
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#define BCSR7_UCC12_GETHnRST (0x1 << 2)
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#define BCSR8_UEM_MARVELL_RST (0x1 << 1)
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#define BCSR_UCC_RGMII (0x1 << 6)
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#define BCSR_UCC_RTBI (0x1 << 5)
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/*
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* U-Boot mangles interrupt polarity for Marvell PHYs,
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* so reset built-in and UEM Marvell PHYs, this puts
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* the PHYs into their normal state.
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*/
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clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
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setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
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setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
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clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
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for (np = NULL; (np = of_find_compatible_node(np,
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"network",
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"ucc_geth")) != NULL;) {
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const unsigned int *prop;
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int ucc_num;
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prop = of_get_property(np, "cell-index", NULL);
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if (prop == NULL)
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continue;
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ucc_num = *prop - 1;
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prop = of_get_property(np, "phy-connection-type", NULL);
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if (prop == NULL)
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continue;
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if (strcmp("rtbi", (const char *)prop) == 0)
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clrsetbits_8(&bcsr_regs[7 + ucc_num],
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BCSR_UCC_RGMII, BCSR_UCC_RTBI);
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}
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} else if (machine_is(p1021_mds)) {
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#define BCSR11_ENET_MICRST (0x1 << 5)
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/* Reset Micrel PHY */
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clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
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setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
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}
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#endif
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#ifdef CONFIG_SMP
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mpc85xx_smp_init();
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#endif
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iounmap(bcsr_regs);
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}
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#ifdef CONFIG_SWIOTLB
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if (lmb_end_of_DRAM() > max) {
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ppc_swiotlb_enable = 1;
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set_pci_dma_ops(&swiotlb_dma_ops);
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ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
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}
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#endif
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static void __init mpc85xx_mds_qe_init(void)
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{
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struct device_node *np;
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!np) {
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np = of_find_node_by_name(NULL, "qe");
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@ -260,70 +286,7 @@ static void __init mpc85xx_mds_setup_arch(void)
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par_io_of_config(ucc);
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}
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if (bcsr_regs) {
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if (machine_is(mpc8568_mds)) {
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#define BCSR_UCC1_GETH_EN (0x1 << 7)
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#define BCSR_UCC2_GETH_EN (0x1 << 7)
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#define BCSR_UCC1_MODE_MSK (0x3 << 4)
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#define BCSR_UCC2_MODE_MSK (0x3 << 0)
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/* Turn off UCC1 & UCC2 */
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clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
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clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
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/* Mode is RGMII, all bits clear */
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clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
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BCSR_UCC2_MODE_MSK);
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/* Turn UCC1 & UCC2 on */
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setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
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setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
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} else if (machine_is(mpc8569_mds)) {
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#define BCSR7_UCC12_GETHnRST (0x1 << 2)
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#define BCSR8_UEM_MARVELL_RST (0x1 << 1)
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#define BCSR_UCC_RGMII (0x1 << 6)
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#define BCSR_UCC_RTBI (0x1 << 5)
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/*
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* U-Boot mangles interrupt polarity for Marvell PHYs,
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* so reset built-in and UEM Marvell PHYs, this puts
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* the PHYs into their normal state.
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*/
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clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
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setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
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setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
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clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
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for (np = NULL; (np = of_find_compatible_node(np,
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"network",
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"ucc_geth")) != NULL;) {
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const unsigned int *prop;
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int ucc_num;
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prop = of_get_property(np, "cell-index", NULL);
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if (prop == NULL)
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continue;
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ucc_num = *prop - 1;
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prop = of_get_property(np, "phy-connection-type", NULL);
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if (prop == NULL)
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continue;
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if (strcmp("rtbi", (const char *)prop) == 0)
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clrsetbits_8(&bcsr_regs[7 + ucc_num],
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BCSR_UCC_RGMII, BCSR_UCC_RTBI);
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}
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} else if (machine_is(p1021_mds)) {
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#define BCSR11_ENET_MICRST (0x1 << 5)
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/* Reset Micrel PHY */
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clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
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setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
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}
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iounmap(bcsr_regs);
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}
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mpc85xx_mds_reset_ucc_phys();
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if (machine_is(p1021_mds)) {
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#define MPC85xx_PMUXCR_OFFSET 0x60
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@ -358,7 +321,79 @@ static void __init mpc85xx_mds_setup_arch(void)
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}
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}
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}
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static void __init mpc85xx_mds_qeic_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!of_device_is_available(np)) {
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of_node_put(np);
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return;
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}
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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if (!np) {
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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}
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if (machine_is(p1021_mds))
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qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
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qe_ic_cascade_high_mpic);
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else
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qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
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of_node_put(np);
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}
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#else
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static void __init mpc85xx_publish_qe_devices(void) { }
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static void __init mpc85xx_mds_qe_init(void) { }
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static void __init mpc85xx_mds_qeic_init(void) { }
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#endif /* CONFIG_QUICC_ENGINE */
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static void __init mpc85xx_mds_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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struct pci_controller *hose;
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#endif
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dma_addr_t max = 0xffffffff;
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
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#ifdef CONFIG_PCI
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for_each_node_by_type(np, "pci") {
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if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
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of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
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struct resource rsrc;
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of_address_to_resource(np, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == 0x8000)
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fsl_add_bridge(np, 1);
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else
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fsl_add_bridge(np, 0);
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hose = pci_find_hose_for_OF_device(np);
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max = min(max, hose->dma_window_base_cur +
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hose->dma_window_size);
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}
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}
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#endif
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#ifdef CONFIG_SMP
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mpc85xx_smp_init();
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#endif
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mpc85xx_mds_qe_init();
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#ifdef CONFIG_SWIOTLB
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if (lmb_end_of_DRAM() > max) {
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ppc_swiotlb_enable = 1;
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set_pci_dma_ops(&swiotlb_dma_ops);
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ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
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}
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#endif
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}
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@ -465,28 +500,7 @@ static void __init mpc85xx_mds_pic_init(void)
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of_node_put(np);
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mpic_init(mpic);
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_compatible_node(NULL, NULL, "fsl,qe");
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if (!of_device_is_available(np)) {
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of_node_put(np);
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return;
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}
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np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
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if (!np) {
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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}
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if (machine_is(p1021_mds))
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qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
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qe_ic_cascade_high_mpic);
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else
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qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
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of_node_put(np);
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#endif /* CONFIG_QUICC_ENGINE */
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mpc85xx_mds_qeic_init();
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}
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static int __init mpc85xx_mds_probe(void)
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