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drm/amd/display: Enable DSC power-gating for DSC streams

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[why]
Currently DSC power gating is disabled by default because the power
transition doesn't happen, causing a crash on some systems

[how]
Fix the lack of power state transition and enable DSC power gating
by default.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nikola Cornij 2019-05-08 14:36:03 -04:00 committed by Alex Deucher
parent c3ec8ba537
commit 98ce8cc1b4
2 changed files with 8 additions and 3 deletions
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8
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@ -222,6 +222,7 @@ static void dcn20_dsc_pg_control(
{
uint32_t power_gate = power_on ? 0 : 1;
uint32_t pwr_status = power_on ? 0 : 2;
uint32_t org_ip_request_cntl = 0;
if (hws->ctx->dc->debug.disable_dsc_power_gate)
return;
@ -229,6 +230,10 @@ static void dcn20_dsc_pg_control(
if (REG(DOMAIN16_PG_CONFIG) == 0)
return;
REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
if (org_ip_request_cntl == 0)
REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
switch (dsc_inst) {
case 0: /* DSC0 */
REG_UPDATE(DOMAIN16_PG_CONFIG,
@ -282,6 +287,9 @@ static void dcn20_dsc_pg_control(
BREAK_TO_DEBUGGER();
break;
}
if (org_ip_request_cntl == 0)
REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
}
#endif

3
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
View File

@ -724,9 +724,6 @@ static const struct dc_debug_options debug_defaults_diags = {
.disable_pplib_wm_range = true,
.disable_stutter = true,
.scl_reset_length10 = true,
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
.disable_dsc_power_gate = true,
#endif
};
void dcn20_dpp_destroy(struct dpp **dpp)