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x86/power: Optimize C3 entry on Centaur CPUs
For new Centaur CPUs the ucode will take care of the preservation of cache coherence between CPU cores in C-states regardless of how deep the C-states are. So, it is not necessary to flush the caches in software befor entering C3. This useless operation will cause performance drop for the cores which share some caches with the idling core. Signed-off-by: David Wang <davidwang@zhaoxin.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Pavel Machek <pavel@ucw.cz> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: brucechang@via-alliance.com Cc: cooperyan@zhaoxin.com Cc: len.brown@intel.com Cc: linux-pm@kernel.org Cc: qiyuanwang@zhaoxin.com Cc: rjw@rjwysocki.net Cc: timguo@zhaoxin.com Link: http://lkml.kernel.org/r/1545900110-2757-1-git-send-email-davidwang@zhaoxin.com [ Tidy up the comment. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -51,6 +51,18 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
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if (c->x86_vendor == X86_VENDOR_INTEL &&
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(c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
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flags->bm_control = 0;
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/*
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* For all recent Centaur CPUs, the ucode will make sure that each
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* core can keep cache coherence with each other while entering C3
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* type state. So, set bm_check to 1 to indicate that the kernel
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* doesn't need to execute a cache flush operation (WBINVD) when
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* entering C3 type state.
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*/
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if (c->x86_vendor == X86_VENDOR_CENTAUR) {
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if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f &&
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c->x86_stepping >= 0x0e))
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flags->bm_check = 1;
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}
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}
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EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
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