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drm/amdgpu: cleanup scheduler command submission
Unify the two code path again, cause they do pretty much the same thing. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <davdi1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
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@ -1210,6 +1210,7 @@ struct amdgpu_cs_parser {
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/* relocations */
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struct amdgpu_bo_list_entry *vm_bos;
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struct list_head validated;
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struct fence *fence;
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struct amdgpu_ib *ibs;
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uint32_t num_ibs;
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@ -439,8 +439,18 @@ static int cmp_size_smaller_first(void *priv, struct list_head *a,
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return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
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}
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static void amdgpu_cs_parser_fini_early(struct amdgpu_cs_parser *parser, int error, bool backoff)
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/**
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* cs_parser_fini() - clean parser states
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* @parser: parser structure holding parsing context.
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* @error: error number
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*
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* If error is set than unvalidate buffer, otherwise just free memory
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* used by parsing context.
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**/
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static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
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{
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unsigned i;
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if (!error) {
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/* Sort the buffer list from the smallest to largest buffer,
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* which affects the order of buffers in the LRU list.
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@ -455,17 +465,13 @@ static void amdgpu_cs_parser_fini_early(struct amdgpu_cs_parser *parser, int err
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list_sort(NULL, &parser->validated, cmp_size_smaller_first);
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ttm_eu_fence_buffer_objects(&parser->ticket,
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&parser->validated,
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&parser->ibs[parser->num_ibs-1].fence->base);
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&parser->validated,
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parser->fence);
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} else if (backoff) {
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ttm_eu_backoff_reservation(&parser->ticket,
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&parser->validated);
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}
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}
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static void amdgpu_cs_parser_fini_late(struct amdgpu_cs_parser *parser)
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{
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unsigned i;
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fence_put(parser->fence);
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if (parser->ctx)
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amdgpu_ctx_put(parser->ctx);
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@ -484,20 +490,6 @@ static void amdgpu_cs_parser_fini_late(struct amdgpu_cs_parser *parser)
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drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
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}
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/**
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* cs_parser_fini() - clean parser states
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* @parser: parser structure holding parsing context.
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* @error: error number
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*
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* If error is set than unvalidate buffer, otherwise just free memory
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* used by parsing context.
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**/
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static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
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{
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amdgpu_cs_parser_fini_early(parser, error, backoff);
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amdgpu_cs_parser_fini_late(parser);
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}
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static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
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struct amdgpu_vm *vm)
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{
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@ -582,15 +574,9 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
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}
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r = amdgpu_bo_vm_update_pte(parser, vm);
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if (r) {
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goto out;
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}
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amdgpu_cs_sync_rings(parser);
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if (!amdgpu_enable_scheduler)
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r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
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parser->filp);
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if (!r)
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amdgpu_cs_sync_rings(parser);
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out:
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return r;
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}
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@ -881,7 +867,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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goto out;
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}
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job->base.s_fence = fence;
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fence_get(&fence->base);
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parser.fence = fence_get(&fence->base);
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cs->out.handle = amdgpu_ctx_add_fence(parser.ctx, ring,
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&fence->base);
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@ -890,17 +876,16 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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trace_amdgpu_cs_ioctl(job);
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amd_sched_entity_push_job(&job->base);
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list_sort(NULL, &parser.validated, cmp_size_smaller_first);
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ttm_eu_fence_buffer_objects(&parser.ticket, &parser.validated,
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&fence->base);
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fence_put(&fence->base);
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} else {
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struct amdgpu_fence *fence;
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amdgpu_cs_parser_fini_late(&parser);
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mutex_unlock(&vm->mutex);
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return 0;
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r = amdgpu_ib_schedule(adev, parser.num_ibs, parser.ibs,
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parser.filp);
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fence = parser.ibs[parser.num_ibs - 1].fence;
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parser.fence = fence_get(&fence->base);
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cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence;
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}
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cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence;
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out:
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amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
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mutex_unlock(&vm->mutex);
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