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pinctrl: freescale: imx7d: support iomux lpsr controller
iMX7D has two iomuxc controllers, iomuxc controller similar as previous iMX SoC generation and iomuxc-lpsr which provides low power state rentetion capabilities on gpios that are part of iomuxc-lpsr Add iomuxc-lpsr gpio group id's Signed-off-by: Adrian Alonso <aalonso@freescale.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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26d8cde526
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@ -174,6 +174,17 @@ enum imx7d_pads {
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MX7D_PAD_ENET1_COL = 154,
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};
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enum imx7d_lpsr_pads {
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MX7D_PAD_GPIO1_IO00 = 0,
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MX7D_PAD_GPIO1_IO01 = 1,
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MX7D_PAD_GPIO1_IO02 = 2,
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MX7D_PAD_GPIO1_IO03 = 3,
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MX7D_PAD_GPIO1_IO04 = 4,
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MX7D_PAD_GPIO1_IO05 = 5,
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MX7D_PAD_GPIO1_IO06 = 6,
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MX7D_PAD_GPIO1_IO07 = 7,
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
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@ -333,13 +344,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
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IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
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};
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static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
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.pins = imx7d_pinctrl_pads,
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.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
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};
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static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
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.pins = imx7d_lpsr_pinctrl_pads,
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.npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
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.flags = ZERO_OFFSET_VALID,
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};
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static struct of_device_id imx7d_pinctrl_of_match[] = {
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{ .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, },
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{ .compatible = "fsl,imx7d-iomuxc-lpsr", .data = &imx7d_lpsr_pinctrl_info },
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{ /* sentinel */ }
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};
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