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dt-bindings: mmc: Add information for DLL register properties

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Add information regarding DLL register properties for getting board
specific configurations. These DLL register settings may vary from
board to board.

Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
Link: https://lore.kernel.org/r/1590139950-7288-3-git-send-email-sartgarg@codeaurora.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Sarthak Garg 2020-05-22 15:02:24 +05:30 committed by Ulf Hansson
parent b91da92909
commit 97306b631d
1 changed files with 13 additions and 0 deletions
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13
Documentation/devicetree/bindings/mmc/sdhci-msm.txt
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@ -47,6 +47,13 @@ Required properties:
"cal" - reference clock for RCLK delay calibration (optional) "cal" - reference clock for RCLK delay calibration (optional)
"sleep" - sleep clock for RCLK delay calibration (optional) "sleep" - sleep clock for RCLK delay calibration (optional)
- qcom,ddr-config: Certain chipsets and platforms require particular settings
for the DDR_CONFIG register. Use this field to specify the register
value as per the Hardware Programming Guide.
- qcom,dll-config: Chipset and Platform specific value. Use this field to
specify the DLL_CONFIG register value as per Hardware Programming Guide.
Example: Example:
sdhc_1: sdhci@f9824900 { sdhc_1: sdhci@f9824900 {
@ -64,6 +71,9 @@ Example:
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
qcom,dll-config = <0x000f642c>;
qcom,ddr-config = <0x80040868>;
}; };
sdhc_2: sdhci@f98a4900 { sdhc_2: sdhci@f98a4900 {
@ -81,4 +91,7 @@ Example:
clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
}; };