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octeontx2-pf: move lmt flush to include/linux/soc

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On OcteonTX2 platform CPT instruction enqueue and NIX
packet send are only possible via LMTST operations which
uses LDEOR instruction. This patch moves lmt flush
function from OcteonTX2 nic driver to include/linux/soc
since it will be used by OcteonTX2 CPT and NIC driver for
LMTST.

Signed-off-by: Suheil Chandran <schandran@marvell.com>
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Srujana Challa 2020-11-18 17:14:14 +05:30 committed by Jakub Kicinski
parent 1a0058cf0c
commit 956fb85218
3 changed files with 32 additions and 12 deletions
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2
MAINTAINERS
View File

@ -10453,6 +10453,7 @@ M: Srujana Challa <schalla@marvell.com>
L: linux-crypto@vger.kernel.org
S: Maintained
F: drivers/crypto/marvell/
F: include/linux/soc/marvell/octeontx2/
MARVELL GIGABIT ETHERNET DRIVERS (skge/sky2)
M: Mirko Lindner <mlindner@marvell.com>
@ -10525,6 +10526,7 @@ M: hariprasad <hkelam@marvell.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/ethernet/marvell/octeontx2/nic/
F: include/linux/soc/marvell/octeontx2/
MARVELL OCTEONTX2 RVU ADMIN FUNCTION DRIVER
M: Sunil Goutham <sgoutham@marvell.com>

13
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
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@ -16,6 +16,7 @@
#include <linux/net_tstamp.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/timecounter.h>
#include <linux/soc/marvell/octeontx2/asm.h>
#include <mbox.h>
#include <npc.h>
@ -462,21 +463,9 @@ static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr)
return result;
}
static inline u64 otx2_lmt_flush(uint64_t addr)
{
u64 result = 0;
__asm__ volatile(".cpu generic+lse\n"
"ldeor xzr,%x[rf],[%[rs]]"
: [rf]"=r"(result)
: [rs]"r"(addr));
return result;
}
#else
#define otx2_write128(lo, hi, addr)
#define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; })
#define otx2_lmt_flush(addr) ({ 0; })
#endif
/* Alloc pointer from pool/aura */

29
include/linux/soc/marvell/octeontx2/asm.h Normal file
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@ -0,0 +1,29 @@
/* SPDX-License-Identifier: GPL-2.0-only
* Copyright (C) 2020 Marvell.
*/
#ifndef __SOC_OTX2_ASM_H
#define __SOC_OTX2_ASM_H
#if defined(CONFIG_ARM64)
/*
* otx2_lmt_flush is used for LMT store operation.
* On octeontx2 platform CPT instruction enqueue and
* NIX packet send are only possible via LMTST
* operations and it uses LDEOR instruction targeting
* the coprocessor address.
*/
#define otx2_lmt_flush(ioaddr) \
({ \
u64 result = 0; \
__asm__ volatile(".cpu generic+lse\n" \
"ldeor xzr, %x[rf], [%[rs]]" \
: [rf]"=r" (result) \
: [rs]"r" (ioaddr)); \
(result); \
})
#else
#define otx2_lmt_flush(ioaddr) ({ 0; })
#endif
#endif /* __SOC_OTX2_ASM_H */