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[ARM] MX35 devices support
The i.MX35 basically features the same peripherals as the i.MX31 with some differences: - The i.MX35 has a FEC ethernet controller - The NAND controller base addresses are different - The i.MX35 has only 3 UARTs Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -84,6 +84,7 @@ struct platform_device mxc_uart_device2 = {
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.num_resources = ARRAY_SIZE(uart2),
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};
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#ifdef CONFIG_ARCH_MX31
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static struct resource uart3[] = {
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{
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.start = UART4_BASE_ADDR,
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@ -121,6 +122,7 @@ struct platform_device mxc_uart_device4 = {
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.resource = uart4,
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.num_resources = ARRAY_SIZE(uart4),
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};
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#endif /* CONFIG_ARCH_MX31 */
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/* GPIO port description */
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static struct mxc_gpio_port imx_gpio_ports[] = {
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@ -166,8 +168,8 @@ struct platform_device mxc_w1_master_device = {
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static struct resource mxc_nand_resources[] = {
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{
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.start = NFC_BASE_ADDR,
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.end = NFC_BASE_ADDR + 0xfff,
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.start = 0, /* runtime dependent */
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.end = 0,
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.flags = IORESOURCE_MEM
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}, {
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.start = MXC_INT_NANDFC,
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@ -290,3 +292,40 @@ struct platform_device mx3_fb = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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#ifdef CONFIG_ARCH_MX35
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static struct resource mxc_fec_resources[] = {
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{
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.start = MXC_FEC_BASE_ADDR,
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.end = MXC_FEC_BASE_ADDR + 0xfff,
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.flags = IORESOURCE_MEM
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}, {
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.start = MXC_INT_FEC,
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.end = MXC_INT_FEC,
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.flags = IORESOURCE_IRQ
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},
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};
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struct platform_device mxc_fec_device = {
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.name = "fec",
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.id = 0,
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.num_resources = ARRAY_SIZE(mxc_fec_resources),
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.resource = mxc_fec_resources,
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};
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#endif
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static int mx3_devices_init(void)
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{
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if (cpu_is_mx31()) {
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mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
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mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
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}
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if (cpu_is_mx35()) {
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mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
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mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
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}
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return 0;
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}
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subsys_initcall(mx3_devices_init);
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@ -11,3 +11,4 @@ extern struct platform_device mxc_i2c_device1;
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extern struct platform_device mxc_i2c_device2;
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extern struct platform_device mx3_ipu;
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extern struct platform_device mx3_fb;
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extern struct platform_device mxc_fec_device;
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