mirror of
https://github.com/edk2-porting/linux-next.git
synced 2025-01-25 15:15:33 +08:00
Merge series "Add Renoir ACP driver" from Vijendar Mukunda <Vijendar.Mukunda@amd.com>:
This adds an ASoC driver for the ACP (Audio CoProcessor) block on AMD Renoir APUs. V3: - Changed PCI driver PM runtime sequence - Removed redundant code in Renoir machine driver V2: - Removed empty declaration of dai_ops - Removed SNDRV_PCM_INFO_BATCH flag - Defined Macros for delay and counter and corrected dma stop sequence. - Changed PCI driver pm runtime sequence - Removed redundant code Vijendar Mukunda (14): ASoC: amd: add Renoir ACP3x IP register header ASoC: amd: add Renoir ACP PCI driver ASoC: amd: add acp init/de-init functions ASoC: amd: create acp3x pdm platform device ASoC: amd: add ACP3x PDM platform driver ASoC: amd: irq handler changes for ACP3x PDM dma driver ASoC: amd: add acp3x pdm driver dma ops ASoC: amd: add ACP PDM DMA driver dai ops ASoC: amd: add Renoir ACP PCI driver PM ops ASoC: amd: add ACP PDM DMA driver pm ops ASoC: amd: enable Renoir acp3x drivers build ASoC: amd: create platform devices for Renoir ASoC: amd: RN machine driver using dmic ASoC: amd: enable build for RN machine driver sound/soc/amd/Kconfig | 13 + sound/soc/amd/Makefile | 1 + sound/soc/amd/renoir/Makefile | 7 + sound/soc/amd/renoir/acp3x-pdm-dma.c | 530 +++++++++++++++++++++ sound/soc/amd/renoir/acp3x-rn.c | 77 +++ sound/soc/amd/renoir/rn-pci-acp3x.c | 344 +++++++++++++ sound/soc/amd/renoir/rn_acp3x.h | 88 ++++ sound/soc/amd/renoir/rn_chip_offset_byte.h | 349 ++++++++++++++ 8 files changed, 1409 insertions(+) create mode 100644 sound/soc/amd/renoir/Makefile create mode 100644 sound/soc/amd/renoir/acp3x-pdm-dma.c create mode 100644 sound/soc/amd/renoir/acp3x-rn.c create mode 100644 sound/soc/amd/renoir/rn-pci-acp3x.c create mode 100644 sound/soc/amd/renoir/rn_acp3x.h create mode 100644 sound/soc/amd/renoir/rn_chip_offset_byte.h -- 2.26.2
This commit is contained in:
Mark Brown
commit
95325ab34c
@ -36,3 +36,16 @@ config SND_SOC_AMD_RV_RT5682_MACH
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depends on SND_SOC_AMD_ACP3x && I2C && CROS_EC
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help
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This option enables machine driver for RT5682 and MAX9835.
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config SND_SOC_AMD_RENOIR
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tristate "AMD Audio Coprocessor - Renoir support"
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depends on X86 && PCI
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help
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This option enables ACP support for Renoir platform
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config SND_SOC_AMD_RENOIR_MACH
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tristate "AMD Renoir support for DMIC"
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select SND_SOC_DMIC
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depends on SND_SOC_AMD_RENOIR
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help
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This option enables machine driver for DMIC
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@ -9,3 +9,4 @@ obj-$(CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH) += snd-soc-acp-da7219mx98357-mac
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obj-$(CONFIG_SND_SOC_AMD_CZ_RT5645_MACH) += snd-soc-acp-rt5645-mach.o
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obj-$(CONFIG_SND_SOC_AMD_ACP3x) += raven/
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obj-$(CONFIG_SND_SOC_AMD_RV_RT5682_MACH) += snd-soc-acp-rt5682-mach.o
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obj-$(CONFIG_SND_SOC_AMD_RENOIR) += renoir/
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7
sound/soc/amd/renoir/Makefile
Normal file
7
sound/soc/amd/renoir/Makefile
Normal file
@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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# Renoir platform Support
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snd-rn-pci-acp3x-objs := rn-pci-acp3x.o
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snd-acp3x-pdm-dma-objs := acp3x-pdm-dma.o
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obj-$(CONFIG_SND_SOC_AMD_RENOIR) += snd-rn-pci-acp3x.o
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obj-$(CONFIG_SND_SOC_AMD_RENOIR) += snd-acp3x-pdm-dma.o
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obj-$(CONFIG_SND_SOC_AMD_RENOIR_MACH) += acp3x-rn.o
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530
sound/soc/amd/renoir/acp3x-pdm-dma.c
Normal file
530
sound/soc/amd/renoir/acp3x-pdm-dma.c
Normal file
@ -0,0 +1,530 @@
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// SPDX-License-Identifier: GPL-2.0+
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//
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// AMD ALSA SoC PDM Driver
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//
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//Copyright 2020 Advanced Micro Devices, Inc.
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/pm_runtime.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include "rn_acp3x.h"
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#define DRV_NAME "acp_rn_pdm_dma"
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static const struct snd_pcm_hardware acp_pdm_hardware_capture = {
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.info = SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_BLOCK_TRANSFER |
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SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
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.formats = SNDRV_PCM_FMTBIT_S32_LE,
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_48000,
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.rate_min = 48000,
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.rate_max = 48000,
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.buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
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.period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
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.period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
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.periods_min = CAPTURE_MIN_NUM_PERIODS,
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.periods_max = CAPTURE_MAX_NUM_PERIODS,
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};
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static irqreturn_t pdm_irq_handler(int irq, void *dev_id)
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{
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struct pdm_dev_data *rn_pdm_data;
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u16 cap_flag;
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u32 val;
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rn_pdm_data = dev_id;
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if (!rn_pdm_data)
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return IRQ_NONE;
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cap_flag = 0;
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val = rn_readl(rn_pdm_data->acp_base + ACP_EXTERNAL_INTR_STAT);
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if ((val & BIT(PDM_DMA_STAT)) && rn_pdm_data->capture_stream) {
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rn_writel(BIT(PDM_DMA_STAT), rn_pdm_data->acp_base +
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ACP_EXTERNAL_INTR_STAT);
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snd_pcm_period_elapsed(rn_pdm_data->capture_stream);
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cap_flag = 1;
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}
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if (cap_flag)
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return IRQ_HANDLED;
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else
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return IRQ_NONE;
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}
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static void init_pdm_ring_buffer(u32 physical_addr,
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u32 buffer_size,
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u32 watermark_size,
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void __iomem *acp_base)
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{
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rn_writel(physical_addr, acp_base + ACP_WOV_RX_RINGBUFADDR);
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rn_writel(buffer_size, acp_base + ACP_WOV_RX_RINGBUFSIZE);
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rn_writel(watermark_size, acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
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rn_writel(0x01, acp_base + ACPAXI2AXI_ATU_CTRL);
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}
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static void config_pdm_stream_params(unsigned int ch_mask,
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void __iomem *acp_base)
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{
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rn_writel(ch_mask, acp_base + ACP_WOV_PDM_NO_OF_CHANNELS);
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rn_writel(PDM_DECIMATION_FACTOR, acp_base +
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ACP_WOV_PDM_DECIMATION_FACTOR);
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}
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static void enable_pdm_clock(void __iomem *acp_base)
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{
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u32 pdm_clk_enable, pdm_ctrl;
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pdm_clk_enable = ACP_PDM_CLK_FREQ_MASK;
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pdm_ctrl = 0x00;
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rn_writel(pdm_clk_enable, acp_base + ACP_WOV_CLK_CTRL);
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pdm_ctrl = rn_readl(acp_base + ACP_WOV_MISC_CTRL);
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pdm_ctrl |= ACP_WOV_MISC_CTRL_MASK;
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rn_writel(pdm_ctrl, acp_base + ACP_WOV_MISC_CTRL);
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}
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static void enable_pdm_interrupts(void __iomem *acp_base)
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{
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u32 ext_int_ctrl;
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ext_int_ctrl = rn_readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
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ext_int_ctrl |= PDM_DMA_INTR_MASK;
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rn_writel(ext_int_ctrl, acp_base + ACP_EXTERNAL_INTR_CNTL);
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}
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static void disable_pdm_interrupts(void __iomem *acp_base)
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{
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u32 ext_int_ctrl;
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ext_int_ctrl = rn_readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
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ext_int_ctrl |= ~PDM_DMA_INTR_MASK;
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rn_writel(ext_int_ctrl, acp_base + ACP_EXTERNAL_INTR_CNTL);
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}
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static bool check_pdm_dma_status(void __iomem *acp_base)
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{
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bool pdm_dma_status;
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u32 pdm_enable, pdm_dma_enable;
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pdm_dma_status = false;
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pdm_enable = rn_readl(acp_base + ACP_WOV_PDM_ENABLE);
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pdm_dma_enable = rn_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
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if ((pdm_enable & ACP_PDM_ENABLE) && (pdm_dma_enable &
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ACP_PDM_DMA_EN_STATUS))
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pdm_dma_status = true;
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return pdm_dma_status;
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}
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static int start_pdm_dma(void __iomem *acp_base)
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{
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u32 pdm_enable;
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u32 pdm_dma_enable;
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int timeout;
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pdm_enable = 0x01;
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pdm_dma_enable = 0x01;
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enable_pdm_clock(acp_base);
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rn_writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
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rn_writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
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pdm_dma_enable = 0x00;
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timeout = 0;
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while (++timeout < ACP_COUNTER) {
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pdm_dma_enable = rn_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
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if ((pdm_dma_enable & 0x02) == ACP_PDM_DMA_EN_STATUS)
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return 0;
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udelay(DELAY_US);
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}
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return -ETIMEDOUT;
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}
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static int stop_pdm_dma(void __iomem *acp_base)
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{
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u32 pdm_enable, pdm_dma_enable, pdm_fifo_flush;
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int timeout;
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pdm_enable = 0x00;
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pdm_dma_enable = 0x00;
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pdm_fifo_flush = 0x00;
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pdm_enable = rn_readl(acp_base + ACP_WOV_PDM_ENABLE);
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pdm_dma_enable = rn_readl(acp_base + ACP_WOV_PDM_DMA_ENABLE);
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if (pdm_dma_enable & 0x01) {
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pdm_dma_enable = 0x02;
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rn_writel(pdm_dma_enable, acp_base + ACP_WOV_PDM_DMA_ENABLE);
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pdm_dma_enable = 0x00;
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timeout = 0;
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while (++timeout < ACP_COUNTER) {
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pdm_dma_enable = rn_readl(acp_base +
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ACP_WOV_PDM_DMA_ENABLE);
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if ((pdm_dma_enable & 0x02) == 0x00)
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break;
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udelay(DELAY_US);
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}
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if (timeout == ACP_COUNTER)
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return -ETIMEDOUT;
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}
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if (pdm_enable == ACP_PDM_ENABLE) {
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pdm_enable = ACP_PDM_DISABLE;
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rn_writel(pdm_enable, acp_base + ACP_WOV_PDM_ENABLE);
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}
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rn_writel(0x01, acp_base + ACP_WOV_PDM_FIFO_FLUSH);
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return 0;
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}
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static void config_acp_dma(struct pdm_stream_instance *rtd, int direction)
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{
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u16 page_idx;
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u32 low, high, val;
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dma_addr_t addr;
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addr = rtd->dma_addr;
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val = 0;
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/* Group Enable */
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rn_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp_base +
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ACPAXI2AXI_ATU_BASE_ADDR_GRP_1);
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rn_writel(PAGE_SIZE_4K_ENABLE, rtd->acp_base +
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ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1);
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for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) {
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/* Load the low address of page int ACP SRAM through SRBM */
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low = lower_32_bits(addr);
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high = upper_32_bits(addr);
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rn_writel(low, rtd->acp_base + ACP_SCRATCH_REG_0 + val);
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high |= BIT(31);
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rn_writel(high, rtd->acp_base + ACP_SCRATCH_REG_0 + val + 4);
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val += 8;
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addr += PAGE_SIZE;
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}
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}
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static int acp_pdm_dma_open(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime;
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struct pdm_dev_data *adata;
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struct pdm_stream_instance *pdm_data;
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int ret;
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runtime = substream->runtime;
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adata = dev_get_drvdata(component->dev);
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pdm_data = kzalloc(sizeof(*pdm_data), GFP_KERNEL);
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if (!pdm_data)
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return -EINVAL;
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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runtime->hw = acp_pdm_hardware_capture;
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ret = snd_pcm_hw_constraint_integer(runtime,
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SNDRV_PCM_HW_PARAM_PERIODS);
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if (ret < 0) {
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dev_err(component->dev, "set integer constraint failed\n");
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kfree(pdm_data);
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return ret;
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}
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enable_pdm_interrupts(adata->acp_base);
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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adata->capture_stream = substream;
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pdm_data->acp_base = adata->acp_base;
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runtime->private_data = pdm_data;
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return ret;
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}
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static int acp_pdm_dma_hw_params(struct snd_soc_component *component,
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struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct pdm_stream_instance *rtd;
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size_t size, period_bytes;
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rtd = substream->runtime->private_data;
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if (!rtd)
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return -EINVAL;
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size = params_buffer_bytes(params);
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period_bytes = params_period_bytes(params);
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rtd->dma_addr = substream->dma_buffer.addr;
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rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT);
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config_acp_dma(rtd, substream->stream);
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init_pdm_ring_buffer(MEM_WINDOW_START, size, period_bytes,
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rtd->acp_base);
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return 0;
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}
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static u64 acp_pdm_get_byte_count(struct pdm_stream_instance *rtd,
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int direction)
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{
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union acp_pdm_dma_count byte_count;
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byte_count.bcount.high =
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rn_readl(rtd->acp_base +
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ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
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byte_count.bcount.low =
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rn_readl(rtd->acp_base +
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ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
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return byte_count.bytescount;
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}
|
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|
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static snd_pcm_uframes_t acp_pdm_dma_pointer(struct snd_soc_component *comp,
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struct snd_pcm_substream *stream)
|
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{
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struct pdm_stream_instance *rtd;
|
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u32 pos, buffersize;
|
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u64 bytescount;
|
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|
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rtd = stream->runtime->private_data;
|
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buffersize = frames_to_bytes(stream->runtime,
|
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stream->runtime->buffer_size);
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bytescount = acp_pdm_get_byte_count(rtd, stream->stream);
|
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if (bytescount > rtd->bytescount)
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bytescount -= rtd->bytescount;
|
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pos = do_div(bytescount, buffersize);
|
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return bytes_to_frames(stream->runtime, pos);
|
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}
|
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|
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static int acp_pdm_dma_new(struct snd_soc_component *component,
|
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struct snd_soc_pcm_runtime *rtd)
|
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{
|
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struct device *parent = component->dev->parent;
|
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|
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snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
|
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parent, MIN_BUFFER, MAX_BUFFER);
|
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return 0;
|
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}
|
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|
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static int acp_pdm_dma_mmap(struct snd_soc_component *component,
|
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struct snd_pcm_substream *substream,
|
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struct vm_area_struct *vma)
|
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{
|
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return snd_pcm_lib_default_mmap(substream, vma);
|
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}
|
||||
|
||||
static int acp_pdm_dma_close(struct snd_soc_component *component,
|
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struct snd_pcm_substream *substream)
|
||||
{
|
||||
struct pdm_dev_data *adata = dev_get_drvdata(component->dev);
|
||||
|
||||
disable_pdm_interrupts(adata->acp_base);
|
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adata->capture_stream = NULL;
|
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return 0;
|
||||
}
|
||||
|
||||
static int acp_pdm_dai_hw_params(struct snd_pcm_substream *substream,
|
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struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct pdm_stream_instance *rtd;
|
||||
unsigned int ch_mask;
|
||||
|
||||
rtd = substream->runtime->private_data;
|
||||
switch (params_channels(params)) {
|
||||
case TWO_CH:
|
||||
default:
|
||||
ch_mask = 0x00;
|
||||
break;
|
||||
}
|
||||
config_pdm_stream_params(ch_mask, rtd->acp_base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int acp_pdm_dai_trigger(struct snd_pcm_substream *substream,
|
||||
int cmd, struct snd_soc_dai *dai)
|
||||
{
|
||||
struct pdm_stream_instance *rtd;
|
||||
int ret;
|
||||
bool pdm_status;
|
||||
|
||||
rtd = substream->runtime->private_data;
|
||||
ret = 0;
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
rtd->bytescount = acp_pdm_get_byte_count(rtd,
|
||||
substream->stream);
|
||||
pdm_status = check_pdm_dma_status(rtd->acp_base);
|
||||
if (!pdm_status)
|
||||
ret = start_pdm_dma(rtd->acp_base);
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
pdm_status = check_pdm_dma_status(rtd->acp_base);
|
||||
if (pdm_status)
|
||||
ret = stop_pdm_dma(rtd->acp_base);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct snd_soc_dai_ops acp_pdm_dai_ops = {
|
||||
.hw_params = acp_pdm_dai_hw_params,
|
||||
.trigger = acp_pdm_dai_trigger,
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_driver acp_pdm_dai_driver = {
|
||||
.capture = {
|
||||
.rates = SNDRV_PCM_RATE_48000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S24_LE |
|
||||
SNDRV_PCM_FMTBIT_S32_LE,
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rate_min = 48000,
|
||||
.rate_max = 48000,
|
||||
},
|
||||
.ops = &acp_pdm_dai_ops,
|
||||
};
|
||||
|
||||
static const struct snd_soc_component_driver acp_pdm_component = {
|
||||
.name = DRV_NAME,
|
||||
.open = acp_pdm_dma_open,
|
||||
.close = acp_pdm_dma_close,
|
||||
.hw_params = acp_pdm_dma_hw_params,
|
||||
.pointer = acp_pdm_dma_pointer,
|
||||
.mmap = acp_pdm_dma_mmap,
|
||||
.pcm_construct = acp_pdm_dma_new,
|
||||
};
|
||||
|
||||
static int acp_pdm_audio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct pdm_dev_data *adata;
|
||||
unsigned int irqflags;
|
||||
int status;
|
||||
|
||||
if (!pdev->dev.platform_data) {
|
||||
dev_err(&pdev->dev, "platform_data not retrieved\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
irqflags = *((unsigned int *)(pdev->dev.platform_data));
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "IORESOURCE_MEM FAILED\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
adata = devm_kzalloc(&pdev->dev, sizeof(*adata), GFP_KERNEL);
|
||||
if (!adata)
|
||||
return -ENOMEM;
|
||||
|
||||
adata->acp_base = devm_ioremap(&pdev->dev, res->start,
|
||||
resource_size(res));
|
||||
if (!adata->acp_base)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
adata->pdm_irq = res->start;
|
||||
adata->capture_stream = NULL;
|
||||
|
||||
dev_set_drvdata(&pdev->dev, adata);
|
||||
status = devm_snd_soc_register_component(&pdev->dev,
|
||||
&acp_pdm_component,
|
||||
&acp_pdm_dai_driver, 1);
|
||||
if (status) {
|
||||
dev_err(&pdev->dev, "Fail to register acp pdm dai\n");
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
status = devm_request_irq(&pdev->dev, adata->pdm_irq, pdm_irq_handler,
|
||||
irqflags, "ACP_PDM_IRQ", adata);
|
||||
if (status) {
|
||||
dev_err(&pdev->dev, "ACP PDM IRQ request failed\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
pm_runtime_set_autosuspend_delay(&pdev->dev, ACP_SUSPEND_DELAY_MS);
|
||||
pm_runtime_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_allow(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int acp_pdm_audio_remove(struct platform_device *pdev)
|
||||
{
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int acp_pdm_resume(struct device *dev)
|
||||
{
|
||||
struct pdm_dev_data *adata;
|
||||
struct snd_pcm_runtime *runtime;
|
||||
struct pdm_stream_instance *rtd;
|
||||
u32 period_bytes, buffer_len;
|
||||
|
||||
adata = dev_get_drvdata(dev);
|
||||
if (adata->capture_stream && adata->capture_stream->runtime) {
|
||||
runtime = adata->capture_stream->runtime;
|
||||
rtd = runtime->private_data;
|
||||
period_bytes = frames_to_bytes(runtime, runtime->period_size);
|
||||
buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
|
||||
config_acp_dma(rtd, SNDRV_PCM_STREAM_CAPTURE);
|
||||
init_pdm_ring_buffer(MEM_WINDOW_START, buffer_len, period_bytes,
|
||||
adata->acp_base);
|
||||
}
|
||||
enable_pdm_interrupts(adata->acp_base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int acp_pdm_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct pdm_dev_data *adata;
|
||||
|
||||
adata = dev_get_drvdata(dev);
|
||||
disable_pdm_interrupts(adata->acp_base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int acp_pdm_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct pdm_dev_data *adata;
|
||||
|
||||
adata = dev_get_drvdata(dev);
|
||||
enable_pdm_interrupts(adata->acp_base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops acp_pdm_pm_ops = {
|
||||
.runtime_suspend = acp_pdm_runtime_suspend,
|
||||
.runtime_resume = acp_pdm_runtime_resume,
|
||||
.resume = acp_pdm_resume,
|
||||
};
|
||||
|
||||
static struct platform_driver acp_pdm_dma_driver = {
|
||||
.probe = acp_pdm_audio_probe,
|
||||
.remove = acp_pdm_audio_remove,
|
||||
.driver = {
|
||||
.name = "acp_rn_pdm_dma",
|
||||
.pm = &acp_pdm_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(acp_pdm_dma_driver);
|
||||
|
||||
MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
|
||||
MODULE_DESCRIPTION("AMD ACP3x Renior PDM Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
77
sound/soc/amd/renoir/acp3x-rn.c
Normal file
77
sound/soc/amd/renoir/acp3x-rn.c
Normal file
@ -0,0 +1,77 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// Machine driver for AMD Renoir platform using DMIC
|
||||
//
|
||||
//Copyright 2020 Advanced Micro Devices, Inc.
|
||||
|
||||
#include <sound/soc.h>
|
||||
#include <sound/soc-dapm.h>
|
||||
#include <linux/module.h>
|
||||
#include <sound/pcm.h>
|
||||
#include <sound/pcm_params.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "rn_acp3x.h"
|
||||
|
||||
#define DRV_NAME "acp_pdm_mach"
|
||||
|
||||
SND_SOC_DAILINK_DEF(acp_pdm,
|
||||
DAILINK_COMP_ARRAY(COMP_CPU("acp_rn_pdm_dma.0")));
|
||||
|
||||
SND_SOC_DAILINK_DEF(dmic_codec,
|
||||
DAILINK_COMP_ARRAY(COMP_CODEC("dmic-codec.0",
|
||||
"dmic-hifi")));
|
||||
|
||||
SND_SOC_DAILINK_DEF(platform,
|
||||
DAILINK_COMP_ARRAY(COMP_PLATFORM("acp_rn_pdm_dma.0")));
|
||||
|
||||
static struct snd_soc_dai_link acp_dai_pdm[] = {
|
||||
{
|
||||
.name = "acp3x-dmic-capture",
|
||||
.stream_name = "DMIC capture",
|
||||
.capture_only = 1,
|
||||
SND_SOC_DAILINK_REG(acp_pdm, dmic_codec, platform),
|
||||
},
|
||||
};
|
||||
|
||||
static struct snd_soc_card acp_card = {
|
||||
.name = "acp",
|
||||
.owner = THIS_MODULE,
|
||||
.dai_link = acp_dai_pdm,
|
||||
.num_links = 1,
|
||||
};
|
||||
|
||||
static int acp_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct acp_pdm *machine = NULL;
|
||||
struct snd_soc_card *card;
|
||||
|
||||
card = &acp_card;
|
||||
acp_card.dev = &pdev->dev;
|
||||
|
||||
platform_set_drvdata(pdev, card);
|
||||
snd_soc_card_set_drvdata(card, machine);
|
||||
ret = devm_snd_soc_register_card(&pdev->dev, card);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
"snd_soc_register_card(%s) failed: %d\n",
|
||||
acp_card.name, ret);
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver acp_mach_driver = {
|
||||
.driver = {
|
||||
.name = "acp_pdm_mach",
|
||||
.pm = &snd_soc_pm_ops,
|
||||
},
|
||||
.probe = acp_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(acp_mach_driver);
|
||||
|
||||
MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:" DRV_NAME);
|
||||
344
sound/soc/amd/renoir/rn-pci-acp3x.c
Normal file
344
sound/soc/amd/renoir/rn-pci-acp3x.c
Normal file
@ -0,0 +1,344 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// AMD Renoir ACP PCI Driver
|
||||
//
|
||||
//Copyright 2020 Advanced Micro Devices, Inc.
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#include "rn_acp3x.h"
|
||||
|
||||
static int acp_power_gating;
|
||||
module_param(acp_power_gating, int, 0644);
|
||||
MODULE_PARM_DESC(acp_power_gating, "Enable acp power gating");
|
||||
|
||||
struct acp_dev_data {
|
||||
void __iomem *acp_base;
|
||||
struct resource *res;
|
||||
struct platform_device *pdev[ACP_DEVS];
|
||||
};
|
||||
|
||||
static int rn_acp_power_on(void __iomem *acp_base)
|
||||
{
|
||||
u32 val;
|
||||
int timeout;
|
||||
|
||||
val = rn_readl(acp_base + ACP_PGFSM_STATUS);
|
||||
|
||||
if (val == 0)
|
||||
return val;
|
||||
|
||||
if ((val & ACP_PGFSM_STATUS_MASK) !=
|
||||
ACP_POWER_ON_IN_PROGRESS)
|
||||
rn_writel(ACP_PGFSM_CNTL_POWER_ON_MASK,
|
||||
acp_base + ACP_PGFSM_CONTROL);
|
||||
timeout = 0;
|
||||
while (++timeout < 500) {
|
||||
val = rn_readl(acp_base + ACP_PGFSM_STATUS);
|
||||
if (!val)
|
||||
return 0;
|
||||
udelay(1);
|
||||
}
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static int rn_acp_power_off(void __iomem *acp_base)
|
||||
{
|
||||
u32 val;
|
||||
int timeout;
|
||||
|
||||
rn_writel(ACP_PGFSM_CNTL_POWER_OFF_MASK,
|
||||
acp_base + ACP_PGFSM_CONTROL);
|
||||
timeout = 0;
|
||||
while (++timeout < 500) {
|
||||
val = rn_readl(acp_base + ACP_PGFSM_STATUS);
|
||||
if ((val & ACP_PGFSM_STATUS_MASK) == ACP_POWERED_OFF)
|
||||
return 0;
|
||||
udelay(1);
|
||||
}
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static int rn_acp_reset(void __iomem *acp_base)
|
||||
{
|
||||
u32 val;
|
||||
int timeout;
|
||||
|
||||
rn_writel(1, acp_base + ACP_SOFT_RESET);
|
||||
timeout = 0;
|
||||
while (++timeout < 500) {
|
||||
val = rn_readl(acp_base + ACP_SOFT_RESET);
|
||||
if (val & ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK)
|
||||
break;
|
||||
cpu_relax();
|
||||
}
|
||||
rn_writel(0, acp_base + ACP_SOFT_RESET);
|
||||
timeout = 0;
|
||||
while (++timeout < 500) {
|
||||
val = rn_readl(acp_base + ACP_SOFT_RESET);
|
||||
if (!val)
|
||||
return 0;
|
||||
cpu_relax();
|
||||
}
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static void rn_acp_enable_interrupts(void __iomem *acp_base)
|
||||
{
|
||||
u32 ext_intr_ctrl;
|
||||
|
||||
rn_writel(0x01, acp_base + ACP_EXTERNAL_INTR_ENB);
|
||||
ext_intr_ctrl = rn_readl(acp_base + ACP_EXTERNAL_INTR_CNTL);
|
||||
ext_intr_ctrl |= ACP_ERROR_MASK;
|
||||
rn_writel(ext_intr_ctrl, acp_base + ACP_EXTERNAL_INTR_CNTL);
|
||||
}
|
||||
|
||||
static void rn_acp_disable_interrupts(void __iomem *acp_base)
|
||||
{
|
||||
rn_writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base +
|
||||
ACP_EXTERNAL_INTR_STAT);
|
||||
rn_writel(0x00, acp_base + ACP_EXTERNAL_INTR_ENB);
|
||||
}
|
||||
|
||||
static int rn_acp_init(void __iomem *acp_base)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* power on */
|
||||
ret = rn_acp_power_on(acp_base);
|
||||
if (ret) {
|
||||
pr_err("ACP power on failed\n");
|
||||
return ret;
|
||||
}
|
||||
rn_writel(0x01, acp_base + ACP_CONTROL);
|
||||
/* Reset */
|
||||
ret = rn_acp_reset(acp_base);
|
||||
if (ret) {
|
||||
pr_err("ACP reset failed\n");
|
||||
return ret;
|
||||
}
|
||||
rn_writel(0x03, acp_base + ACP_CLKMUX_SEL);
|
||||
rn_acp_enable_interrupts(acp_base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rn_acp_deinit(void __iomem *acp_base)
|
||||
{
|
||||
int ret;
|
||||
|
||||
rn_acp_disable_interrupts(acp_base);
|
||||
/* Reset */
|
||||
ret = rn_acp_reset(acp_base);
|
||||
if (ret) {
|
||||
pr_err("ACP reset failed\n");
|
||||
return ret;
|
||||
}
|
||||
rn_writel(0x00, acp_base + ACP_CLKMUX_SEL);
|
||||
rn_writel(0x00, acp_base + ACP_CONTROL);
|
||||
/* power off */
|
||||
if (acp_power_gating) {
|
||||
ret = rn_acp_power_off(acp_base);
|
||||
if (ret) {
|
||||
pr_err("ACP power off failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int snd_rn_acp_probe(struct pci_dev *pci,
|
||||
const struct pci_device_id *pci_id)
|
||||
{
|
||||
struct acp_dev_data *adata;
|
||||
struct platform_device_info pdevinfo[ACP_DEVS];
|
||||
unsigned int irqflags;
|
||||
int ret, index;
|
||||
u32 addr;
|
||||
|
||||
if (pci_enable_device(pci)) {
|
||||
dev_err(&pci->dev, "pci_enable_device failed\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = pci_request_regions(pci, "AMD ACP3x audio");
|
||||
if (ret < 0) {
|
||||
dev_err(&pci->dev, "pci_request_regions failed\n");
|
||||
goto disable_pci;
|
||||
}
|
||||
|
||||
adata = devm_kzalloc(&pci->dev, sizeof(struct acp_dev_data),
|
||||
GFP_KERNEL);
|
||||
if (!adata) {
|
||||
ret = -ENOMEM;
|
||||
goto release_regions;
|
||||
}
|
||||
|
||||
/* check for msi interrupt support */
|
||||
ret = pci_enable_msi(pci);
|
||||
if (ret)
|
||||
/* msi is not enabled */
|
||||
irqflags = IRQF_SHARED;
|
||||
else
|
||||
/* msi is enabled */
|
||||
irqflags = 0;
|
||||
|
||||
addr = pci_resource_start(pci, 0);
|
||||
adata->acp_base = devm_ioremap(&pci->dev, addr,
|
||||
pci_resource_len(pci, 0));
|
||||
if (!adata->acp_base) {
|
||||
ret = -ENOMEM;
|
||||
goto disable_msi;
|
||||
}
|
||||
pci_set_master(pci);
|
||||
pci_set_drvdata(pci, adata);
|
||||
ret = rn_acp_init(adata->acp_base);
|
||||
if (ret)
|
||||
goto disable_msi;
|
||||
|
||||
adata->res = devm_kzalloc(&pci->dev,
|
||||
sizeof(struct resource) * 2,
|
||||
GFP_KERNEL);
|
||||
if (!adata->res) {
|
||||
ret = -ENOMEM;
|
||||
goto de_init;
|
||||
}
|
||||
|
||||
adata->res[0].name = "acp_pdm_iomem";
|
||||
adata->res[0].flags = IORESOURCE_MEM;
|
||||
adata->res[0].start = addr;
|
||||
adata->res[0].end = addr + (ACP_REG_END - ACP_REG_START);
|
||||
adata->res[1].name = "acp_pdm_irq";
|
||||
adata->res[1].flags = IORESOURCE_IRQ;
|
||||
adata->res[1].start = pci->irq;
|
||||
adata->res[1].end = pci->irq;
|
||||
|
||||
memset(&pdevinfo, 0, sizeof(pdevinfo));
|
||||
pdevinfo[0].name = "acp_rn_pdm_dma";
|
||||
pdevinfo[0].id = 0;
|
||||
pdevinfo[0].parent = &pci->dev;
|
||||
pdevinfo[0].num_res = 2;
|
||||
pdevinfo[0].res = adata->res;
|
||||
pdevinfo[0].data = &irqflags;
|
||||
pdevinfo[0].size_data = sizeof(irqflags);
|
||||
|
||||
pdevinfo[1].name = "dmic-codec";
|
||||
pdevinfo[1].id = 0;
|
||||
pdevinfo[1].parent = &pci->dev;
|
||||
pdevinfo[2].name = "acp_pdm_mach";
|
||||
pdevinfo[2].id = 0;
|
||||
pdevinfo[2].parent = &pci->dev;
|
||||
for (index = 0; index < ACP_DEVS; index++) {
|
||||
adata->pdev[index] =
|
||||
platform_device_register_full(&pdevinfo[index]);
|
||||
if (IS_ERR(adata->pdev[index])) {
|
||||
dev_err(&pci->dev, "cannot register %s device\n",
|
||||
pdevinfo[index].name);
|
||||
ret = PTR_ERR(adata->pdev[index]);
|
||||
goto unregister_devs;
|
||||
}
|
||||
}
|
||||
pm_runtime_set_autosuspend_delay(&pci->dev, ACP_SUSPEND_DELAY_MS);
|
||||
pm_runtime_use_autosuspend(&pci->dev);
|
||||
pm_runtime_put_noidle(&pci->dev);
|
||||
pm_runtime_allow(&pci->dev);
|
||||
return 0;
|
||||
|
||||
unregister_devs:
|
||||
for (index = 0; index < ACP_DEVS; index++)
|
||||
platform_device_unregister(adata->pdev[index]);
|
||||
de_init:
|
||||
if (rn_acp_deinit(adata->acp_base))
|
||||
dev_err(&pci->dev, "ACP de-init failed\n");
|
||||
disable_msi:
|
||||
pci_disable_msi(pci);
|
||||
release_regions:
|
||||
pci_release_regions(pci);
|
||||
disable_pci:
|
||||
pci_disable_device(pci);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int snd_rn_acp_suspend(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
struct acp_dev_data *adata;
|
||||
|
||||
adata = dev_get_drvdata(dev);
|
||||
ret = rn_acp_deinit(adata->acp_base);
|
||||
if (ret)
|
||||
dev_err(dev, "ACP de-init failed\n");
|
||||
else
|
||||
dev_dbg(dev, "ACP de-initialized\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int snd_rn_acp_resume(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
struct acp_dev_data *adata;
|
||||
|
||||
adata = dev_get_drvdata(dev);
|
||||
ret = rn_acp_init(adata->acp_base);
|
||||
if (ret) {
|
||||
dev_err(dev, "ACP init failed\n");
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops rn_acp_pm = {
|
||||
.runtime_suspend = snd_rn_acp_suspend,
|
||||
.runtime_resume = snd_rn_acp_resume,
|
||||
.suspend = snd_rn_acp_suspend,
|
||||
.resume = snd_rn_acp_resume,
|
||||
};
|
||||
|
||||
static void snd_rn_acp_remove(struct pci_dev *pci)
|
||||
{
|
||||
struct acp_dev_data *adata;
|
||||
int ret, index;
|
||||
|
||||
adata = pci_get_drvdata(pci);
|
||||
for (index = 0; index < ACP_DEVS; index++)
|
||||
platform_device_unregister(adata->pdev[index]);
|
||||
ret = rn_acp_deinit(adata->acp_base);
|
||||
if (ret)
|
||||
dev_err(&pci->dev, "ACP de-init failed\n");
|
||||
pm_runtime_forbid(&pci->dev);
|
||||
pm_runtime_get_noresume(&pci->dev);
|
||||
pci_disable_msi(pci);
|
||||
pci_release_regions(pci);
|
||||
pci_disable_device(pci);
|
||||
}
|
||||
|
||||
static const struct pci_device_id snd_rn_acp_ids[] = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_DEVICE_ID),
|
||||
.class = PCI_CLASS_MULTIMEDIA_OTHER << 8,
|
||||
.class_mask = 0xffffff },
|
||||
{ 0, },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, snd_rn_acp_ids);
|
||||
|
||||
static struct pci_driver rn_acp_driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.id_table = snd_rn_acp_ids,
|
||||
.probe = snd_rn_acp_probe,
|
||||
.remove = snd_rn_acp_remove,
|
||||
.driver = {
|
||||
.pm = &rn_acp_pm,
|
||||
}
|
||||
};
|
||||
|
||||
module_pci_driver(rn_acp_driver);
|
||||
|
||||
MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
|
||||
MODULE_DESCRIPTION("AMD ACP Renoir PCI driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
88
sound/soc/amd/renoir/rn_acp3x.h
Normal file
88
sound/soc/amd/renoir/rn_acp3x.h
Normal file
@ -0,0 +1,88 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* AMD ALSA SoC PDM Driver
|
||||
*
|
||||
* Copyright 2020 Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
#include "rn_chip_offset_byte.h"
|
||||
|
||||
#define ACP_DEVS 3
|
||||
#define ACP_PHY_BASE_ADDRESS 0x1240000
|
||||
#define ACP_REG_START 0x1240000
|
||||
#define ACP_REG_END 0x1250200
|
||||
|
||||
#define ACP_DEVICE_ID 0x15E2
|
||||
#define ACP_POWER_ON 0x00
|
||||
#define ACP_POWER_ON_IN_PROGRESS 0x01
|
||||
#define ACP_POWER_OFF 0x02
|
||||
#define ACP_POWER_OFF_IN_PROGRESS 0x03
|
||||
#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
|
||||
|
||||
#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
|
||||
#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
|
||||
#define ACP_PGFSM_STATUS_MASK 0x03
|
||||
#define ACP_POWERED_ON 0x00
|
||||
#define ACP_POWER_ON_IN_PROGRESS 0x01
|
||||
#define ACP_POWERED_OFF 0x02
|
||||
#define ACP_POWER_OFF_IN_PROGRESS 0x03
|
||||
|
||||
#define ACP_ERROR_MASK 0x20000000
|
||||
#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
|
||||
#define PDM_DMA_STAT 0x10
|
||||
#define PDM_DMA_INTR_MASK 0x10000
|
||||
#define ACP_ERROR_STAT 29
|
||||
#define PDM_DECIMATION_FACTOR 0x2
|
||||
#define ACP_PDM_CLK_FREQ_MASK 0x07
|
||||
#define ACP_WOV_MISC_CTRL_MASK 0x10
|
||||
#define ACP_PDM_ENABLE 0x01
|
||||
#define ACP_PDM_DISABLE 0x00
|
||||
#define ACP_PDM_DMA_EN_STATUS 0x02
|
||||
#define TWO_CH 0x02
|
||||
#define DELAY_US 5
|
||||
#define ACP_COUNTER 20000
|
||||
/* time in ms for runtime suspend delay */
|
||||
#define ACP_SUSPEND_DELAY_MS 2000
|
||||
|
||||
#define ACP_SRAM_PTE_OFFSET 0x02050000
|
||||
#define PAGE_SIZE_4K_ENABLE 0x2
|
||||
#define MEM_WINDOW_START 0x4000000
|
||||
|
||||
#define CAPTURE_MIN_NUM_PERIODS 4
|
||||
#define CAPTURE_MAX_NUM_PERIODS 4
|
||||
#define CAPTURE_MAX_PERIOD_SIZE 8192
|
||||
#define CAPTURE_MIN_PERIOD_SIZE 4096
|
||||
|
||||
#define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
|
||||
#define MIN_BUFFER MAX_BUFFER
|
||||
struct pdm_dev_data {
|
||||
u32 pdm_irq;
|
||||
void __iomem *acp_base;
|
||||
struct snd_pcm_substream *capture_stream;
|
||||
};
|
||||
|
||||
struct pdm_stream_instance {
|
||||
u16 num_pages;
|
||||
u16 channels;
|
||||
dma_addr_t dma_addr;
|
||||
u64 bytescount;
|
||||
void __iomem *acp_base;
|
||||
};
|
||||
|
||||
union acp_pdm_dma_count {
|
||||
struct {
|
||||
u32 low;
|
||||
u32 high;
|
||||
} bcount;
|
||||
u64 bytescount;
|
||||
};
|
||||
|
||||
static inline u32 rn_readl(void __iomem *base_addr)
|
||||
{
|
||||
return readl(base_addr - ACP_PHY_BASE_ADDRESS);
|
||||
}
|
||||
|
||||
static inline void rn_writel(u32 val, void __iomem *base_addr)
|
||||
{
|
||||
writel(val, base_addr - ACP_PHY_BASE_ADDRESS);
|
||||
}
|
||||
349
sound/soc/amd/renoir/rn_chip_offset_byte.h
Normal file
349
sound/soc/amd/renoir/rn_chip_offset_byte.h
Normal file
@ -0,0 +1,349 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* AMD ACP 3.1 Register Documentation
|
||||
*
|
||||
* Copyright 2020 Advanced Micro Devices, Inc.
|
||||
*/
|
||||
|
||||
#ifndef _rn_OFFSET_HEADER
|
||||
#define _rn_OFFSET_HEADER
|
||||
// Registers from ACP_DMA block
|
||||
|
||||
#define ACP_DMA_CNTL_0 0x1240000
|
||||
#define ACP_DMA_CNTL_1 0x1240004
|
||||
#define ACP_DMA_CNTL_2 0x1240008
|
||||
#define ACP_DMA_CNTL_3 0x124000C
|
||||
#define ACP_DMA_CNTL_4 0x1240010
|
||||
#define ACP_DMA_CNTL_5 0x1240014
|
||||
#define ACP_DMA_CNTL_6 0x1240018
|
||||
#define ACP_DMA_CNTL_7 0x124001C
|
||||
#define ACP_DMA_DSCR_STRT_IDX_0 0x1240020
|
||||
#define ACP_DMA_DSCR_STRT_IDX_1 0x1240024
|
||||
#define ACP_DMA_DSCR_STRT_IDX_2 0x1240028
|
||||
#define ACP_DMA_DSCR_STRT_IDX_3 0x124002C
|
||||
#define ACP_DMA_DSCR_STRT_IDX_4 0x1240030
|
||||
#define ACP_DMA_DSCR_STRT_IDX_5 0x1240034
|
||||
#define ACP_DMA_DSCR_STRT_IDX_6 0x1240038
|
||||
#define ACP_DMA_DSCR_STRT_IDX_7 0x124003C
|
||||
#define ACP_DMA_DSCR_CNT_0 0x1240040
|
||||
#define ACP_DMA_DSCR_CNT_1 0x1240044
|
||||
#define ACP_DMA_DSCR_CNT_2 0x1240048
|
||||
#define ACP_DMA_DSCR_CNT_3 0x124004C
|
||||
#define ACP_DMA_DSCR_CNT_4 0x1240050
|
||||
#define ACP_DMA_DSCR_CNT_5 0x1240054
|
||||
#define ACP_DMA_DSCR_CNT_6 0x1240058
|
||||
#define ACP_DMA_DSCR_CNT_7 0x124005C
|
||||
#define ACP_DMA_PRIO_0 0x1240060
|
||||
#define ACP_DMA_PRIO_1 0x1240064
|
||||
#define ACP_DMA_PRIO_2 0x1240068
|
||||
#define ACP_DMA_PRIO_3 0x124006C
|
||||
#define ACP_DMA_PRIO_4 0x1240070
|
||||
#define ACP_DMA_PRIO_5 0x1240074
|
||||
#define ACP_DMA_PRIO_6 0x1240078
|
||||
#define ACP_DMA_PRIO_7 0x124007C
|
||||
#define ACP_DMA_CUR_DSCR_0 0x1240080
|
||||
#define ACP_DMA_CUR_DSCR_1 0x1240084
|
||||
#define ACP_DMA_CUR_DSCR_2 0x1240088
|
||||
#define ACP_DMA_CUR_DSCR_3 0x124008C
|
||||
#define ACP_DMA_CUR_DSCR_4 0x1240090
|
||||
#define ACP_DMA_CUR_DSCR_5 0x1240094
|
||||
#define ACP_DMA_CUR_DSCR_6 0x1240098
|
||||
#define ACP_DMA_CUR_DSCR_7 0x124009C
|
||||
#define ACP_DMA_CUR_TRANS_CNT_0 0x12400A0
|
||||
#define ACP_DMA_CUR_TRANS_CNT_1 0x12400A4
|
||||
#define ACP_DMA_CUR_TRANS_CNT_2 0x12400A8
|
||||
#define ACP_DMA_CUR_TRANS_CNT_3 0x12400AC
|
||||
#define ACP_DMA_CUR_TRANS_CNT_4 0x12400B0
|
||||
#define ACP_DMA_CUR_TRANS_CNT_5 0x12400B4
|
||||
#define ACP_DMA_CUR_TRANS_CNT_6 0x12400B8
|
||||
#define ACP_DMA_CUR_TRANS_CNT_7 0x12400BC
|
||||
#define ACP_DMA_ERR_STS_0 0x12400C0
|
||||
#define ACP_DMA_ERR_STS_1 0x12400C4
|
||||
#define ACP_DMA_ERR_STS_2 0x12400C8
|
||||
#define ACP_DMA_ERR_STS_3 0x12400CC
|
||||
#define ACP_DMA_ERR_STS_4 0x12400D0
|
||||
#define ACP_DMA_ERR_STS_5 0x12400D4
|
||||
#define ACP_DMA_ERR_STS_6 0x12400D8
|
||||
#define ACP_DMA_ERR_STS_7 0x12400DC
|
||||
#define ACP_DMA_DESC_BASE_ADDR 0x12400E0
|
||||
#define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E4
|
||||
#define ACP_DMA_CH_STS 0x12400E8
|
||||
#define ACP_DMA_CH_GROUP 0x12400EC
|
||||
#define ACP_DMA_CH_RST_STS 0x12400F0
|
||||
|
||||
// Registers from ACP_AXI2AXIATU block
|
||||
|
||||
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C00
|
||||
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C04
|
||||
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C08
|
||||
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C
|
||||
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C10
|
||||
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C14
|
||||
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C18
|
||||
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C
|
||||
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C20
|
||||
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C24
|
||||
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C28
|
||||
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C
|
||||
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C30
|
||||
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C34
|
||||
#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C38
|
||||
#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C
|
||||
#define ACPAXI2AXI_ATU_CTRL 0x1240C40
|
||||
|
||||
// Registers from ACP_CLKRST block
|
||||
|
||||
#define ACP_SOFT_RESET 0x1241000
|
||||
#define ACP_CONTROL 0x1241004
|
||||
#define ACP_STATUS 0x1241008
|
||||
#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010
|
||||
|
||||
// Registers from ACP_MISC block
|
||||
|
||||
#define ACP_EXTERNAL_INTR_ENB 0x1241800
|
||||
#define ACP_EXTERNAL_INTR_CNTL 0x1241804
|
||||
#define ACP_EXTERNAL_INTR_STAT 0x1241808
|
||||
#define ACP_PGMEM_CTRL 0x12418C0
|
||||
#define ACP_ERROR_STATUS 0x12418C4
|
||||
#define ACP_SW_I2S_ERROR_REASON 0x12418C8
|
||||
#define ACP_MEM_PG_STS 0x12418CC
|
||||
|
||||
// Registers from ACP_PGFSM block
|
||||
|
||||
#define ACP_I2S_PIN_CONFIG 0x1241400
|
||||
#define ACP_PAD_PULLUP_PULLDOWN_CTRL 0x1241404
|
||||
#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x1241408
|
||||
#define ACP_SW_PAD_KEEPER_EN 0x124140C
|
||||
#define ACP_PGFSM_CONTROL 0x124141C
|
||||
#define ACP_PGFSM_STATUS 0x1241420
|
||||
#define ACP_CLKMUX_SEL 0x1241424
|
||||
#define ACP_DEVICE_STATE 0x1241428
|
||||
#define AZ_DEVICE_STATE 0x124142C
|
||||
#define ACP_INTR_URGENCY_TIMER 0x1241430
|
||||
#define AZ_INTR_URGENCY_TIMER 0x1241434
|
||||
|
||||
// Registers from ACP_SCRATCH block
|
||||
|
||||
#define ACP_SCRATCH_REG_0 0x1250000
|
||||
#define ACP_SCRATCH_REG_1 0x1250004
|
||||
#define ACP_SCRATCH_REG_2 0x1250008
|
||||
#define ACP_SCRATCH_REG_3 0x125000C
|
||||
#define ACP_SCRATCH_REG_4 0x1250010
|
||||
#define ACP_SCRATCH_REG_5 0x1250014
|
||||
#define ACP_SCRATCH_REG_6 0x1250018
|
||||
#define ACP_SCRATCH_REG_7 0x125001C
|
||||
#define ACP_SCRATCH_REG_8 0x1250020
|
||||
#define ACP_SCRATCH_REG_9 0x1250024
|
||||
#define ACP_SCRATCH_REG_10 0x1250028
|
||||
#define ACP_SCRATCH_REG_11 0x125002C
|
||||
#define ACP_SCRATCH_REG_12 0x1250030
|
||||
#define ACP_SCRATCH_REG_13 0x1250034
|
||||
#define ACP_SCRATCH_REG_14 0x1250038
|
||||
#define ACP_SCRATCH_REG_15 0x125003C
|
||||
#define ACP_SCRATCH_REG_16 0x1250040
|
||||
#define ACP_SCRATCH_REG_17 0x1250044
|
||||
#define ACP_SCRATCH_REG_18 0x1250048
|
||||
#define ACP_SCRATCH_REG_19 0x125004C
|
||||
#define ACP_SCRATCH_REG_20 0x1250050
|
||||
#define ACP_SCRATCH_REG_21 0x1250054
|
||||
#define ACP_SCRATCH_REG_22 0x1250058
|
||||
#define ACP_SCRATCH_REG_23 0x125005C
|
||||
#define ACP_SCRATCH_REG_24 0x1250060
|
||||
#define ACP_SCRATCH_REG_25 0x1250064
|
||||
#define ACP_SCRATCH_REG_26 0x1250068
|
||||
#define ACP_SCRATCH_REG_27 0x125006C
|
||||
#define ACP_SCRATCH_REG_28 0x1250070
|
||||
#define ACP_SCRATCH_REG_29 0x1250074
|
||||
#define ACP_SCRATCH_REG_30 0x1250078
|
||||
#define ACP_SCRATCH_REG_31 0x125007C
|
||||
#define ACP_SCRATCH_REG_32 0x1250080
|
||||
#define ACP_SCRATCH_REG_33 0x1250084
|
||||
#define ACP_SCRATCH_REG_34 0x1250088
|
||||
#define ACP_SCRATCH_REG_35 0x125008C
|
||||
#define ACP_SCRATCH_REG_36 0x1250090
|
||||
#define ACP_SCRATCH_REG_37 0x1250094
|
||||
#define ACP_SCRATCH_REG_38 0x1250098
|
||||
#define ACP_SCRATCH_REG_39 0x125009C
|
||||
#define ACP_SCRATCH_REG_40 0x12500A0
|
||||
#define ACP_SCRATCH_REG_41 0x12500A4
|
||||
#define ACP_SCRATCH_REG_42 0x12500A8
|
||||
#define ACP_SCRATCH_REG_43 0x12500AC
|
||||
#define ACP_SCRATCH_REG_44 0x12500B0
|
||||
#define ACP_SCRATCH_REG_45 0x12500B4
|
||||
#define ACP_SCRATCH_REG_46 0x12500B8
|
||||
#define ACP_SCRATCH_REG_47 0x12500BC
|
||||
#define ACP_SCRATCH_REG_48 0x12500C0
|
||||
#define ACP_SCRATCH_REG_49 0x12500C4
|
||||
#define ACP_SCRATCH_REG_50 0x12500C8
|
||||
#define ACP_SCRATCH_REG_51 0x12500CC
|
||||
#define ACP_SCRATCH_REG_52 0x12500D0
|
||||
#define ACP_SCRATCH_REG_53 0x12500D4
|
||||
#define ACP_SCRATCH_REG_54 0x12500D8
|
||||
#define ACP_SCRATCH_REG_55 0x12500DC
|
||||
#define ACP_SCRATCH_REG_56 0x12500E0
|
||||
#define ACP_SCRATCH_REG_57 0x12500E4
|
||||
#define ACP_SCRATCH_REG_58 0x12500E8
|
||||
#define ACP_SCRATCH_REG_59 0x12500EC
|
||||
#define ACP_SCRATCH_REG_60 0x12500F0
|
||||
#define ACP_SCRATCH_REG_61 0x12500F4
|
||||
#define ACP_SCRATCH_REG_62 0x12500F8
|
||||
#define ACP_SCRATCH_REG_63 0x12500FC
|
||||
#define ACP_SCRATCH_REG_64 0x1250100
|
||||
#define ACP_SCRATCH_REG_65 0x1250104
|
||||
#define ACP_SCRATCH_REG_66 0x1250108
|
||||
#define ACP_SCRATCH_REG_67 0x125010C
|
||||
#define ACP_SCRATCH_REG_68 0x1250110
|
||||
#define ACP_SCRATCH_REG_69 0x1250114
|
||||
#define ACP_SCRATCH_REG_70 0x1250118
|
||||
#define ACP_SCRATCH_REG_71 0x125011C
|
||||
#define ACP_SCRATCH_REG_72 0x1250120
|
||||
#define ACP_SCRATCH_REG_73 0x1250124
|
||||
#define ACP_SCRATCH_REG_74 0x1250128
|
||||
#define ACP_SCRATCH_REG_75 0x125012C
|
||||
#define ACP_SCRATCH_REG_76 0x1250130
|
||||
#define ACP_SCRATCH_REG_77 0x1250134
|
||||
#define ACP_SCRATCH_REG_78 0x1250138
|
||||
#define ACP_SCRATCH_REG_79 0x125013C
|
||||
#define ACP_SCRATCH_REG_80 0x1250140
|
||||
#define ACP_SCRATCH_REG_81 0x1250144
|
||||
#define ACP_SCRATCH_REG_82 0x1250148
|
||||
#define ACP_SCRATCH_REG_83 0x125014C
|
||||
#define ACP_SCRATCH_REG_84 0x1250150
|
||||
#define ACP_SCRATCH_REG_85 0x1250154
|
||||
#define ACP_SCRATCH_REG_86 0x1250158
|
||||
#define ACP_SCRATCH_REG_87 0x125015C
|
||||
#define ACP_SCRATCH_REG_88 0x1250160
|
||||
#define ACP_SCRATCH_REG_89 0x1250164
|
||||
#define ACP_SCRATCH_REG_90 0x1250168
|
||||
#define ACP_SCRATCH_REG_91 0x125016C
|
||||
#define ACP_SCRATCH_REG_92 0x1250170
|
||||
#define ACP_SCRATCH_REG_93 0x1250174
|
||||
#define ACP_SCRATCH_REG_94 0x1250178
|
||||
#define ACP_SCRATCH_REG_95 0x125017C
|
||||
#define ACP_SCRATCH_REG_96 0x1250180
|
||||
#define ACP_SCRATCH_REG_97 0x1250184
|
||||
#define ACP_SCRATCH_REG_98 0x1250188
|
||||
#define ACP_SCRATCH_REG_99 0x125018C
|
||||
#define ACP_SCRATCH_REG_100 0x1250190
|
||||
#define ACP_SCRATCH_REG_101 0x1250194
|
||||
#define ACP_SCRATCH_REG_102 0x1250198
|
||||
#define ACP_SCRATCH_REG_103 0x125019C
|
||||
#define ACP_SCRATCH_REG_104 0x12501A0
|
||||
#define ACP_SCRATCH_REG_105 0x12501A4
|
||||
#define ACP_SCRATCH_REG_106 0x12501A8
|
||||
#define ACP_SCRATCH_REG_107 0x12501AC
|
||||
#define ACP_SCRATCH_REG_108 0x12501B0
|
||||
#define ACP_SCRATCH_REG_109 0x12501B4
|
||||
#define ACP_SCRATCH_REG_110 0x12501B8
|
||||
#define ACP_SCRATCH_REG_111 0x12501BC
|
||||
#define ACP_SCRATCH_REG_112 0x12501C0
|
||||
#define ACP_SCRATCH_REG_113 0x12501C4
|
||||
#define ACP_SCRATCH_REG_114 0x12501C8
|
||||
#define ACP_SCRATCH_REG_115 0x12501CC
|
||||
#define ACP_SCRATCH_REG_116 0x12501D0
|
||||
#define ACP_SCRATCH_REG_117 0x12501D4
|
||||
#define ACP_SCRATCH_REG_118 0x12501D8
|
||||
#define ACP_SCRATCH_REG_119 0x12501DC
|
||||
#define ACP_SCRATCH_REG_120 0x12501E0
|
||||
#define ACP_SCRATCH_REG_121 0x12501E4
|
||||
#define ACP_SCRATCH_REG_122 0x12501E8
|
||||
#define ACP_SCRATCH_REG_123 0x12501EC
|
||||
#define ACP_SCRATCH_REG_124 0x12501F0
|
||||
#define ACP_SCRATCH_REG_125 0x12501F4
|
||||
#define ACP_SCRATCH_REG_126 0x12501F8
|
||||
#define ACP_SCRATCH_REG_127 0x12501FC
|
||||
#define ACP_SCRATCH_REG_128 0x1250200
|
||||
|
||||
// Registers from ACP_AUDIO_BUFFERS block
|
||||
|
||||
#define ACP_I2S_RX_RINGBUFADDR 0x1242000
|
||||
#define ACP_I2S_RX_RINGBUFSIZE 0x1242004
|
||||
#define ACP_I2S_RX_LINKPOSITIONCNTR 0x1242008
|
||||
#define ACP_I2S_RX_FIFOADDR 0x124200C
|
||||
#define ACP_I2S_RX_FIFOSIZE 0x1242010
|
||||
#define ACP_I2S_RX_DMA_SIZE 0x1242014
|
||||
#define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1242018
|
||||
#define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x124201C
|
||||
#define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020
|
||||
#define ACP_I2S_TX_RINGBUFADDR 0x1242024
|
||||
#define ACP_I2S_TX_RINGBUFSIZE 0x1242028
|
||||
#define ACP_I2S_TX_LINKPOSITIONCNTR 0x124202C
|
||||
#define ACP_I2S_TX_FIFOADDR 0x1242030
|
||||
#define ACP_I2S_TX_FIFOSIZE 0x1242034
|
||||
#define ACP_I2S_TX_DMA_SIZE 0x1242038
|
||||
#define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x124203C
|
||||
#define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1242040
|
||||
#define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044
|
||||
#define ACP_BT_RX_RINGBUFADDR 0x1242048
|
||||
#define ACP_BT_RX_RINGBUFSIZE 0x124204C
|
||||
#define ACP_BT_RX_LINKPOSITIONCNTR 0x1242050
|
||||
#define ACP_BT_RX_FIFOADDR 0x1242054
|
||||
#define ACP_BT_RX_FIFOSIZE 0x1242058
|
||||
#define ACP_BT_RX_DMA_SIZE 0x124205C
|
||||
#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1242060
|
||||
#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x1242064
|
||||
#define ACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068
|
||||
#define ACP_BT_TX_RINGBUFADDR 0x124206C
|
||||
#define ACP_BT_TX_RINGBUFSIZE 0x1242070
|
||||
#define ACP_BT_TX_LINKPOSITIONCNTR 0x1242074
|
||||
#define ACP_BT_TX_FIFOADDR 0x1242078
|
||||
#define ACP_BT_TX_FIFOSIZE 0x124207C
|
||||
#define ACP_BT_TX_DMA_SIZE 0x1242080
|
||||
#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1242084
|
||||
#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x1242088
|
||||
#define ACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C
|
||||
#define ACP_HS_RX_RINGBUFADDR 0x1242090
|
||||
#define ACP_HS_RX_RINGBUFSIZE 0x1242094
|
||||
#define ACP_HS_RX_LINKPOSITIONCNTR 0x1242098
|
||||
#define ACP_HS_RX_FIFOADDR 0x124209C
|
||||
#define ACP_HS_RX_FIFOSIZE 0x12420A0
|
||||
#define ACP_HS_RX_DMA_SIZE 0x12420A4
|
||||
#define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x12420A8
|
||||
#define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x12420AC
|
||||
#define ACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0
|
||||
#define ACP_HS_TX_RINGBUFADDR 0x12420B4
|
||||
#define ACP_HS_TX_RINGBUFSIZE 0x12420B8
|
||||
#define ACP_HS_TX_LINKPOSITIONCNTR 0x12420BC
|
||||
#define ACP_HS_TX_FIFOADDR 0x12420C0
|
||||
#define ACP_HS_TX_FIFOSIZE 0x12420C4
|
||||
#define ACP_HS_TX_DMA_SIZE 0x12420C8
|
||||
#define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x12420CC
|
||||
#define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x12420D0
|
||||
#define ACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4
|
||||
|
||||
// Registers from ACP_I2S_TDM block
|
||||
|
||||
#define ACP_I2STDM_IER 0x1242400
|
||||
#define ACP_I2STDM_IRER 0x1242404
|
||||
#define ACP_I2STDM_RXFRMT 0x1242408
|
||||
#define ACP_I2STDM_ITER 0x124240C
|
||||
#define ACP_I2STDM_TXFRMT 0x1242410
|
||||
|
||||
// Registers from ACP_BT_TDM block
|
||||
|
||||
#define ACP_BTTDM_IER 0x1242800
|
||||
#define ACP_BTTDM_IRER 0x1242804
|
||||
#define ACP_BTTDM_RXFRMT 0x1242808
|
||||
#define ACP_BTTDM_ITER 0x124280C
|
||||
#define ACP_BTTDM_TXFRMT 0x1242810
|
||||
|
||||
// Registers from ACP_WOV block
|
||||
|
||||
#define ACP_WOV_PDM_ENABLE 0x1242C04
|
||||
#define ACP_WOV_PDM_DMA_ENABLE 0x1242C08
|
||||
#define ACP_WOV_RX_RINGBUFADDR 0x1242C0C
|
||||
#define ACP_WOV_RX_RINGBUFSIZE 0x1242C10
|
||||
#define ACP_WOV_RX_LINKPOSITIONCNTR 0x1242C14
|
||||
#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x1242C18
|
||||
#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x1242C1C
|
||||
#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x1242C20
|
||||
#define ACP_WOV_PDM_FIFO_FLUSH 0x1242C24
|
||||
#define ACP_WOV_PDM_NO_OF_CHANNELS 0x1242C28
|
||||
#define ACP_WOV_PDM_DECIMATION_FACTOR 0x1242C2C
|
||||
#define ACP_WOV_PDM_VAD_CTRL 0x1242C30
|
||||
#define ACP_WOV_BUFFER_STATUS 0x1242C58
|
||||
#define ACP_WOV_MISC_CTRL 0x1242C5C
|
||||
#define ACP_WOV_CLK_CTRL 0x1242C60
|
||||
#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x1242C64
|
||||
#define ACP_WOV_ERROR_STATUS_REGISTER 0x1242C68
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user