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davinci: Add watchdog base address flexibility

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The watchdog code currently hardcodes the base address
of the timer its using.  To support new SoCs, make it
support timers at any address.  Use the soc_info structure
to do this.

Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Mark A. Greer 2009-04-15 12:40:21 -07:00 committed by Kevin Hilman
parent f64691b3ab
commit 951d6f6d70
7 changed files with 12 additions and 5 deletions
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7
arch/arm/mach-davinci/devices.c
View File

@ -216,8 +216,6 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
static struct resource wdt_resources[] = {
{
.start = 0x01c21c00,
.end = 0x01c21fff,
.flags = IORESOURCE_MEM,
},
};
@ -231,6 +229,11 @@ struct platform_device davinci_wdt_device = {
static void davinci_init_wdt(void)
{
struct davinci_soc_info *soc_info = &davinci_soc_info;
wdt_resources[0].start = (resource_size_t)soc_info->wdt_base;
wdt_resources[0].end = (resource_size_t)soc_info->wdt_base + SZ_1K - 1;
platform_device_register(&davinci_wdt_device);
}

1
arch/arm/mach-davinci/dm355.c
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@ -646,6 +646,7 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
.intc_irq_prios = dm355_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm355_timer_info,
.wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
};
void __init dm355_init(void)

1
arch/arm/mach-davinci/dm644x.c
View File

@ -589,6 +589,7 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
.intc_irq_prios = dm644x_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm644x_timer_info,
.wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
};
void __init dm644x_init(void)

1
arch/arm/mach-davinci/dm646x.c
View File

@ -568,6 +568,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
.intc_irq_prios = dm646x_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm646x_timer_info,
.wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
};
void __init dm646x_init(void)

1
arch/arm/mach-davinci/include/mach/common.h
View File

@ -57,6 +57,7 @@ struct davinci_soc_info {
u8 *intc_irq_prios;
unsigned long intc_irq_num;
struct davinci_timer_info *timer_info;
void __iomem *wdt_base;
};
extern struct davinci_soc_info davinci_soc_info;

1
arch/arm/mach-davinci/include/mach/time.h
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@ -13,6 +13,7 @@
#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
enum {
T0_BOT,

5
arch/arm/mach-davinci/time.c
View File

@ -35,8 +35,6 @@
static struct clock_event_device clockevent_davinci;
static unsigned int davinci_clock_tick_rate;
#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
/*
* This driver configures the 2 64-bit count-up timers as 4 independent
* 32-bit count-up timers used as follows:
@ -343,7 +341,8 @@ struct sys_timer davinci_timer = {
void davinci_watchdog_reset(void)
{
u32 tgcr, wdtcr;
void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
struct davinci_soc_info *soc_info = &davinci_soc_info;
void __iomem *base = soc_info->wdt_base;
struct clk *wd_clk;
wd_clk = clk_get(&davinci_wdt_device.dev, NULL);