mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-13 15:53:56 +08:00
blackfin updates for Linux 3.12
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJSMoABAAoJEJommM3PjknHeK0QAMCWvahMa3bHu1lPbvYoUKZ8 lFYWye3RLpXQQgLcKTfVH/qoci1I4ssr5MmChZ88TmAZgojRlPk95rBu0pX08+dI 6Ro6rfAYCd6LT06YFb1hOYzBkqmz2SCY1R+MKLPu2kzTC06lnd+iF2sEpBpyBSTq YyW42ZRgOcGf+/iqiBUo112ZbP2V00jQIeQNyvgwF7GKy+lx86SYxzsIukteSCgI W1pNNUnshXT9sH8tGLLtHEkAkYzSkL0mDLdpztkYKiVqXUaSZAz2jfz6CDqfTiNj i+wqTG02NN8lMSH8no8Eko9svzuGAmQVYQiSCL2y0Xesy4P2HW2B5uzVD0oKQXp3 dKAmzUlhoSakAcq/6Rf11HYNYfeCN0T1VqnDt4U/OrIIq/WbK0qPsRtawYw0A5tZ 4uOCZqxfcUW4y0y6TXBRToFb4Fa0vmGX3WGi6DnW6wU1PaEnW14tkqqvCOA9EUHr SZePAkPldRqLxCaJkhqS5eh6SlkObO81Nxtq7D0a1KkT6e2pYToq7QPKECitfs4U q5Q6PxKbxrLBRQRIYmU62dQYGsMinwaqjkOsyU0+e89iA4NGu+vq/SVRgYWiSxWF BHFW+OBZdYvhyTVYRF5ruSPdMxR6uUVSgMwYPYUUKaXgJ8qV9zaRhrFtdsYmweVc AVH7Iay5w9WSO7WghTTS =Shbz -----END PGP SIGNATURE----- Merge tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realmz6/blackfin-linux Pull blackfin updates from Steven Miao. * tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realmz6/blackfin-linux: blackfin: Ignore generated uImages blackfin: Add STMMAC platform data to enable dwmac1000 driver on BF60x. bf609: adv7343: add S-Video and Component output support bf609: add adv7343 video encoder support clock: add stmmac clock for ethernet driver blackfin: scb: Add SCB1 to SCB9 config options and data. blackfin: scb: Add system crossbar init code.
This commit is contained in:
Linus Torvalds
commit
951a730af4
1
arch/blackfin/boot/.gitignore
vendored
1
arch/blackfin/boot/.gitignore
vendored
@ -1,2 +1,3 @@
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vmImage*
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vmlinux*
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uImage*
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21
arch/blackfin/include/asm/scb.h
Normal file
21
arch/blackfin/include/asm/scb.h
Normal file
@ -0,0 +1,21 @@
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/*
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* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
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*
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* Copyright 2012 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#define SCB_SLOT_OFFSET 24
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#define SCB_MI_MAX_SLOT 32
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struct scb_mi_prio {
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unsigned long scb_mi_arbr;
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unsigned long scb_mi_arbw;
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unsigned char scb_mi_slots;
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unsigned char scb_mi_prio[SCB_MI_MAX_SLOT];
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};
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extern struct scb_mi_prio scb_data[];
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extern void init_scb(void);
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@ -35,6 +35,9 @@
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#ifdef CONFIG_BF60x
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#include <mach/pm.h>
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#endif
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#ifdef CONFIG_SCB_PRIORITY
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#include <asm/scb.h>
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#endif
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u16 _bfin_swrst;
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EXPORT_SYMBOL(_bfin_swrst);
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@ -1101,6 +1104,9 @@ void __init setup_arch(char **cmdline_p)
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#endif
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init_exception_vectors();
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bfin_cache_init(); /* Initialize caches for the boot CPU */
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#ifdef CONFIG_SCB_PRIORITY
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init_scb();
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#endif
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}
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static int __init topology_init(void)
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File diff suppressed because it is too large
Load Diff
@ -4,3 +4,4 @@
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obj-y := dma.o clock.o ints-priority.o
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obj-$(CONFIG_PM) += pm.o dpm.o
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obj-$(CONFIG_SCB_PRIORITY) += scb.o
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@ -104,6 +104,7 @@ static struct platform_device bfin_rotary_device = {
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#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
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#include <linux/stmmac.h>
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#include <linux/phy.h>
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static unsigned short pins[] = P_RMII0;
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@ -111,11 +112,26 @@ static struct stmmac_mdio_bus_data phy_private_data = {
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.phy_mask = 1,
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};
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static struct stmmac_dma_cfg eth_dma_cfg = {
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.pbl = 2,
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};
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int stmmac_ptp_clk_init(struct platform_device *pdev)
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{
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bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
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return 0;
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}
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static struct plat_stmmacenet_data eth_private_data = {
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.has_gmac = 1,
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.bus_id = 0,
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.enh_desc = 1,
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.phy_addr = 1,
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.mdio_bus_data = &phy_private_data,
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.dma_cfg = ð_dma_cfg,
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.force_thresh_dma_mode = 1,
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.interface = PHY_INTERFACE_MODE_RMII,
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.init = stmmac_ptp_clk_init,
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};
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static struct platform_device bfin_eth_device = {
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@ -1107,6 +1123,81 @@ static struct bfin_display_config bfin_display_data = {
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};
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#endif
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#if IS_ENABLED(CONFIG_VIDEO_ADV7343)
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#include <media/adv7343.h>
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static struct v4l2_output adv7343_outputs[] = {
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{
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.index = 0,
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.name = "Composite",
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.type = V4L2_OUTPUT_TYPE_ANALOG,
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.std = V4L2_STD_ALL,
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.capabilities = V4L2_OUT_CAP_STD,
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},
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{
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.index = 1,
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.name = "S-Video",
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.type = V4L2_OUTPUT_TYPE_ANALOG,
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.std = V4L2_STD_ALL,
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.capabilities = V4L2_OUT_CAP_STD,
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},
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{
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.index = 2,
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.name = "Component",
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.type = V4L2_OUTPUT_TYPE_ANALOG,
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.std = V4L2_STD_ALL,
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.capabilities = V4L2_OUT_CAP_STD,
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},
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};
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static struct disp_route adv7343_routes[] = {
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{
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.output = ADV7343_COMPOSITE_ID,
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},
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{
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.output = ADV7343_SVIDEO_ID,
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},
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{
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.output = ADV7343_COMPONENT_ID,
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},
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};
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static struct adv7343_platform_data adv7343_data = {
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.mode_config = {
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.sleep_mode = false,
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.pll_control = false,
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.dac_1 = true,
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.dac_2 = true,
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.dac_3 = true,
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.dac_4 = true,
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.dac_5 = true,
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.dac_6 = true,
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},
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.sd_config = {
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.sd_dac_out1 = false,
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.sd_dac_out2 = false,
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},
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};
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static struct bfin_display_config bfin_display_data = {
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.card_name = "BF609",
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.outputs = adv7343_outputs,
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.num_outputs = ARRAY_SIZE(adv7343_outputs),
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.routes = adv7343_routes,
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.i2c_adapter_id = 0,
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.board_info = {
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.type = "adv7343",
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.addr = 0x2b,
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.platform_data = (void *)&adv7343_data,
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},
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.ppi_info = &ppi_info_disp,
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.ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
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| EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
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| EPPI_CTL_NON656 | EPPI_CTL_DIR),
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};
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#endif
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static struct platform_device bfin_display_device = {
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.name = "bfin_display",
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.dev = {
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@ -220,6 +220,12 @@ unsigned long sys_clk_get_rate(struct clk *clk)
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}
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}
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unsigned long dummy_get_rate(struct clk *clk)
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{
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clk->parent->rate = clk_get_rate(clk->parent);
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return clk->parent->rate;
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}
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unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long max_rate;
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@ -283,6 +289,10 @@ static struct clk_ops sys_clk_ops = {
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.round_rate = sys_clk_round_rate,
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};
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static struct clk_ops dummy_clk_ops = {
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.get_rate = dummy_get_rate,
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};
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static struct clk sys_clkin = {
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.name = "SYS_CLKIN",
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.rate = CONFIG_CLKIN_HZ,
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@ -364,6 +374,12 @@ static struct clk oclk = {
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.parent = &pll_clk,
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};
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static struct clk ethclk = {
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.name = "stmmaceth",
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.parent = &sclk0,
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.ops = &dummy_clk_ops,
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};
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static struct clk_lookup bf609_clks[] = {
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CLK(sys_clkin, NULL, "SYS_CLKIN"),
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CLK(pll_clk, NULL, "PLLCLK"),
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@ -375,6 +391,7 @@ static struct clk_lookup bf609_clks[] = {
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CLK(sclk1, NULL, "SCLK1"),
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CLK(dclk, NULL, "DCLK"),
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CLK(oclk, NULL, "OCLK"),
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CLK(ethclk, NULL, "stmmaceth"),
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};
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int __init clk_init(void)
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@ -839,6 +839,16 @@
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#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */
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#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */
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/* ==================================================
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Pads Controller Registers
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================================================== */
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/* =========================
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PADS0
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========================= */
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#define PADS0_EMAC_PTP_CLKSEL 0xFFC03404 /* PADS0 Clock Selection for EMAC and PTP */
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#define PADS0_TWI_VSEL 0xFFC03408 /* PADS0 TWI Voltage Selection */
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#define PADS0_PORTS_HYST 0xFFC03440 /* PADS0 Hysteresis Enable Register */
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/* =========================
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PINT Registers
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363
arch/blackfin/mach-bf609/scb.c
Normal file
363
arch/blackfin/mach-bf609/scb.c
Normal file
@ -0,0 +1,363 @@
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/*
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* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
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*
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* Copyright 2012 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <asm/blackfin.h>
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#include <asm/scb.h>
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struct scb_mi_prio scb_data[] = {
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#ifdef CONFIG_SCB0_MI0
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{ REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, {
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CONFIG_SCB0_MI0_SLOT0,
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CONFIG_SCB0_MI0_SLOT1,
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CONFIG_SCB0_MI0_SLOT2,
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CONFIG_SCB0_MI0_SLOT3,
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CONFIG_SCB0_MI0_SLOT4,
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CONFIG_SCB0_MI0_SLOT5,
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CONFIG_SCB0_MI0_SLOT6,
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CONFIG_SCB0_MI0_SLOT7,
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CONFIG_SCB0_MI0_SLOT8,
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CONFIG_SCB0_MI0_SLOT9,
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CONFIG_SCB0_MI0_SLOT10,
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CONFIG_SCB0_MI0_SLOT11,
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CONFIG_SCB0_MI0_SLOT12,
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CONFIG_SCB0_MI0_SLOT13,
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CONFIG_SCB0_MI0_SLOT14,
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CONFIG_SCB0_MI0_SLOT15,
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CONFIG_SCB0_MI0_SLOT16,
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CONFIG_SCB0_MI0_SLOT17,
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CONFIG_SCB0_MI0_SLOT18,
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CONFIG_SCB0_MI0_SLOT19,
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CONFIG_SCB0_MI0_SLOT20,
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CONFIG_SCB0_MI0_SLOT21,
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CONFIG_SCB0_MI0_SLOT22,
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CONFIG_SCB0_MI0_SLOT23,
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CONFIG_SCB0_MI0_SLOT24,
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CONFIG_SCB0_MI0_SLOT25,
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CONFIG_SCB0_MI0_SLOT26,
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CONFIG_SCB0_MI0_SLOT27,
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CONFIG_SCB0_MI0_SLOT28,
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CONFIG_SCB0_MI0_SLOT29,
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CONFIG_SCB0_MI0_SLOT30,
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CONFIG_SCB0_MI0_SLOT31
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},
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},
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#endif
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#ifdef CONFIG_SCB0_MI1
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{ REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, {
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CONFIG_SCB0_MI1_SLOT0,
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CONFIG_SCB0_MI1_SLOT1,
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CONFIG_SCB0_MI1_SLOT2,
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CONFIG_SCB0_MI1_SLOT3,
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CONFIG_SCB0_MI1_SLOT4,
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CONFIG_SCB0_MI1_SLOT5,
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CONFIG_SCB0_MI1_SLOT6,
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CONFIG_SCB0_MI1_SLOT7,
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CONFIG_SCB0_MI1_SLOT8,
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CONFIG_SCB0_MI1_SLOT9,
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CONFIG_SCB0_MI1_SLOT10,
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CONFIG_SCB0_MI1_SLOT11,
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CONFIG_SCB0_MI1_SLOT12,
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CONFIG_SCB0_MI1_SLOT13,
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CONFIG_SCB0_MI1_SLOT14,
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CONFIG_SCB0_MI1_SLOT15,
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CONFIG_SCB0_MI1_SLOT16,
|
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CONFIG_SCB0_MI1_SLOT17,
|
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CONFIG_SCB0_MI1_SLOT18,
|
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CONFIG_SCB0_MI1_SLOT19,
|
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CONFIG_SCB0_MI1_SLOT20,
|
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CONFIG_SCB0_MI1_SLOT21,
|
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CONFIG_SCB0_MI1_SLOT22,
|
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CONFIG_SCB0_MI1_SLOT23,
|
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CONFIG_SCB0_MI1_SLOT24,
|
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CONFIG_SCB0_MI1_SLOT25,
|
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CONFIG_SCB0_MI1_SLOT26,
|
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CONFIG_SCB0_MI1_SLOT27,
|
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CONFIG_SCB0_MI1_SLOT28,
|
||||
CONFIG_SCB0_MI1_SLOT29,
|
||||
CONFIG_SCB0_MI1_SLOT30,
|
||||
CONFIG_SCB0_MI1_SLOT31
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB0_MI2
|
||||
{ REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, {
|
||||
CONFIG_SCB0_MI2_SLOT0,
|
||||
CONFIG_SCB0_MI2_SLOT1,
|
||||
CONFIG_SCB0_MI2_SLOT2,
|
||||
CONFIG_SCB0_MI2_SLOT3,
|
||||
CONFIG_SCB0_MI2_SLOT4,
|
||||
CONFIG_SCB0_MI2_SLOT5,
|
||||
CONFIG_SCB0_MI2_SLOT6,
|
||||
CONFIG_SCB0_MI2_SLOT7,
|
||||
CONFIG_SCB0_MI2_SLOT8,
|
||||
CONFIG_SCB0_MI2_SLOT9,
|
||||
CONFIG_SCB0_MI2_SLOT10,
|
||||
CONFIG_SCB0_MI2_SLOT11,
|
||||
CONFIG_SCB0_MI2_SLOT12,
|
||||
CONFIG_SCB0_MI2_SLOT13,
|
||||
CONFIG_SCB0_MI2_SLOT14,
|
||||
CONFIG_SCB0_MI2_SLOT15,
|
||||
CONFIG_SCB0_MI2_SLOT16,
|
||||
CONFIG_SCB0_MI2_SLOT17,
|
||||
CONFIG_SCB0_MI2_SLOT18,
|
||||
CONFIG_SCB0_MI2_SLOT19,
|
||||
CONFIG_SCB0_MI2_SLOT20,
|
||||
CONFIG_SCB0_MI2_SLOT21,
|
||||
CONFIG_SCB0_MI2_SLOT22,
|
||||
CONFIG_SCB0_MI2_SLOT23,
|
||||
CONFIG_SCB0_MI2_SLOT24,
|
||||
CONFIG_SCB0_MI2_SLOT25,
|
||||
CONFIG_SCB0_MI2_SLOT26,
|
||||
CONFIG_SCB0_MI2_SLOT27,
|
||||
CONFIG_SCB0_MI2_SLOT28,
|
||||
CONFIG_SCB0_MI2_SLOT29,
|
||||
CONFIG_SCB0_MI2_SLOT30,
|
||||
CONFIG_SCB0_MI2_SLOT31
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB0_MI3
|
||||
{ REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, {
|
||||
CONFIG_SCB0_MI3_SLOT0,
|
||||
CONFIG_SCB0_MI3_SLOT1,
|
||||
CONFIG_SCB0_MI3_SLOT2,
|
||||
CONFIG_SCB0_MI3_SLOT3,
|
||||
CONFIG_SCB0_MI3_SLOT4,
|
||||
CONFIG_SCB0_MI3_SLOT5,
|
||||
CONFIG_SCB0_MI3_SLOT6,
|
||||
CONFIG_SCB0_MI3_SLOT7,
|
||||
CONFIG_SCB0_MI3_SLOT8,
|
||||
CONFIG_SCB0_MI3_SLOT9,
|
||||
CONFIG_SCB0_MI3_SLOT10,
|
||||
CONFIG_SCB0_MI3_SLOT11,
|
||||
CONFIG_SCB0_MI3_SLOT12,
|
||||
CONFIG_SCB0_MI3_SLOT13,
|
||||
CONFIG_SCB0_MI3_SLOT14,
|
||||
CONFIG_SCB0_MI3_SLOT15,
|
||||
CONFIG_SCB0_MI3_SLOT16,
|
||||
CONFIG_SCB0_MI3_SLOT17,
|
||||
CONFIG_SCB0_MI3_SLOT18,
|
||||
CONFIG_SCB0_MI3_SLOT19,
|
||||
CONFIG_SCB0_MI3_SLOT20,
|
||||
CONFIG_SCB0_MI3_SLOT21,
|
||||
CONFIG_SCB0_MI3_SLOT22,
|
||||
CONFIG_SCB0_MI3_SLOT23,
|
||||
CONFIG_SCB0_MI3_SLOT24,
|
||||
CONFIG_SCB0_MI3_SLOT25,
|
||||
CONFIG_SCB0_MI3_SLOT26,
|
||||
CONFIG_SCB0_MI3_SLOT27,
|
||||
CONFIG_SCB0_MI3_SLOT28,
|
||||
CONFIG_SCB0_MI3_SLOT29,
|
||||
CONFIG_SCB0_MI3_SLOT30,
|
||||
CONFIG_SCB0_MI3_SLOT31
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB0_MI4
|
||||
{ REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, {
|
||||
CONFIG_SCB0_MI4_SLOT0,
|
||||
CONFIG_SCB0_MI4_SLOT1,
|
||||
CONFIG_SCB0_MI4_SLOT2,
|
||||
CONFIG_SCB0_MI4_SLOT3,
|
||||
CONFIG_SCB0_MI4_SLOT4,
|
||||
CONFIG_SCB0_MI4_SLOT5,
|
||||
CONFIG_SCB0_MI4_SLOT6,
|
||||
CONFIG_SCB0_MI4_SLOT7,
|
||||
CONFIG_SCB0_MI4_SLOT8,
|
||||
CONFIG_SCB0_MI4_SLOT9,
|
||||
CONFIG_SCB0_MI4_SLOT10,
|
||||
CONFIG_SCB0_MI4_SLOT11,
|
||||
CONFIG_SCB0_MI4_SLOT12,
|
||||
CONFIG_SCB0_MI4_SLOT13,
|
||||
CONFIG_SCB0_MI4_SLOT14,
|
||||
CONFIG_SCB0_MI4_SLOT15,
|
||||
CONFIG_SCB0_MI4_SLOT16,
|
||||
CONFIG_SCB0_MI4_SLOT17,
|
||||
CONFIG_SCB0_MI4_SLOT18,
|
||||
CONFIG_SCB0_MI4_SLOT19,
|
||||
CONFIG_SCB0_MI4_SLOT20,
|
||||
CONFIG_SCB0_MI4_SLOT21,
|
||||
CONFIG_SCB0_MI4_SLOT22,
|
||||
CONFIG_SCB0_MI4_SLOT23,
|
||||
CONFIG_SCB0_MI4_SLOT24,
|
||||
CONFIG_SCB0_MI4_SLOT25,
|
||||
CONFIG_SCB0_MI4_SLOT26,
|
||||
CONFIG_SCB0_MI4_SLOT27,
|
||||
CONFIG_SCB0_MI4_SLOT28,
|
||||
CONFIG_SCB0_MI4_SLOT29,
|
||||
CONFIG_SCB0_MI4_SLOT30,
|
||||
CONFIG_SCB0_MI4_SLOT31
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB0_MI5
|
||||
{ REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, {
|
||||
CONFIG_SCB0_MI5_SLOT0,
|
||||
CONFIG_SCB0_MI5_SLOT1,
|
||||
CONFIG_SCB0_MI5_SLOT2,
|
||||
CONFIG_SCB0_MI5_SLOT3,
|
||||
CONFIG_SCB0_MI5_SLOT4,
|
||||
CONFIG_SCB0_MI5_SLOT5,
|
||||
CONFIG_SCB0_MI5_SLOT6,
|
||||
CONFIG_SCB0_MI5_SLOT7,
|
||||
CONFIG_SCB0_MI5_SLOT8,
|
||||
CONFIG_SCB0_MI5_SLOT9,
|
||||
CONFIG_SCB0_MI5_SLOT10,
|
||||
CONFIG_SCB0_MI5_SLOT11,
|
||||
CONFIG_SCB0_MI5_SLOT12,
|
||||
CONFIG_SCB0_MI5_SLOT13,
|
||||
CONFIG_SCB0_MI5_SLOT14,
|
||||
CONFIG_SCB0_MI5_SLOT15
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB1_MI0
|
||||
{ REG_SCB1_ARBR0, REG_SCB1_ARBW0, 20, {
|
||||
CONFIG_SCB1_MI0_SLOT0,
|
||||
CONFIG_SCB1_MI0_SLOT1,
|
||||
CONFIG_SCB1_MI0_SLOT2,
|
||||
CONFIG_SCB1_MI0_SLOT3,
|
||||
CONFIG_SCB1_MI0_SLOT4,
|
||||
CONFIG_SCB1_MI0_SLOT5,
|
||||
CONFIG_SCB1_MI0_SLOT6,
|
||||
CONFIG_SCB1_MI0_SLOT7,
|
||||
CONFIG_SCB1_MI0_SLOT8,
|
||||
CONFIG_SCB1_MI0_SLOT9,
|
||||
CONFIG_SCB1_MI0_SLOT10,
|
||||
CONFIG_SCB1_MI0_SLOT11,
|
||||
CONFIG_SCB1_MI0_SLOT12,
|
||||
CONFIG_SCB1_MI0_SLOT13,
|
||||
CONFIG_SCB1_MI0_SLOT14,
|
||||
CONFIG_SCB1_MI0_SLOT15,
|
||||
CONFIG_SCB1_MI0_SLOT16,
|
||||
CONFIG_SCB1_MI0_SLOT17,
|
||||
CONFIG_SCB1_MI0_SLOT18,
|
||||
CONFIG_SCB1_MI0_SLOT19
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB2_MI0
|
||||
{ REG_SCB2_ARBR0, REG_SCB2_ARBW0, 10, {
|
||||
CONFIG_SCB2_MI0_SLOT0,
|
||||
CONFIG_SCB2_MI0_SLOT1,
|
||||
CONFIG_SCB2_MI0_SLOT2,
|
||||
CONFIG_SCB2_MI0_SLOT3,
|
||||
CONFIG_SCB2_MI0_SLOT4,
|
||||
CONFIG_SCB2_MI0_SLOT5,
|
||||
CONFIG_SCB2_MI0_SLOT6,
|
||||
CONFIG_SCB2_MI0_SLOT7,
|
||||
CONFIG_SCB2_MI0_SLOT8,
|
||||
CONFIG_SCB2_MI0_SLOT9
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB3_MI0
|
||||
{ REG_SCB3_ARBR0, REG_SCB3_ARBW0, 16, {
|
||||
CONFIG_SCB3_MI0_SLOT0,
|
||||
CONFIG_SCB3_MI0_SLOT1,
|
||||
CONFIG_SCB3_MI0_SLOT2,
|
||||
CONFIG_SCB3_MI0_SLOT3,
|
||||
CONFIG_SCB3_MI0_SLOT4,
|
||||
CONFIG_SCB3_MI0_SLOT5,
|
||||
CONFIG_SCB3_MI0_SLOT6,
|
||||
CONFIG_SCB3_MI0_SLOT7,
|
||||
CONFIG_SCB3_MI0_SLOT8,
|
||||
CONFIG_SCB3_MI0_SLOT9,
|
||||
CONFIG_SCB3_MI0_SLOT10,
|
||||
CONFIG_SCB3_MI0_SLOT11,
|
||||
CONFIG_SCB3_MI0_SLOT12,
|
||||
CONFIG_SCB3_MI0_SLOT13,
|
||||
CONFIG_SCB3_MI0_SLOT14,
|
||||
CONFIG_SCB3_MI0_SLOT15
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB4_MI0
|
||||
{ REG_SCB4_ARBR0, REG_SCB4_ARBW0, 16, {
|
||||
CONFIG_SCB4_MI0_SLOT0,
|
||||
CONFIG_SCB4_MI0_SLOT1,
|
||||
CONFIG_SCB4_MI0_SLOT2,
|
||||
CONFIG_SCB4_MI0_SLOT3,
|
||||
CONFIG_SCB4_MI0_SLOT4,
|
||||
CONFIG_SCB4_MI0_SLOT5,
|
||||
CONFIG_SCB4_MI0_SLOT6,
|
||||
CONFIG_SCB4_MI0_SLOT7,
|
||||
CONFIG_SCB4_MI0_SLOT8,
|
||||
CONFIG_SCB4_MI0_SLOT9,
|
||||
CONFIG_SCB4_MI0_SLOT10,
|
||||
CONFIG_SCB4_MI0_SLOT11,
|
||||
CONFIG_SCB4_MI0_SLOT12,
|
||||
CONFIG_SCB4_MI0_SLOT13,
|
||||
CONFIG_SCB4_MI0_SLOT14,
|
||||
CONFIG_SCB4_MI0_SLOT15
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB5_MI0
|
||||
{ REG_SCB5_ARBR0, REG_SCB5_ARBW0, 8, {
|
||||
CONFIG_SCB5_MI0_SLOT0,
|
||||
CONFIG_SCB5_MI0_SLOT1,
|
||||
CONFIG_SCB5_MI0_SLOT2,
|
||||
CONFIG_SCB5_MI0_SLOT3,
|
||||
CONFIG_SCB5_MI0_SLOT4,
|
||||
CONFIG_SCB5_MI0_SLOT5,
|
||||
CONFIG_SCB5_MI0_SLOT6,
|
||||
CONFIG_SCB5_MI0_SLOT7
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB6_MI0
|
||||
{ REG_SCB6_ARBR0, REG_SCB6_ARBW0, 4, {
|
||||
CONFIG_SCB6_MI0_SLOT0,
|
||||
CONFIG_SCB6_MI0_SLOT1,
|
||||
CONFIG_SCB6_MI0_SLOT2,
|
||||
CONFIG_SCB6_MI0_SLOT3
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB7_MI0
|
||||
{ REG_SCB7_ARBR0, REG_SCB7_ARBW0, 6, {
|
||||
CONFIG_SCB7_MI0_SLOT0,
|
||||
CONFIG_SCB7_MI0_SLOT1,
|
||||
CONFIG_SCB7_MI0_SLOT2,
|
||||
CONFIG_SCB7_MI0_SLOT3,
|
||||
CONFIG_SCB7_MI0_SLOT4,
|
||||
CONFIG_SCB7_MI0_SLOT5
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB8_MI0
|
||||
{ REG_SCB8_ARBR0, REG_SCB8_ARBW0, 8, {
|
||||
CONFIG_SCB8_MI0_SLOT0,
|
||||
CONFIG_SCB8_MI0_SLOT1,
|
||||
CONFIG_SCB8_MI0_SLOT2,
|
||||
CONFIG_SCB8_MI0_SLOT3,
|
||||
CONFIG_SCB8_MI0_SLOT4,
|
||||
CONFIG_SCB8_MI0_SLOT5,
|
||||
CONFIG_SCB8_MI0_SLOT6,
|
||||
CONFIG_SCB8_MI0_SLOT7
|
||||
},
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SCB9_MI0
|
||||
{ REG_SCB9_ARBR0, REG_SCB9_ARBW0, 10, {
|
||||
CONFIG_SCB9_MI0_SLOT0,
|
||||
CONFIG_SCB9_MI0_SLOT1,
|
||||
CONFIG_SCB9_MI0_SLOT2,
|
||||
CONFIG_SCB9_MI0_SLOT3,
|
||||
CONFIG_SCB9_MI0_SLOT4,
|
||||
CONFIG_SCB9_MI0_SLOT5,
|
||||
CONFIG_SCB9_MI0_SLOT6,
|
||||
CONFIG_SCB9_MI0_SLOT7,
|
||||
CONFIG_SCB9_MI0_SLOT8,
|
||||
CONFIG_SCB9_MI0_SLOT9
|
||||
},
|
||||
},
|
||||
#endif
|
||||
{ 0, }
|
||||
};
|
||||
@ -10,6 +10,7 @@ obj-$(CONFIG_PM) += pm.o
|
||||
ifneq ($(CONFIG_BF60x),y)
|
||||
obj-$(CONFIG_PM) += dpmc_modes.o
|
||||
endif
|
||||
obj-$(CONFIG_SCB_PRIORITY) += scb-init.o
|
||||
obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
|
||||
obj-$(CONFIG_SMP) += smp.o
|
||||
obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o
|
||||
|
||||
53
arch/blackfin/mach-common/scb-init.c
Normal file
53
arch/blackfin/mach-common/scb-init.c
Normal file
@ -0,0 +1,53 @@
|
||||
/*
|
||||
* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
|
||||
*
|
||||
* Copyright 2012 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <asm/scb.h>
|
||||
|
||||
__attribute__((l1_text))
|
||||
inline void scb_mi_write(unsigned long scb_mi_arbw, unsigned int slots,
|
||||
unsigned char *scb_mi_prio)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < slots; ++i)
|
||||
bfin_write32(scb_mi_arbw, (i << SCB_SLOT_OFFSET) | scb_mi_prio[i]);
|
||||
}
|
||||
|
||||
__attribute__((l1_text))
|
||||
inline void scb_mi_read(unsigned long scb_mi_arbw, unsigned int slots,
|
||||
unsigned char *scb_mi_prio)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < slots; ++i) {
|
||||
bfin_write32(scb_mi_arbw, (0xFF << SCB_SLOT_OFFSET) | i);
|
||||
scb_mi_prio[i] = bfin_read32(scb_mi_arbw);
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((l1_text))
|
||||
void init_scb(void)
|
||||
{
|
||||
unsigned int i, j;
|
||||
unsigned char scb_tmp_prio[32];
|
||||
|
||||
pr_info("Init System Crossbar\n");
|
||||
for (i = 0; scb_data[i].scb_mi_arbr > 0; ++i) {
|
||||
|
||||
scb_mi_write(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_data[i].scb_mi_prio);
|
||||
|
||||
pr_debug("scb priority at 0x%lx:\n", scb_data[i].scb_mi_arbr);
|
||||
scb_mi_read(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_tmp_prio);
|
||||
for (j = 0; j < scb_data[i].scb_mi_slots; ++j)
|
||||
pr_debug("slot %d = %d\n", j, scb_tmp_prio[j]);
|
||||
}
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user