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[MIPS] Save write-only Config.OD from being clobbered
Save the Config.OD bit from being clobbered by coherency_setup(). This bit, when set, fixes various errata in the early steppings of Au1x00 SOCs. Unfortunately, the bit was write-only on the most early of them. In addition, also restore the bit after a wakeup from sleep. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -112,6 +112,11 @@ sdsleep:
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mtc0 k0, CP0_PAGEMASK
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lw k0, 0x14(sp)
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mtc0 k0, CP0_CONFIG
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/* We need to catch the ealry Alchemy SOCs with
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* the write-only Config[OD] bit and set it back to one...
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*/
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jal au1x00_fixup_config_od
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lw $1, PT_R1(sp)
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lw $2, PT_R2(sp)
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lw $3, PT_R3(sp)
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@ -1161,6 +1161,31 @@ static void __init setup_scache(void)
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c->options |= MIPS_CPU_SUBSET_CACHES;
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}
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void au1x00_fixup_config_od(void)
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{
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/*
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* c0_config.od (bit 19) was write only (and read as 0)
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* on the early revisions of Alchemy SOCs. It disables the bus
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* transaction overlapping and needs to be set to fix various errata.
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*/
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switch (read_c0_prid()) {
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case 0x00030100: /* Au1000 DA */
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case 0x00030201: /* Au1000 HA */
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case 0x00030202: /* Au1000 HB */
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case 0x01030200: /* Au1500 AB */
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/*
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* Au1100 errata actually keeps silence about this bit, so we set it
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* just in case for those revisions that require it to be set according
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* to arch/mips/au1000/common/cputable.c
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*/
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case 0x02030200: /* Au1100 AB */
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case 0x02030201: /* Au1100 BA */
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case 0x02030202: /* Au1100 BC */
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set_c0_config(1 << 19);
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break;
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}
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}
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static inline void coherency_setup(void)
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{
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change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
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@ -1181,6 +1206,15 @@ static inline void coherency_setup(void)
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case CPU_R4400MC:
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clear_c0_config(CONF_CU);
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break;
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/*
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* We need to catch the ealry Alchemy SOCs with
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* the write-only co_config.od bit and set it back to one...
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*/
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case CPU_AU1000: /* rev. DA, HA, HB */
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case CPU_AU1100: /* rev. AB, BA, BC ?? */
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case CPU_AU1500: /* rev. AB */
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au1x00_fixup_config_od();
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break;
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}
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}
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