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powerpc: Context switch the new EBB SPRs
This context switches the new Event Based Branching (EBB) SPRs. The three new SPRs are: - Event Based Branch Handler Register (EBBHR) - Event Based Branch Return Register (EBBRR) - Branch Event Status and Control Register (BESCR) Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Matt Evans <matt@ozlabs.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -281,6 +281,9 @@ struct thread_struct {
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#endif
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#ifdef CONFIG_PPC_BOOK3S_64
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unsigned long tar;
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unsigned long ebbrr;
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unsigned long ebbhr;
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unsigned long bescr;
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#endif
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};
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@ -663,6 +663,9 @@
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#define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */
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#define SPRN_MMCRS 894 /* Supervisor monitor mode control register */
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#define SPRN_MMCRC 851 /* Core monitor mode control register */
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#define SPRN_EBBHR 804 /* Event based branch handler register */
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#define SPRN_EBBRR 805 /* Event based branch return register */
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#define SPRN_BESCR 806 /* Branch event status and control register */
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#define SPRN_PMC1 787
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#define SPRN_PMC2 788
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@ -124,6 +124,9 @@ int main(void)
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#ifdef CONFIG_PPC_BOOK3S_64
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DEFINE(THREAD_TAR, offsetof(struct thread_struct, tar));
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DEFINE(THREAD_BESCR, offsetof(struct thread_struct, bescr));
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DEFINE(THREAD_EBBHR, offsetof(struct thread_struct, ebbhr));
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DEFINE(THREAD_EBBRR, offsetof(struct thread_struct, ebbrr));
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#endif
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch));
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@ -458,6 +458,14 @@ BEGIN_FTR_SECTION
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*/
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mfspr r0,SPRN_TAR
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std r0,THREAD_TAR(r3)
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/* Event based branch registers */
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mfspr r0, SPRN_BESCR
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std r0, THREAD_BESCR(r3)
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mfspr r0, SPRN_EBBHR
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std r0, THREAD_EBBHR(r3)
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mfspr r0, SPRN_EBBRR
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std r0, THREAD_EBBRR(r3)
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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#endif
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@ -545,6 +553,14 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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#ifdef CONFIG_PPC_BOOK3S_64
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BEGIN_FTR_SECTION
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/* Event based branch registers */
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ld r0, THREAD_BESCR(r4)
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mtspr SPRN_BESCR, r0
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ld r0, THREAD_EBBHR(r4)
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mtspr SPRN_EBBHR, r0
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ld r0, THREAD_EBBRR(r4)
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mtspr SPRN_EBBRR, r0
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ld r0,THREAD_TAR(r4)
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mtspr SPRN_TAR,r0
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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