mirror of
https://github.com/edk2-porting/linux-next.git
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irqchip/stm32: Add stm32mp1 support with hierarchy domain
Exti controller has been differently integrated on stm32mp1 SoC. A parent irq has only one external interrupt. A hierachy domain could be used. Handlers are call by parent, each parent interrupt could be masked and unmasked according to the needs. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Ludovic Barre
Marc Zyngier
parent
5a2490e029
commit
927abfc446
@ -5,11 +5,14 @@ Required properties:
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- compatible: Should be:
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"st,stm32-exti"
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"st,stm32h7-exti"
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"st,stm32mp1-exti"
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- reg: Specifies base physical address and size of the registers
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- interrupt-controller: Indentifies the node as an interrupt controller
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- #interrupt-cells: Specifies the number of cells to encode an interrupt
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specifier, shall be 2
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- interrupts: interrupts references to primary interrupt controller
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(only needed for exti controller with multiple exti under
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same parent interrupt: st,stm32-exti and st,stm32h7-exti")
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Example:
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@ -15,6 +15,8 @@
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define IRQS_PER_BANK 32
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struct stm32_exti_bank {
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@ -29,14 +31,24 @@ struct stm32_exti_bank {
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#define UNDEF_REG ~0
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struct stm32_desc_irq {
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u32 exti;
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u32 irq_parent;
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};
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struct stm32_exti_drv_data {
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const struct stm32_exti_bank **exti_banks;
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const struct stm32_desc_irq *desc_irqs;
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u32 bank_nr;
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u32 irq_nr;
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};
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struct stm32_exti_chip_data {
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struct stm32_exti_host_data *host_data;
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const struct stm32_exti_bank *reg_bank;
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struct raw_spinlock rlock;
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u32 wake_active;
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u32 mask_cache;
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u32 rtsr_cache;
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u32 ftsr_cache;
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};
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@ -107,6 +119,89 @@ static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
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.bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
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};
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static const struct stm32_exti_bank stm32mp1_exti_b1 = {
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.imr_ofst = 0x80,
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.emr_ofst = 0x84,
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.rtsr_ofst = 0x00,
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.ftsr_ofst = 0x04,
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.swier_ofst = 0x08,
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.rpr_ofst = 0x0C,
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.fpr_ofst = 0x10,
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};
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static const struct stm32_exti_bank stm32mp1_exti_b2 = {
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.imr_ofst = 0x90,
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.emr_ofst = 0x94,
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.rtsr_ofst = 0x20,
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.ftsr_ofst = 0x24,
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.swier_ofst = 0x28,
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.rpr_ofst = 0x2C,
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.fpr_ofst = 0x30,
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};
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static const struct stm32_exti_bank stm32mp1_exti_b3 = {
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.imr_ofst = 0xA0,
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.emr_ofst = 0xA4,
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.rtsr_ofst = 0x40,
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.ftsr_ofst = 0x44,
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.swier_ofst = 0x48,
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.rpr_ofst = 0x4C,
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.fpr_ofst = 0x50,
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};
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static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
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&stm32mp1_exti_b1,
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&stm32mp1_exti_b2,
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&stm32mp1_exti_b3,
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};
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static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
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{ .exti = 1, .irq_parent = 7 },
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{ .exti = 2, .irq_parent = 8 },
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{ .exti = 3, .irq_parent = 9 },
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{ .exti = 4, .irq_parent = 10 },
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{ .exti = 5, .irq_parent = 23 },
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{ .exti = 6, .irq_parent = 64 },
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{ .exti = 7, .irq_parent = 65 },
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{ .exti = 8, .irq_parent = 66 },
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{ .exti = 9, .irq_parent = 67 },
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{ .exti = 10, .irq_parent = 40 },
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{ .exti = 11, .irq_parent = 42 },
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{ .exti = 12, .irq_parent = 76 },
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{ .exti = 13, .irq_parent = 77 },
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{ .exti = 14, .irq_parent = 121 },
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{ .exti = 15, .irq_parent = 127 },
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{ .exti = 16, .irq_parent = 1 },
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{ .exti = 65, .irq_parent = 144 },
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{ .exti = 68, .irq_parent = 143 },
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{ .exti = 73, .irq_parent = 129 },
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};
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static const struct stm32_exti_drv_data stm32mp1_drv_data = {
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.exti_banks = stm32mp1_exti_banks,
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.bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
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.desc_irqs = stm32mp1_desc_irq,
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.irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
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};
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static int stm32_exti_to_irq(const struct stm32_exti_drv_data *drv_data,
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irq_hw_number_t hwirq)
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{
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const struct stm32_desc_irq *desc_irq;
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int i;
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if (!drv_data->desc_irqs)
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return -EINVAL;
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for (i = 0; i < drv_data->irq_nr; i++) {
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desc_irq = &drv_data->desc_irqs[i];
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if (desc_irq->exti == hwirq)
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return desc_irq->irq_parent;
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}
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return -EINVAL;
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}
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static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
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{
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struct stm32_exti_chip_data *chip_data = gc->private;
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@ -282,6 +377,173 @@ static void stm32_irq_ack(struct irq_data *d)
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irq_gc_unlock(gc);
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}
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static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
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{
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struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
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void __iomem *base = chip_data->host_data->base;
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u32 val;
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val = readl_relaxed(base + reg);
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val |= BIT(d->hwirq % IRQS_PER_BANK);
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writel_relaxed(val, base + reg);
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return val;
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}
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static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
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{
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struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
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void __iomem *base = chip_data->host_data->base;
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u32 val;
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val = readl_relaxed(base + reg);
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val &= ~BIT(d->hwirq % IRQS_PER_BANK);
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writel_relaxed(val, base + reg);
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return val;
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}
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static void stm32_exti_h_eoi(struct irq_data *d)
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{
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struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
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const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
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raw_spin_lock(&chip_data->rlock);
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stm32_exti_set_bit(d, stm32_bank->rpr_ofst);
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if (stm32_bank->fpr_ofst != UNDEF_REG)
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stm32_exti_set_bit(d, stm32_bank->fpr_ofst);
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raw_spin_unlock(&chip_data->rlock);
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if (d->parent_data->chip)
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irq_chip_eoi_parent(d);
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}
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static void stm32_exti_h_mask(struct irq_data *d)
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{
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struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
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const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
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raw_spin_lock(&chip_data->rlock);
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chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
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raw_spin_unlock(&chip_data->rlock);
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if (d->parent_data->chip)
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irq_chip_mask_parent(d);
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}
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static void stm32_exti_h_unmask(struct irq_data *d)
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{
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struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
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const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
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raw_spin_lock(&chip_data->rlock);
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chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
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raw_spin_unlock(&chip_data->rlock);
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if (d->parent_data->chip)
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irq_chip_unmask_parent(d);
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}
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static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
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{
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struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
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const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
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void __iomem *base = chip_data->host_data->base;
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u32 rtsr, ftsr;
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int err;
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raw_spin_lock(&chip_data->rlock);
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rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
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ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
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err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
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if (err) {
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raw_spin_unlock(&chip_data->rlock);
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return err;
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}
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writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
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writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
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raw_spin_unlock(&chip_data->rlock);
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return 0;
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}
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static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
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{
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struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
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u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
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raw_spin_lock(&chip_data->rlock);
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if (on)
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chip_data->wake_active |= mask;
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else
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chip_data->wake_active &= ~mask;
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raw_spin_unlock(&chip_data->rlock);
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return 0;
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}
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static int stm32_exti_h_set_affinity(struct irq_data *d,
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const struct cpumask *dest, bool force)
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{
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if (d->parent_data->chip)
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return irq_chip_set_affinity_parent(d, dest, force);
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return -EINVAL;
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}
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static struct irq_chip stm32_exti_h_chip = {
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.name = "stm32-exti-h",
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.irq_eoi = stm32_exti_h_eoi,
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.irq_mask = stm32_exti_h_mask,
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.irq_unmask = stm32_exti_h_unmask,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_type = stm32_exti_h_set_type,
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.irq_set_wake = stm32_exti_h_set_wake,
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.flags = IRQCHIP_MASK_ON_SUSPEND,
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#ifdef CONFIG_SMP
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.irq_set_affinity = stm32_exti_h_set_affinity,
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#endif
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};
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static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
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unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct stm32_exti_host_data *host_data = dm->host_data;
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struct stm32_exti_chip_data *chip_data;
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec p_fwspec;
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irq_hw_number_t hwirq;
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int p_irq, bank;
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hwirq = fwspec->param[0];
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bank = hwirq / IRQS_PER_BANK;
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chip_data = &host_data->chips_data[bank];
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irq_domain_set_hwirq_and_chip(dm, virq, hwirq,
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&stm32_exti_h_chip, chip_data);
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p_irq = stm32_exti_to_irq(host_data->drv_data, hwirq);
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if (p_irq >= 0) {
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p_fwspec.fwnode = dm->parent->fwnode;
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p_fwspec.param_count = 3;
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p_fwspec.param[0] = GIC_SPI;
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p_fwspec.param[1] = p_irq;
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p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
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return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
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}
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return 0;
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}
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static struct
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stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
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struct device_node *node)
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@ -323,6 +585,8 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
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chip_data->host_data = h_data;
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chip_data->reg_bank = stm32_bank;
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raw_spin_lock_init(&chip_data->rlock);
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/* Determine number of irqs supported */
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writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
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irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
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@ -421,6 +685,56 @@ out_free_mem:
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return ret;
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}
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static const struct irq_domain_ops stm32_exti_h_domain_ops = {
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.alloc = stm32_exti_h_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int
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__init stm32_exti_hierarchy_init(const struct stm32_exti_drv_data *drv_data,
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struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain, *domain;
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struct stm32_exti_host_data *host_data;
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int ret, i;
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("interrupt-parent not found\n");
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return -EINVAL;
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}
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host_data = stm32_exti_host_init(drv_data, node);
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if (!host_data) {
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ret = -ENOMEM;
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goto out_free_mem;
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}
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for (i = 0; i < drv_data->bank_nr; i++)
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stm32_exti_chip_init(host_data, i, node);
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domain = irq_domain_add_hierarchy(parent_domain, 0,
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drv_data->bank_nr * IRQS_PER_BANK,
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node, &stm32_exti_h_domain_ops,
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host_data);
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if (!domain) {
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pr_err("%s: Could not register exti domain.\n", node->name);
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ret = -ENOMEM;
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goto out_unmap;
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}
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return 0;
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out_unmap:
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iounmap(host_data->base);
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out_free_mem:
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kfree(host_data->chips_data);
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kfree(host_data);
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return ret;
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}
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static int __init stm32f4_exti_of_init(struct device_node *np,
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struct device_node *parent)
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{
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@ -436,3 +750,11 @@ static int __init stm32h7_exti_of_init(struct device_node *np,
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}
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IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
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static int __init stm32mp1_exti_of_init(struct device_node *np,
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struct device_node *parent)
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{
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return stm32_exti_hierarchy_init(&stm32mp1_drv_data, np, parent);
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}
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IRQCHIP_DECLARE(stm32mp1_exti, "st,stm32mp1-exti", stm32mp1_exti_of_init);
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