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MIPS: MSP71xx: Add vectored interrupt support.
This patch will add vectored interrupt setups required for MIPS MT modes. irq_cic has been restructured and moved per irq handler to different file. irq_cic has been re wrote to support mips MT modes ( VSMP / SMTC ) [Ralf: fixed some more checkpatch warnings.] Signed-off-by: Anoop P A <anoop.pa@gmail.com> To: linux-mips@linux-mips.org To: linux-kernel@vger.kernel.org To: dhowells@redhat.com Patchwork: https://patchwork.linux-mips.org/patch/2041/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Anoop P A
Ralf Baechle
parent
3b042d0830
commit
92592c9cca
@ -6,7 +6,7 @@ obj-y += msp_prom.o msp_setup.o msp_irq.o \
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obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o
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obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o
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obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o
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obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o
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obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o msp_irq_per.o
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obj-$(CONFIG_PCI) += msp_pci.o
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obj-$(CONFIG_MSPETH) += msp_eth.o
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obj-$(CONFIG_USB_MSP71XX) += msp_usb.o
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@ -19,8 +19,6 @@
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#include <msp_int.h>
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extern void msp_int_handle(void);
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/* SLP bases systems */
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extern void msp_slp_irq_init(void);
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extern void msp_slp_irq_dispatch(void);
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@ -29,6 +27,18 @@ extern void msp_slp_irq_dispatch(void);
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extern void msp_cic_irq_init(void);
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extern void msp_cic_irq_dispatch(void);
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/* VSMP support init */
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extern void msp_vsmp_int_init(void);
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/* vectored interrupt implementation */
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/* SW0/1 interrupts are used for SMP/SMTC */
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static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); }
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static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); }
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static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); }
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static inline void usb_int_dispatch(void) { do_IRQ(MSP_INT_USB); }
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static inline void sec_int_dispatch(void) { do_IRQ(MSP_INT_SEC); }
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/*
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* The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded
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* hierarchical system. The first level are the direct MIPS interrupts
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@ -96,29 +106,57 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
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do_IRQ(MSP_INT_SW1);
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}
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static struct irqaction cascade_msp = {
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static struct irqaction cic_cascade_msp = {
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.handler = no_action,
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.name = "MSP cascade"
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.name = "MSP CIC cascade"
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};
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static struct irqaction per_cascade_msp = {
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.handler = no_action,
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.name = "MSP PER cascade"
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};
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void __init arch_init_irq(void)
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{
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/* assume we'll be using vectored interrupt mode except in UP mode*/
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#ifdef CONFIG_MIPS_MT
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BUG_ON(!cpu_has_vint);
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#endif
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/* initialize the 1st-level CPU based interrupt controller */
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mips_cpu_irq_init();
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#ifdef CONFIG_IRQ_MSP_CIC
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msp_cic_irq_init();
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#ifdef CONFIG_MIPS_MT
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set_vi_handler(MSP_INT_CIC, msp_cic_irq_dispatch);
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set_vi_handler(MSP_INT_MAC0, mac0_int_dispatch);
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set_vi_handler(MSP_INT_MAC1, mac1_int_dispatch);
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set_vi_handler(MSP_INT_SAR, mac2_int_dispatch);
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set_vi_handler(MSP_INT_USB, usb_int_dispatch);
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set_vi_handler(MSP_INT_SEC, sec_int_dispatch);
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#ifdef CONFIG_MIPS_MT_SMP
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msp_vsmp_int_init();
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#elif defined CONFIG_MIPS_MT_SMTC
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/*Set hwmask for all platform devices */
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irq_hwmask[MSP_INT_MAC0] = C_IRQ0;
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irq_hwmask[MSP_INT_MAC1] = C_IRQ1;
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irq_hwmask[MSP_INT_USB] = C_IRQ2;
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irq_hwmask[MSP_INT_SAR] = C_IRQ3;
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irq_hwmask[MSP_INT_SEC] = C_IRQ5;
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#endif /* CONFIG_MIPS_MT_SMP */
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#endif /* CONFIG_MIPS_MT */
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/* setup the cascaded interrupts */
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setup_irq(MSP_INT_CIC, &cascade_msp);
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setup_irq(MSP_INT_PER, &cascade_msp);
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setup_irq(MSP_INT_CIC, &cic_cascade_msp);
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setup_irq(MSP_INT_PER, &per_cascade_msp);
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#else
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/* setup the 2nd-level SLP register based interrupt controller */
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/* VSMP /SMTC support support is not enabled for SLP */
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msp_slp_irq_init();
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/* setup the cascaded SLP/PER interrupts */
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setup_irq(MSP_INT_SLP, &cascade_msp);
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setup_irq(MSP_INT_PER, &cascade_msp);
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setup_irq(MSP_INT_SLP, &cic_cascade_msp);
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setup_irq(MSP_INT_PER, &per_cascade_msp);
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#endif
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}
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@ -1,8 +1,7 @@
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/*
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* This file define the irq handler for MSP SLM subsystem interrupts.
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* Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c
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*
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* Copyright 2005-2007 PMC-Sierra, Inc, derived from irq_cpu.c
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* Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
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* This file define the irq handler for MSP CIC subsystem interrupts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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@ -16,119 +15,212 @@
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <msp_cic_int.h>
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#include <msp_regs.h>
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/*
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* NOTE: We are only enabling support for VPE0 right now.
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* External API
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*/
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extern void msp_per_irq_init(void);
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extern void msp_per_irq_dispatch(void);
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static inline void unmask_msp_cic_irq(unsigned int irq)
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{
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/* check for PER interrupt range */
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if (irq < MSP_PER_INTBASE)
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*CIC_VPE0_MSK_REG |= (1 << (irq - MSP_CIC_INTBASE));
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else
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*PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
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}
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static inline void mask_msp_cic_irq(unsigned int irq)
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{
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/* check for PER interrupt range */
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if (irq < MSP_PER_INTBASE)
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*CIC_VPE0_MSK_REG &= ~(1 << (irq - MSP_CIC_INTBASE));
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else
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*PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
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}
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/*
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* While we ack the interrupt interrupts are disabled and thus we don't need
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* to deal with concurrency issues. Same for msp_cic_irq_end.
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* Convenience Macro. Should be somewhere generic.
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*/
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static inline void ack_msp_cic_irq(unsigned int irq)
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#define get_current_vpe() \
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((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
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#ifdef CONFIG_SMP
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#define LOCK_VPE(flags, mtflags) \
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do { \
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local_irq_save(flags); \
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mtflags = dmt(); \
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} while (0)
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#define UNLOCK_VPE(flags, mtflags) \
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do { \
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emt(mtflags); \
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local_irq_restore(flags);\
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} while (0)
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#define LOCK_CORE(flags, mtflags) \
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do { \
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local_irq_save(flags); \
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mtflags = dvpe(); \
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} while (0)
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#define UNLOCK_CORE(flags, mtflags) \
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do { \
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evpe(mtflags); \
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local_irq_restore(flags);\
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} while (0)
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#else
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#define LOCK_VPE(flags, mtflags)
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#define UNLOCK_VPE(flags, mtflags)
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#endif
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/* ensure writes to cic are completed */
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static inline void cic_wmb(void)
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{
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mask_msp_cic_irq(irq);
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const volatile void __iomem *cic_mem = CIC_VPE0_MSK_REG;
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volatile u32 dummy_read;
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wmb();
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dummy_read = __raw_readl(cic_mem);
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dummy_read++;
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}
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static inline void unmask_cic_irq(unsigned int irq)
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{
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volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG;
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int vpe;
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#ifdef CONFIG_SMP
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unsigned int mtflags;
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unsigned long flags;
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/*
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* only really necessary for 18, 16-14 and sometimes 3:0 (since
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* these can be edge sensitive) but it doesn't hurt for the others.
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*/
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* Make sure we have IRQ affinity. It may have changed while
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* we were processing the IRQ.
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*/
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if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity))
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return;
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#endif
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/* check for PER interrupt range */
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if (irq < MSP_PER_INTBASE)
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*CIC_STS_REG = (1 << (irq - MSP_CIC_INTBASE));
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else
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*PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE));
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vpe = get_current_vpe();
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LOCK_VPE(flags, mtflags);
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cic_msk_reg[vpe] |= (1 << (irq - MSP_CIC_INTBASE));
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UNLOCK_VPE(flags, mtflags);
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cic_wmb();
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}
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static inline void mask_cic_irq(unsigned int irq)
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{
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volatile u32 *cic_msk_reg = CIC_VPE0_MSK_REG;
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int vpe = get_current_vpe();
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#ifdef CONFIG_SMP
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unsigned long flags, mtflags;
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#endif
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LOCK_VPE(flags, mtflags);
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cic_msk_reg[vpe] &= ~(1 << (irq - MSP_CIC_INTBASE));
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UNLOCK_VPE(flags, mtflags);
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cic_wmb();
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}
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static inline void msp_cic_irq_ack(unsigned int irq)
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{
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mask_cic_irq(irq);
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/*
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* Only really necessary for 18, 16-14 and sometimes 3:0
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* (since these can be edge sensitive) but it doesn't
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* hurt for the others
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*/
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*CIC_STS_REG = (1 << (irq - MSP_CIC_INTBASE));
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smtc_im_ack_irq(irq);
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}
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static void msp_cic_irq_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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unmask_cic_irq(irq);
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}
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/*Note: Limiting to VSMP . Not tested in SMTC */
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#ifdef CONFIG_MIPS_MT_SMP
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static inline int msp_cic_irq_set_affinity(unsigned int irq,
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const struct cpumask *cpumask)
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{
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int cpu;
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unsigned long flags;
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unsigned int mtflags;
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unsigned long imask = (1 << (irq - MSP_CIC_INTBASE));
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volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG;
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/* timer balancing should be disabled in kernel code */
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BUG_ON(irq == MSP_INT_VPE0_TIMER || irq == MSP_INT_VPE1_TIMER);
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LOCK_CORE(flags, mtflags);
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/* enable if any of each VPE's TCs require this IRQ */
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for_each_online_cpu(cpu) {
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if (cpumask_test_cpu(cpu, cpumask))
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cic_mask[cpu] |= imask;
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else
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cic_mask[cpu] &= ~imask;
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}
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UNLOCK_CORE(flags, mtflags);
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return 0;
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}
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#endif
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static struct irq_chip msp_cic_irq_controller = {
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.name = "MSP_CIC",
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.ack = ack_msp_cic_irq,
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.mask = ack_msp_cic_irq,
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.mask_ack = ack_msp_cic_irq,
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.unmask = unmask_msp_cic_irq,
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.mask = mask_cic_irq,
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.mask_ack = msp_cic_irq_ack,
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.unmask = unmask_cic_irq,
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.ack = msp_cic_irq_ack,
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.end = msp_cic_irq_end,
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#ifdef CONFIG_MIPS_MT_SMP
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.set_affinity = msp_cic_irq_set_affinity,
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#endif
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};
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void __init msp_cic_irq_init(void)
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{
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int i;
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/* Mask/clear interrupts. */
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*CIC_VPE0_MSK_REG = 0x00000000;
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*PER_INT_MSK_REG = 0x00000000;
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*CIC_VPE1_MSK_REG = 0x00000000;
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*CIC_STS_REG = 0xFFFFFFFF;
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*PER_INT_STS_REG = 0xFFFFFFFF;
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#if defined(CONFIG_PMC_MSP7120_GW) || \
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defined(CONFIG_PMC_MSP7120_EVAL)
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/*
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* The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI.
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* These inputs map to EXT_INT_POL[6:4] inside the CIC.
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* They are to be active low, level sensitive.
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*/
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* The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI.
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* These inputs map to EXT_INT_POL[6:4] inside the CIC.
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* They are to be active low, level sensitive.
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*/
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*CIC_EXT_CFG_REG &= 0xFFFF8F8F;
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#endif
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/* initialize all the IRQ descriptors */
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for (i = MSP_CIC_INTBASE; i < MSP_PER_INTBASE + 32; i++)
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for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) {
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set_irq_chip_and_handler(i, &msp_cic_irq_controller,
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handle_level_irq);
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#ifdef CONFIG_MIPS_MT_SMTC
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/* Mask of CIC interrupt */
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irq_hwmask[i] = C_IRQ4;
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#endif
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}
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/* Initialize the PER interrupt sub-system */
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msp_per_irq_init();
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}
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/* CIC masked by CIC vector processing before dispatch called */
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void msp_cic_irq_dispatch(void)
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{
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u32 pending;
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int intbase;
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intbase = MSP_CIC_INTBASE;
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pending = *CIC_STS_REG & *CIC_VPE0_MSK_REG;
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/* check for PER interrupt */
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if (pending == (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) {
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intbase = MSP_PER_INTBASE;
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pending = *PER_INT_STS_REG & *PER_INT_MSK_REG;
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}
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/* check for spurious interrupt */
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if (pending == 0x00000000) {
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printk(KERN_ERR
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"Spurious %s interrupt? status %08x, mask %08x\n",
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(intbase == MSP_CIC_INTBASE) ? "CIC" : "PER",
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(intbase == MSP_CIC_INTBASE) ?
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*CIC_STS_REG : *PER_INT_STS_REG,
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(intbase == MSP_CIC_INTBASE) ?
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*CIC_VPE0_MSK_REG : *PER_INT_MSK_REG);
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return;
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}
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/* check for the timer and dispatch it first */
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if ((intbase == MSP_CIC_INTBASE) &&
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(pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE))))
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volatile u32 *cic_msk_reg = (volatile u32 *)CIC_VPE0_MSK_REG;
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u32 cic_mask;
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u32 pending;
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int cic_status = *CIC_STS_REG;
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cic_mask = cic_msk_reg[get_current_vpe()];
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pending = cic_status & cic_mask;
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if (pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE))) {
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do_IRQ(MSP_INT_VPE0_TIMER);
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else
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do_IRQ(ffs(pending) + intbase - 1);
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} else if (pending & (1 << (MSP_INT_VPE1_TIMER - MSP_CIC_INTBASE))) {
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do_IRQ(MSP_INT_VPE1_TIMER);
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} else if (pending & (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) {
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msp_per_irq_dispatch();
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} else if (pending) {
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do_IRQ(ffs(pending) + MSP_CIC_INTBASE - 1);
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} else{
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spurious_interrupt();
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/* Re-enable the CIC cascaded interrupt. */
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irq_desc[MSP_INT_CIC].chip->end(MSP_INT_CIC);
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}
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}
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179
arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
Normal file
179
arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
Normal file
@ -0,0 +1,179 @@
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/*
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* Copyright 2010 PMC-Sierra, Inc, derived from irq_cpu.c
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*
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* This file define the irq handler for MSP PER subsystem interrupts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
#include <msp_cic_int.h>
|
||||
#include <msp_regs.h>
|
||||
|
||||
|
||||
/*
|
||||
* Convenience Macro. Should be somewhere generic.
|
||||
*/
|
||||
#define get_current_vpe() \
|
||||
((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* The PER registers must be protected from concurrent access.
|
||||
*/
|
||||
|
||||
static DEFINE_SPINLOCK(per_lock);
|
||||
#endif
|
||||
|
||||
/* ensure writes to per are completed */
|
||||
|
||||
static inline void per_wmb(void)
|
||||
{
|
||||
const volatile void __iomem *per_mem = PER_INT_MSK_REG;
|
||||
volatile u32 dummy_read;
|
||||
|
||||
wmb();
|
||||
dummy_read = __raw_readl(per_mem);
|
||||
dummy_read++;
|
||||
}
|
||||
|
||||
static inline void unmask_per_irq(unsigned int irq)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&per_lock, flags);
|
||||
*PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
|
||||
spin_unlock_irqrestore(&per_lock, flags);
|
||||
#else
|
||||
*PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
|
||||
#endif
|
||||
per_wmb();
|
||||
}
|
||||
|
||||
static inline void mask_per_irq(unsigned int irq)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&per_lock, flags);
|
||||
*PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
|
||||
spin_unlock_irqrestore(&per_lock, flags);
|
||||
#else
|
||||
*PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
|
||||
#endif
|
||||
per_wmb();
|
||||
}
|
||||
|
||||
static inline void msp_per_irq_enable(unsigned int irq)
|
||||
{
|
||||
unmask_per_irq(irq);
|
||||
}
|
||||
|
||||
static inline void msp_per_irq_disable(unsigned int irq)
|
||||
{
|
||||
mask_per_irq(irq);
|
||||
}
|
||||
|
||||
static unsigned int msp_per_irq_startup(unsigned int irq)
|
||||
{
|
||||
msp_per_irq_enable(irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define msp_per_irq_shutdown msp_per_irq_disable
|
||||
|
||||
static inline void msp_per_irq_ack(unsigned int irq)
|
||||
{
|
||||
mask_per_irq(irq);
|
||||
/*
|
||||
* In the PER interrupt controller, only bits 11 and 10
|
||||
* are write-to-clear, (SPI TX complete, SPI RX complete).
|
||||
* It does nothing for any others.
|
||||
*/
|
||||
|
||||
*PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE));
|
||||
|
||||
/* Re-enable the CIC cascaded interrupt and return */
|
||||
irq_desc[MSP_INT_CIC].chip->end(MSP_INT_CIC);
|
||||
}
|
||||
|
||||
static void msp_per_irq_end(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
|
||||
unmask_per_irq(irq);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static inline int msp_per_irq_set_affinity(unsigned int irq,
|
||||
const struct cpumask *affinity)
|
||||
{
|
||||
unsigned long flags;
|
||||
/*
|
||||
* Calls to ack, end, startup, enable are spinlocked in setup_irq and
|
||||
* __do_IRQ.Callers of this function do not spinlock,so we need to
|
||||
* do so ourselves.
|
||||
*/
|
||||
raw_spin_lock_irqsave(&irq_desc[irq].lock, flags);
|
||||
msp_per_irq_enable(irq);
|
||||
raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
|
||||
return 0;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct irq_chip msp_per_irq_controller = {
|
||||
.name = "MSP_PER",
|
||||
.startup = msp_per_irq_startup,
|
||||
.shutdown = msp_per_irq_shutdown,
|
||||
.enable = msp_per_irq_enable,
|
||||
.disable = msp_per_irq_disable,
|
||||
#ifdef CONFIG_SMP
|
||||
.set_affinity = msp_per_irq_set_affinity,
|
||||
#endif
|
||||
.ack = msp_per_irq_ack,
|
||||
.end = msp_per_irq_end,
|
||||
};
|
||||
|
||||
void __init msp_per_irq_init(void)
|
||||
{
|
||||
int i;
|
||||
/* Mask/clear interrupts. */
|
||||
*PER_INT_MSK_REG = 0x00000000;
|
||||
*PER_INT_STS_REG = 0xFFFFFFFF;
|
||||
/* initialize all the IRQ descriptors */
|
||||
for (i = MSP_PER_INTBASE; i < MSP_PER_INTBASE + 32; i++) {
|
||||
irq_desc[i].status = IRQ_DISABLED;
|
||||
irq_desc[i].action = NULL;
|
||||
irq_desc[i].depth = 1;
|
||||
irq_desc[i].chip = &msp_per_irq_controller;
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
irq_hwmask[i] = C_IRQ4;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
void msp_per_irq_dispatch(void)
|
||||
{
|
||||
u32 per_mask = *PER_INT_MSK_REG;
|
||||
u32 per_status = *PER_INT_STS_REG;
|
||||
u32 pending;
|
||||
|
||||
pending = per_status & per_mask;
|
||||
if (pending) {
|
||||
do_IRQ(ffs(pending) + MSP_PER_INTBASE - 1);
|
||||
} else {
|
||||
spurious_interrupt();
|
||||
/* Re-enable the CIC cascaded interrupt and return */
|
||||
irq_desc[MSP_INT_CIC].chip->end(MSP_INT_CIC);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user