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Merge tag 'drm-misc-fixes-2017-06-15' of git://anongit.freedesktop.org/git/drm-misc into drm-fixes
Driver Changes: - dw-hdmi: Fix compilation error if REGMAP_MMIO not selected (Laurent) - host1x: Fix incorrect return value (Christophe) - tegra: Shore up idr API usage in tegra staging code (Dmitry) - mgag200: Always use HiPri mode for G200e4v2 and limit max bandwidth (Mathieu) - mxsfb: Ensure display can be lit up without bootloader initialization (Fabio) Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Cc: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Cc: Dmitry Osipenko <digetx@gmail.com> Cc: Mathieu Larouche <mathieu.larouche@matrox.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> * tag 'drm-misc-fixes-2017-06-15' of git://anongit.freedesktop.org/git/drm-misc: drm: mxsfb_crtc: Reset the eLCDIF controller drm/mgag200: Fix to always set HiPri for G200e4 V2 drm/tegra: Correct idr_alloc() minimum id drm/tegra: Fix lockup on a use of staging API gpu: host1x: Fix error handling drm: dw-hdmi: Fix compilation breakage by selecting REGMAP_MMIO
This commit is contained in:
commit
91c0719c69
@ -1,6 +1,7 @@
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config DRM_DW_HDMI
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tristate
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select DRM_KMS_HELPER
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select REGMAP_MMIO
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config DRM_DW_HDMI_AHB_AUDIO
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tristate "Synopsys Designware AHB Audio interface"
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@ -1173,7 +1173,10 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
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if (IS_G200_SE(mdev)) {
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if (mdev->unique_rev_id >= 0x02) {
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if (mdev->unique_rev_id >= 0x04) {
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WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
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WREG8(MGAREG_CRTCEXT_DATA, 0);
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} else if (mdev->unique_rev_id >= 0x02) {
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u8 hi_pri_lvl;
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u32 bpp;
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u32 mb;
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@ -1639,6 +1642,10 @@ static int mga_vga_mode_valid(struct drm_connector *connector,
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if (mga_vga_calculate_mode_bandwidth(mode, bpp)
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> (30100 * 1024))
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return MODE_BANDWIDTH;
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} else {
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if (mga_vga_calculate_mode_bandwidth(mode, bpp)
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> (55000 * 1024))
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return MODE_BANDWIDTH;
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}
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} else if (mdev->type == G200_WB) {
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if (mode->hdisplay > 1280)
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@ -35,6 +35,13 @@
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#include "mxsfb_drv.h"
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#include "mxsfb_regs.h"
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#define MXS_SET_ADDR 0x4
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#define MXS_CLR_ADDR 0x8
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#define MODULE_CLKGATE BIT(30)
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#define MODULE_SFTRST BIT(31)
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/* 1 second delay should be plenty of time for block reset */
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#define RESET_TIMEOUT 1000000
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static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
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{
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return (val & mxsfb->devdata->hs_wdth_mask) <<
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@ -159,6 +166,36 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
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clk_disable_unprepare(mxsfb->clk_disp_axi);
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}
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/*
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* Clear the bit and poll it cleared. This is usually called with
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* a reset address and mask being either SFTRST(bit 31) or CLKGATE
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* (bit 30).
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*/
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static int clear_poll_bit(void __iomem *addr, u32 mask)
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{
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u32 reg;
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writel(mask, addr + MXS_CLR_ADDR);
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return readl_poll_timeout(addr, reg, !(reg & mask), 0, RESET_TIMEOUT);
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}
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static int mxsfb_reset_block(void __iomem *reset_addr)
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{
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int ret;
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ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
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if (ret)
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return ret;
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writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
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ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
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if (ret)
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return ret;
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return clear_poll_bit(reset_addr, MODULE_CLKGATE);
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}
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static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
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{
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struct drm_display_mode *m = &mxsfb->pipe.crtc.state->adjusted_mode;
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@ -173,6 +210,11 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
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*/
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mxsfb_enable_axi_clk(mxsfb);
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/* Mandatory eLCDIF reset as per the Reference Manual */
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err = mxsfb_reset_block(mxsfb->base);
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if (err)
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return;
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/* Clear the FIFOs */
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writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
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@ -451,18 +451,6 @@ fail:
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#ifdef CONFIG_DRM_TEGRA_STAGING
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static struct tegra_drm_context *
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tegra_drm_file_get_context(struct tegra_drm_file *file, u32 id)
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{
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struct tegra_drm_context *context;
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mutex_lock(&file->lock);
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context = idr_find(&file->contexts, id);
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mutex_unlock(&file->lock);
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return context;
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}
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static int tegra_gem_create(struct drm_device *drm, void *data,
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struct drm_file *file)
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{
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@ -551,7 +539,7 @@ static int tegra_client_open(struct tegra_drm_file *fpriv,
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if (err < 0)
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return err;
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err = idr_alloc(&fpriv->contexts, context, 0, 0, GFP_KERNEL);
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err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
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if (err < 0) {
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client->ops->close_channel(context);
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return err;
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@ -606,7 +594,7 @@ static int tegra_close_channel(struct drm_device *drm, void *data,
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mutex_lock(&fpriv->lock);
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context = tegra_drm_file_get_context(fpriv, args->context);
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context = idr_find(&fpriv->contexts, args->context);
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if (!context) {
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err = -EINVAL;
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goto unlock;
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@ -631,7 +619,7 @@ static int tegra_get_syncpt(struct drm_device *drm, void *data,
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mutex_lock(&fpriv->lock);
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context = tegra_drm_file_get_context(fpriv, args->context);
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context = idr_find(&fpriv->contexts, args->context);
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if (!context) {
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err = -ENODEV;
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goto unlock;
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@ -660,7 +648,7 @@ static int tegra_submit(struct drm_device *drm, void *data,
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mutex_lock(&fpriv->lock);
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context = tegra_drm_file_get_context(fpriv, args->context);
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context = idr_find(&fpriv->contexts, args->context);
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if (!context) {
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err = -ENODEV;
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goto unlock;
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@ -685,7 +673,7 @@ static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
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mutex_lock(&fpriv->lock);
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context = tegra_drm_file_get_context(fpriv, args->context);
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context = idr_find(&fpriv->contexts, args->context);
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if (!context) {
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err = -ENODEV;
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goto unlock;
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@ -172,7 +172,7 @@ static int host1x_probe(struct platform_device *pdev)
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host->rst = devm_reset_control_get(&pdev->dev, "host1x");
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if (IS_ERR(host->rst)) {
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err = PTR_ERR(host->clk);
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err = PTR_ERR(host->rst);
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dev_err(&pdev->dev, "failed to get reset: %d\n", err);
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return err;
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}
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