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drm/amdgpu: fix the gart table cleared issue for S3
Something writes over the first 8 MB so reserve this on vega10 until we root cause it. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -607,6 +607,7 @@ struct amdgpu_mc {
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uint32_t srbm_soft_reset;
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struct amdgpu_mode_mc_save save;
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bool prt_warning;
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uint64_t stolen_size;
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/* apertures */
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u64 shared_aperture_start;
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u64 shared_aperture_end;
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@ -1121,7 +1121,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
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/* Change the size here instead of the init above so only lpfn is affected */
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amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
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r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
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r = amdgpu_bo_create(adev, adev->mc.stolen_size, PAGE_SIZE, true,
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AMDGPU_GEM_DOMAIN_VRAM,
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AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
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AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
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@ -834,6 +834,8 @@ static int gmc_v6_0_sw_init(void *handle)
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adev->mc.mc_mask = 0xffffffffffULL;
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adev->mc.stolen_size = 256 * 1024;
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adev->need_dma32 = false;
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dma_bits = adev->need_dma32 ? 32 : 40;
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r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
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@ -970,6 +970,8 @@ static int gmc_v7_0_sw_init(void *handle)
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*/
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adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
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adev->mc.stolen_size = 256 * 1024;
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/* set DMA mask + need_dma32 flags.
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* PCIE - can handle 40-bits.
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* IGP - can handle 40-bits
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@ -1054,6 +1054,8 @@ static int gmc_v8_0_sw_init(void *handle)
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*/
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adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
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adev->mc.stolen_size = 256 * 1024;
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/* set DMA mask + need_dma32 flags.
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* PCIE - can handle 40-bits.
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* IGP - can handle 40-bits
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@ -572,6 +572,12 @@ static int gmc_v9_0_sw_init(void *handle)
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*/
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adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
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/*
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* It needs to reserve 8M stolen memory for vega10
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* TODO: Figure out how to avoid that...
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*/
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adev->mc.stolen_size = 8 * 1024 * 1024;
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/* set DMA mask + need_dma32 flags.
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* PCIE - can handle 44-bits.
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* IGP - can handle 44-bits
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