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Merge branch 'master' of /pub/scm/linux/kernel/git/torvalds/linux-2.6

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Steve French 2009-04-30 15:36:52 +00:00
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8
Documentation/ABI/testing/sysfs-firmware-acpi
View File

@ -69,9 +69,13 @@ Description:
gpe1F: 0 invalid
gpe_all: 1192
sci: 1194
sci_not: 0
sci - The total number of times the ACPI SCI
has claimed an interrupt.
sci - The number of times the ACPI SCI
has been called and claimed an interrupt.
sci_not - The number of times the ACPI SCI
has been called and NOT claimed an interrupt.
gpe_all - count of SCI caused by GPEs.

6
Documentation/DocBook/kernel-api.tmpl
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@ -190,16 +190,20 @@ X!Ekernel/module.c
!Edrivers/pci/pci.c
!Edrivers/pci/pci-driver.c
!Edrivers/pci/remove.c
!Edrivers/pci/pci-acpi.c
!Edrivers/pci/search.c
!Edrivers/pci/msi.c
!Edrivers/pci/bus.c
!Edrivers/pci/access.c
!Edrivers/pci/irq.c
!Edrivers/pci/htirq.c
<!-- FIXME: Removed for now since no structured comments in source
X!Edrivers/pci/hotplug.c
-->
!Edrivers/pci/probe.c
!Edrivers/pci/slot.c
!Edrivers/pci/rom.c
!Edrivers/pci/iov.c
!Idrivers/pci/pci-sysfs.c
</sect1>
<sect1><title>PCI Hotplug Support Library</title>
!Edrivers/pci/hotplug/pci_hotplug_core.c

8
Documentation/filesystems/caching/cachefiles.txt
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@ -407,7 +407,7 @@ A NOTE ON SECURITY
==================
CacheFiles makes use of the split security in the task_struct. It allocates
its own task_security structure, and redirects current->act_as to point to it
its own task_security structure, and redirects current->cred to point to it
when it acts on behalf of another process, in that process's context.
The reason it does this is that it calls vfs_mkdir() and suchlike rather than
@ -429,9 +429,9 @@ This means it may lose signals or ptrace events for example, and affects what
the process looks like in /proc.
So CacheFiles makes use of a logical split in the security between the
objective security (task->sec) and the subjective security (task->act_as). The
objective security holds the intrinsic security properties of a process and is
never overridden. This is what appears in /proc, and is what is used when a
objective security (task->real_cred) and the subjective security (task->cred).
The objective security holds the intrinsic security properties of a process and
is never overridden. This is what appears in /proc, and is what is used when a
process is the target of an operation by some other process (SIGKILL for
example).

3
Documentation/filesystems/vfs.txt
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@ -277,8 +277,7 @@ or bottom half).
unfreeze_fs: called when VFS is unlocking a filesystem and making it writable
again.
statfs: called when the VFS needs to get filesystem statistics. This
is called with the kernel lock held
statfs: called when the VFS needs to get filesystem statistics.
remount_fs: called when the filesystem is remounted. This is called
with the kernel lock held

17
Documentation/isdn/00-INDEX
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@ -2,8 +2,14 @@
- this file (info on ISDN implementation for Linux)
CREDITS
- list of the kind folks that brought you this stuff.
HiSax.cert
- information about the ITU approval certification of the HiSax driver.
INTERFACE
- description of Linklevel and Hardwarelevel ISDN interface.
- description of isdn4linux Link Level and Hardware Level interfaces.
INTERFACE.fax
- description of the fax subinterface of isdn4linux.
INTERFACE.CAPI
- description of kernel CAPI Link Level to Hardware Level interface.
README
- general info on what you need and what to do for Linux ISDN.
README.FAQ
@ -12,6 +18,8 @@ README.audio
- info for running audio over ISDN.
README.fax
- info for using Fax over ISDN.
README.gigaset
- info on the drivers for Siemens Gigaset ISDN adapters.
README.icn
- info on the ICN-ISDN-card and its driver.
README.HiSax
@ -37,7 +45,8 @@ README.diversion
README.sc
- info on driver for Spellcaster cards.
README.x25
_ info for running X.25 over ISDN.
- info for running X.25 over ISDN.
README.hysdn
- info on driver for Hypercope active HYSDN cards
- info on driver for Hypercope active HYSDN cards
README.mISDN
- info on the Modular ISDN subsystem (mISDN).

213
Documentation/isdn/INTERFACE.CAPI Normal file
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@ -0,0 +1,213 @@
Kernel CAPI Interface to Hardware Drivers
-----------------------------------------
1. Overview
From the CAPI 2.0 specification:
COMMON-ISDN-API (CAPI) is an application programming interface standard used
to access ISDN equipment connected to basic rate interfaces (BRI) and primary
rate interfaces (PRI).
Kernel CAPI operates as a dispatching layer between CAPI applications and CAPI
hardware drivers. Hardware drivers register ISDN devices (controllers, in CAPI
lingo) with Kernel CAPI to indicate their readiness to provide their service
to CAPI applications. CAPI applications also register with Kernel CAPI,
requesting association with a CAPI device. Kernel CAPI then dispatches the
application registration to an available device, forwarding it to the
corresponding hardware driver. Kernel CAPI then forwards CAPI messages in both
directions between the application and the hardware driver.
Format and semantics of CAPI messages are specified in the CAPI 2.0 standard.
This standard is freely available from http://www.capi.org.
2. Driver and Device Registration
CAPI drivers optionally register themselves with Kernel CAPI by calling the
Kernel CAPI function register_capi_driver() with a pointer to a struct
capi_driver. This structure must be filled with the name and revision of the
driver, and optionally a pointer to a callback function, add_card(). The
registration can be revoked by calling the function unregister_capi_driver()
with a pointer to the same struct capi_driver.
CAPI drivers must register each of the ISDN devices they control with Kernel
CAPI by calling the Kernel CAPI function attach_capi_ctr() with a pointer to a
struct capi_ctr before they can be used. This structure must be filled with
the names of the driver and controller, and a number of callback function
pointers which are subsequently used by Kernel CAPI for communicating with the
driver. The registration can be revoked by calling the function
detach_capi_ctr() with a pointer to the same struct capi_ctr.
Before the device can be actually used, the driver must fill in the device
information fields 'manu', 'version', 'profile' and 'serial' in the capi_ctr
structure of the device, and signal its readiness by calling capi_ctr_ready().
From then on, Kernel CAPI may call the registered callback functions for the
device.
If the device becomes unusable for any reason (shutdown, disconnect ...), the
driver has to call capi_ctr_reseted(). This will prevent further calls to the
callback functions by Kernel CAPI.
3. Application Registration and Communication
Kernel CAPI forwards registration requests from applications (calls to CAPI
operation CAPI_REGISTER) to an appropriate hardware driver by calling its
register_appl() callback function. A unique Application ID (ApplID, u16) is
allocated by Kernel CAPI and passed to register_appl() along with the
parameter structure provided by the application. This is analogous to the
open() operation on regular files or character devices.
After a successful return from register_appl(), CAPI messages from the
application may be passed to the driver for the device via calls to the
send_message() callback function. The CAPI message to send is stored in the
data portion of an skb. Conversely, the driver may call Kernel CAPI's
capi_ctr_handle_message() function to pass a received CAPI message to Kernel
CAPI for forwarding to an application, specifying its ApplID.
Deregistration requests (CAPI operation CAPI_RELEASE) from applications are
forwarded as calls to the release_appl() callback function, passing the same
ApplID as with register_appl(). After return from release_appl(), no CAPI
messages for that application may be passed to or from the device anymore.
4. Data Structures
4.1 struct capi_driver
This structure describes a Kernel CAPI driver itself. It is used in the
register_capi_driver() and unregister_capi_driver() functions, and contains
the following non-private fields, all to be set by the driver before calling
register_capi_driver():
char name[32]
the name of the driver, as a zero-terminated ASCII string
char revision[32]
the revision number of the driver, as a zero-terminated ASCII string
int (*add_card)(struct capi_driver *driver, capicardparams *data)
a callback function pointer (may be NULL)
4.2 struct capi_ctr
This structure describes an ISDN device (controller) handled by a Kernel CAPI
driver. After registration via the attach_capi_ctr() function it is passed to
all controller specific lower layer interface and callback functions to
identify the controller to operate on.
It contains the following non-private fields:
- to be set by the driver before calling attach_capi_ctr():
struct module *owner
pointer to the driver module owning the device
void *driverdata
an opaque pointer to driver specific data, not touched by Kernel CAPI
char name[32]
the name of the controller, as a zero-terminated ASCII string
char *driver_name
the name of the driver, as a zero-terminated ASCII string
int (*load_firmware)(struct capi_ctr *ctrlr, capiloaddata *ldata)
(optional) pointer to a callback function for sending firmware and
configuration data to the device
void (*reset_ctr)(struct capi_ctr *ctrlr)
pointer to a callback function for performing a reset on the device,
releasing all registered applications
void (*register_appl)(struct capi_ctr *ctrlr, u16 applid,
capi_register_params *rparam)
void (*release_appl)(struct capi_ctr *ctrlr, u16 applid)
pointers to callback functions for registration and deregistration of
applications with the device
u16 (*send_message)(struct capi_ctr *ctrlr, struct sk_buff *skb)
pointer to a callback function for sending a CAPI message to the
device
char *(*procinfo)(struct capi_ctr *ctrlr)
pointer to a callback function returning the entry for the device in
the CAPI controller info table, /proc/capi/controller
read_proc_t *ctr_read_proc
pointer to the read_proc callback function for the device's proc file
system entry, /proc/capi/controllers/<n>; will be called with a
pointer to the device's capi_ctr structure as the last (data) argument
- to be filled in before calling capi_ctr_ready():
u8 manu[CAPI_MANUFACTURER_LEN]
value to return for CAPI_GET_MANUFACTURER
capi_version version
value to return for CAPI_GET_VERSION
capi_profile profile
value to return for CAPI_GET_PROFILE
u8 serial[CAPI_SERIAL_LEN]
value to return for CAPI_GET_SERIAL
5. Lower Layer Interface Functions
(declared in <linux/isdn/capilli.h>)
void register_capi_driver(struct capi_driver *drvr)
void unregister_capi_driver(struct capi_driver *drvr)
register/unregister a driver with Kernel CAPI
int attach_capi_ctr(struct capi_ctr *ctrlr)
int detach_capi_ctr(struct capi_ctr *ctrlr)
register/unregister a device (controller) with Kernel CAPI
void capi_ctr_ready(struct capi_ctr *ctrlr)
void capi_ctr_reseted(struct capi_ctr *ctrlr)
signal controller ready/not ready
void capi_ctr_suspend_output(struct capi_ctr *ctrlr)
void capi_ctr_resume_output(struct capi_ctr *ctrlr)
signal suspend/resume
void capi_ctr_handle_message(struct capi_ctr * ctrlr, u16 applid,
struct sk_buff *skb)
pass a received CAPI message to Kernel CAPI
for forwarding to the specified application
6. Helper Functions and Macros
Library functions (from <linux/isdn/capilli.h>):
void capilib_new_ncci(struct list_head *head, u16 applid,
u32 ncci, u32 winsize)
void capilib_free_ncci(struct list_head *head, u16 applid, u32 ncci)
void capilib_release_appl(struct list_head *head, u16 applid)
void capilib_release(struct list_head *head)
void capilib_data_b3_conf(struct list_head *head, u16 applid,
u32 ncci, u16 msgid)
u16 capilib_data_b3_req(struct list_head *head, u16 applid,
u32 ncci, u16 msgid)
Macros to extract/set element values from/in a CAPI message header
(from <linux/isdn/capiutil.h>):
Get Macro Set Macro Element (Type)
CAPIMSG_LEN(m) CAPIMSG_SETLEN(m, len) Total Length (u16)
CAPIMSG_APPID(m) CAPIMSG_SETAPPID(m, applid) ApplID (u16)
CAPIMSG_COMMAND(m) CAPIMSG_SETCOMMAND(m,cmd) Command (u8)
CAPIMSG_SUBCOMMAND(m) CAPIMSG_SETSUBCOMMAND(m, cmd) Subcommand (u8)
CAPIMSG_CMD(m) - Command*256
+ Subcommand (u16)
CAPIMSG_MSGID(m) CAPIMSG_SETMSGID(m, msgid) Message Number (u16)
CAPIMSG_CONTROL(m) CAPIMSG_SETCONTROL(m, contr) Controller/PLCI/NCCI
(u32)
CAPIMSG_DATALEN(m) CAPIMSG_SETDATALEN(m, len) Data Length (u16)

2
Documentation/kernel-parameters.txt
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@ -1620,6 +1620,8 @@ and is between 256 and 4096 characters. It is defined in the file
nowb [ARM]
nox2apic [X86-64,APIC] Do not enable x2APIC mode.
nptcg= [IA64] Override max number of concurrent global TLB
purges which is reported from either PAL_VM_SUMMARY or
SAL PALO.

4
Documentation/laptops/thinkpad-acpi.txt
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@ -1,7 +1,7 @@
ThinkPad ACPI Extras Driver
Version 0.22
November 23rd, 2008
Version 0.23
April 10th, 2009
Borislav Deianov <borislav@users.sf.net>
Henrique de Moraes Holschuh <hmh@hmh.eng.br>

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15
Documentation/logo.txt
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@ -1,4 +1,13 @@
Tux is taking a three month sabbatical to work as a barber, so Tuz is
standing in. He's taken pains to ensure you'll hardly notice.
This is the full-colour version of the currently unofficial Linux logo
("currently unofficial" just means that there has been no paperwork and
that I have not really announced it yet). It was created by Larry Ewing,
and is freely usable as long as you acknowledge Larry as the original
artist.
Note that there are black-and-white versions of this available that
scale down to smaller sizes and are better for letterheads or whatever
you want to use it for: for the full range of logos take a look at
Larry's web-page:
http://www.isc.tamu.edu/~lewing/linux/
Image by Andrew McGown and Josh Bush. Image is licensed CC BY-SA.

89
Documentation/powerpc/booting-without-of.txt
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@ -43,12 +43,11 @@ Table of Contents
2) Representing devices without a current OF specification
a) PHY nodes
b) Interrupt controllers
c) CFI or JEDEC memory-mapped NOR flash
d) 4xx/Axon EMAC ethernet nodes
e) Xilinx IP cores
f) USB EHCI controllers
g) MDIO on GPIOs
h) SPI busses
c) 4xx/Axon EMAC ethernet nodes
d) Xilinx IP cores
e) USB EHCI controllers
f) MDIO on GPIOs
g) SPI busses
VII - Marvell Discovery mv64[345]6x System Controller chips
1) The /system-controller node
@ -999,7 +998,7 @@ compatibility.
translation of SOC addresses for memory mapped SOC registers.
- bus-frequency: Contains the bus frequency for the SOC node.
Typically, the value of this field is filled in by the boot
loader.
loader.
Recommended properties:
@ -1287,71 +1286,7 @@ platforms are moved over to use the flattened-device-tree model.
device_type = "open-pic";
};
c) CFI or JEDEC memory-mapped NOR flash
Flash chips (Memory Technology Devices) are often used for solid state
file systems on embedded devices.
- compatible : should contain the specific model of flash chip(s)
used, if known, followed by either "cfi-flash" or "jedec-flash"
- reg : Address range of the flash chip
- bank-width : Width (in bytes) of the flash bank. Equal to the
device width times the number of interleaved chips.
- device-width : (optional) Width of a single flash chip. If
omitted, assumed to be equal to 'bank-width'.
- #address-cells, #size-cells : Must be present if the flash has
sub-nodes representing partitions (see below). In this case
both #address-cells and #size-cells must be equal to 1.
For JEDEC compatible devices, the following additional properties
are defined:
- vendor-id : Contains the flash chip's vendor id (1 byte).
- device-id : Contains the flash chip's device id (1 byte).
In addition to the information on the flash bank itself, the
device tree may optionally contain additional information
describing partitions of the flash address space. This can be
used on platforms which have strong conventions about which
portions of the flash are used for what purposes, but which don't
use an on-flash partition table such as RedBoot.
Each partition is represented as a sub-node of the flash device.
Each node's name represents the name of the corresponding
partition of the flash device.
Flash partitions
- reg : The partition's offset and size within the flash bank.
- label : (optional) The label / name for this flash partition.
If omitted, the label is taken from the node name (excluding
the unit address).
- read-only : (optional) This parameter, if present, is a hint to
Linux that this flash partition should only be mounted
read-only. This is usually used for flash partitions
containing early-boot firmware images or data which should not
be clobbered.
Example:
flash@ff000000 {
compatible = "amd,am29lv128ml", "cfi-flash";
reg = <ff000000 01000000>;
bank-width = <4>;
device-width = <1>;
#address-cells = <1>;
#size-cells = <1>;
fs@0 {
label = "fs";
reg = <0 f80000>;
};
firmware@f80000 {
label ="firmware";
reg = <f80000 80000>;
read-only;
};
};
d) 4xx/Axon EMAC ethernet nodes
c) 4xx/Axon EMAC ethernet nodes
The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
the Axon bridge. To operate this needs to interact with a ths
@ -1499,7 +1434,7 @@ platforms are moved over to use the flattened-device-tree model.
available.
For Axon: 0x0000012a
e) Xilinx IP cores
d) Xilinx IP cores
The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
@ -1761,7 +1696,7 @@ platforms are moved over to use the flattened-device-tree model.
listed above, nodes for these devices should include a phy-handle
property, and may include other common network device properties
like local-mac-address.
iv) Xilinx Uartlite
Xilinx uartlite devices are simple fixed speed serial ports.
@ -1793,7 +1728,7 @@ platforms are moved over to use the flattened-device-tree model.
- reg-offset : A value of 3 is required
- reg-shift : A value of 2 is required
f) USB EHCI controllers
e) USB EHCI controllers
Required properties:
- compatible : should be "usb-ehci".
@ -1819,7 +1754,7 @@ platforms are moved over to use the flattened-device-tree model.
big-endian;
};
g) MDIO on GPIOs
f) MDIO on GPIOs
Currently defined compatibles:
- virtual,gpio-mdio
@ -1839,7 +1774,7 @@ platforms are moved over to use the flattened-device-tree model.
&qe_pio_c 6>;
};
h) SPI (Serial Peripheral Interface) busses
g) SPI (Serial Peripheral Interface) busses
SPI busses can be described with a node for the SPI master device
and a set of child nodes for each SPI slave on the bus. For this

80
Documentation/powerpc/dts-bindings/mtd-physmap.txt Normal file
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@ -0,0 +1,80 @@
CFI or JEDEC memory-mapped NOR flash
Flash chips (Memory Technology Devices) are often used for solid state
file systems on embedded devices.
- compatible : should contain the specific model of flash chip(s)
used, if known, followed by either "cfi-flash" or "jedec-flash"
- reg : Address range(s) of the flash chip(s)
It's possible to (optionally) define multiple "reg" tuples so that
non-identical NOR chips can be described in one flash node.
- bank-width : Width (in bytes) of the flash bank. Equal to the
device width times the number of interleaved chips.
- device-width : (optional) Width of a single flash chip. If
omitted, assumed to be equal to 'bank-width'.
- #address-cells, #size-cells : Must be present if the flash has
sub-nodes representing partitions (see below). In this case
both #address-cells and #size-cells must be equal to 1.
For JEDEC compatible devices, the following additional properties
are defined:
- vendor-id : Contains the flash chip's vendor id (1 byte).
- device-id : Contains the flash chip's device id (1 byte).
In addition to the information on the flash bank itself, the
device tree may optionally contain additional information
describing partitions of the flash address space. This can be
used on platforms which have strong conventions about which
portions of the flash are used for what purposes, but which don't
use an on-flash partition table such as RedBoot.
Each partition is represented as a sub-node of the flash device.
Each node's name represents the name of the corresponding
partition of the flash device.
Flash partitions
- reg : The partition's offset and size within the flash bank.
- label : (optional) The label / name for this flash partition.
If omitted, the label is taken from the node name (excluding
the unit address).
- read-only : (optional) This parameter, if present, is a hint to
Linux that this flash partition should only be mounted
read-only. This is usually used for flash partitions
containing early-boot firmware images or data which should not
be clobbered.
Example:
flash@ff000000 {
compatible = "amd,am29lv128ml", "cfi-flash";
reg = <ff000000 01000000>;
bank-width = <4>;
device-width = <1>;
#address-cells = <1>;
#size-cells = <1>;
fs@0 {
label = "fs";
reg = <0 f80000>;
};
firmware@f80000 {
label ="firmware";
reg = <f80000 80000>;
read-only;
};
};
Here an example with multiple "reg" tuples:
flash@f0000000,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,PC48F4400P0VB", "cfi-flash";
reg = <0 0x00000000 0x02000000
0 0x02000000 0x02000000>;
bank-width = <2>;
partition@0 {
label = "test-part1";
reg = <0 0x04000000>;
};
};

6
Documentation/spi/spi-summary
View File

@ -511,10 +511,16 @@ SPI MASTER METHODS
This sets up the device clock rate, SPI mode, and word sizes.
Drivers may change the defaults provided by board_info, and then
call spi_setup(spi) to invoke this routine. It may sleep.
Unless each SPI slave has its own configuration registers, don't
change them right away ... otherwise drivers could corrupt I/O
that's in progress for other SPI devices.
** BUG ALERT: for some reason the first version of
** many spi_master drivers seems to get this wrong.
** When you code setup(), ASSUME that the controller
** is actively processing transfers for another device.
master->transfer(struct spi_device *spi, struct spi_message *message)
This must not sleep. Its responsibility is arrange that the
transfer happens and its complete() callback is issued. The two

28
MAINTAINERS
View File

@ -1337,12 +1337,9 @@ L: cbe-oss-dev@ozlabs.org
W: http://www.ibm.com/developerworks/power/cell/
S: Supported
F: arch/powerpc/include/asm/cell*.h
F: arch/powerpc/include/asm/lv1call.h
F: arch/powerpc/include/asm/ps3*.h
F: arch/powerpc/include/asm/spu*.h
F: arch/powerpc/oprofile/*cell*
F: arch/powerpc/platforms/cell/
F: arch/powerpc/platforms/ps3/
CERTIFIED WIRELESS USB (WUSB) SUBSYSTEM:
P: David Vrabel
@ -2065,6 +2062,8 @@ F: drivers/infiniband/hw/ehca/
EMBEDDED LINUX
P: Paul Gortmaker
M: paul.gortmaker@windriver.com
P: Matt Mackall
M: mpm@selenic.com
P: David Woodhouse
M: dwmw2@infradead.org
L: linux-embedded@vger.kernel.org
@ -2562,7 +2561,6 @@ F: kernel/power/
F: include/linux/suspend.h
F: include/linux/freezer.h
F: include/linux/pm.h
F: include/asm-*/suspend*.h
F: arch/*/include/asm/suspend*.h
HID CORE LAYER
@ -2760,7 +2758,7 @@ IDE SUBSYSTEM
P: Bartlomiej Zolnierkiewicz
M: bzolnier@gmail.com
L: linux-ide@vger.kernel.org
T: quilt kernel.org/pub/linux/kernel/people/bart/pata-2.6/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/bart/ide-2.6.git
S: Maintained
F: Documentation/ide/
F: drivers/ide/
@ -3340,7 +3338,7 @@ P: Eduard - Gabriel Munteanu
M: eduard.munteanu@linux360.ro
L: linux-kernel@vger.kernel.org
S: Maintained
F: Documentation/vm/kmemtrace.txt
F: Documentation/trace/kmemtrace.txt
F: include/trace/kmemtrace.h
F: kernel/trace/kmemtrace.c
@ -3450,7 +3448,7 @@ P: Matt Porter
M: mporter@kernel.crashing.org
W: http://www.penguinppc.org/
L: linuxppc-dev@ozlabs.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git
S: Maintained
LINUX FOR POWERPC EMBEDDED XILINX VIRTEX
@ -3993,8 +3991,8 @@ NETWORKING [GENERAL]
P: David S. Miller
M: davem@davemloft.net
L: netdev@vger.kernel.org
W: http://linux-net.osdl.org/
T: git kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6.git
W: http://www.linuxfoundation.org/en/Net
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.git
S: Maintained
F: net/
F: include/net/
@ -4035,6 +4033,13 @@ F: net/wireless/
F: include/net/ieee80211*
F: include/net/wireless.h
NETWORKING DRIVERS
L: netdev@vger.kernel.org
W: http://www.linuxfoundation.org/en/Net
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.git
S: Odd Fixes
F: drivers/net/
NETXEN (1/10) GbE SUPPORT
P: Dhananjay Phadke
M: dhananjay@netxen.com
@ -4506,7 +4511,9 @@ F: arch/powerpc/include/asm/ps3*.h
F: arch/powerpc/platforms/ps3/
F: drivers/*/ps3*
F: drivers/ps3/
F: drivers/rtc/rtc-ps3.c
F: drivers/usb/host/*ps3.c
F: sound/ppc/snd_ps3*
PS3VRAM DRIVER
P: Jim Paris
@ -5404,7 +5411,6 @@ F: kernel/power/
F: include/linux/suspend.h
F: include/linux/freezer.h
F: include/linux/pm.h
F: include/asm-*/suspend.h
SVGA HANDLING
P: Martin Mares
@ -5638,7 +5644,7 @@ L: uclinux-dev@uclinux.org (subscribers-only)
S: Maintained
F: arch/m68knommu/
UCLINUX FOR RENESAS H8/300
UCLINUX FOR RENESAS H8/300 (H8300)
P: Yoshinori Sato
M: ysato@users.sourceforge.jp
W: http://uclinux-h8.sourceforge.jp/

4
Makefile
View File

@ -1,8 +1,8 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 30
EXTRAVERSION = -rc2
NAME = Temporary Tasmanian Devil
EXTRAVERSION = -rc4
NAME = Vindictive Armadillo
# *DOCUMENTATION*
# To see a list of typical targets execute "make help"

2
arch/alpha/include/asm/percpu.h
View File

@ -73,6 +73,6 @@ extern unsigned long __per_cpu_offset[NR_CPUS];
#endif /* SMP */
#define DECLARE_PER_CPU(type, name) extern __typeof__(type) per_cpu_var(name)
#include <asm-generic/percpu.h>
#endif /* __ALPHA_PERCPU_H */

3
arch/alpha/kernel/head.S
View File

@ -7,10 +7,11 @@
* the kernel global pointer and jump to the kernel entry-point.
*/
#include <linux/init.h>
#include <asm/system.h>
#include <asm/asm-offsets.h>
.section .text.head, "ax"
__HEAD
.globl swapper_pg_dir
.globl _stext
swapper_pg_dir=SWAPPER_PGD

2
arch/alpha/kernel/vmlinux.lds.S
View File

@ -16,7 +16,7 @@ SECTIONS
_text = .; /* Text and read-only data */
.text : {
*(.text.head)
HEAD_TEXT
TEXT_TEXT
SCHED_TEXT
LOCK_TEXT

2
arch/arm/include/asm/unistd.h
View File

@ -387,6 +387,8 @@
#define __NR_dup3 (__NR_SYSCALL_BASE+358)
#define __NR_pipe2 (__NR_SYSCALL_BASE+359)
#define __NR_inotify_init1 (__NR_SYSCALL_BASE+360)
#define __NR_preadv (__NR_SYSCALL_BASE+361)
#define __NR_pwritev (__NR_SYSCALL_BASE+362)
/*
* The following SWIs are ARM private.

2
arch/arm/kernel/calls.S
View File

@ -370,6 +370,8 @@
CALL(sys_dup3)
CALL(sys_pipe2)
/* 360 */ CALL(sys_inotify_init1)
CALL(sys_preadv)
CALL(sys_pwritev)
#ifndef syscalls_counted
.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
#define syscalls_counted

19
arch/arm/kernel/sys_oabi-compat.c
View File

@ -177,21 +177,12 @@ asmlinkage long sys_oabi_fstatat64(int dfd,
int flag)
{
struct kstat stat;
int error = -EINVAL;
int error;
if ((flag & ~AT_SYMLINK_NOFOLLOW) != 0)
goto out;
if (flag & AT_SYMLINK_NOFOLLOW)
error = vfs_lstat_fd(dfd, filename, &stat);
else
error = vfs_stat_fd(dfd, filename, &stat);
if (!error)
error = cp_oldabi_stat64(&stat, statbuf);
out:
return error;
error = vfs_fstatat(dfd, filename, &stat, flag);
if (error)
return error;
return cp_oldabi_stat64(&stat, statbuf);
}
struct oabi_flock64 {

2
arch/arm/mach-at91/at91rm9200_time.c
View File

@ -85,7 +85,7 @@ static struct irqaction at91rm9200_timer_irq = {
.handler = at91rm9200_timer_interrupt
};
static cycle_t read_clk32k(void)
static cycle_t read_clk32k(struct clocksource *cs)
{
return read_CRTR();
}

2
arch/arm/mach-at91/at91sam926x_time.c
View File

@ -31,7 +31,7 @@ static u32 pit_cnt; /* access only w/system irq blocked */
* Clocksource: just a monotonic counter of MCK/16 cycles.
* We don't care whether or not PIT irqs are enabled.
*/
static cycle_t read_pit_clk(void)
static cycle_t read_pit_clk(struct clocksource *cs)
{
unsigned long flags;
u32 elapsed;

2
arch/arm/mach-davinci/time.c
View File

@ -238,7 +238,7 @@ static void __init timer_init(void)
/*
* clocksource
*/
static cycle_t read_cycles(void)
static cycle_t read_cycles(struct clocksource *cs)
{
struct timer_s *t = &timers[TID_CLOCKSOURCE];

1
arch/arm/mach-imx/include/mach/gpio.h
View File

@ -1,6 +1,7 @@
#ifndef _IMX_GPIO_H
#include <linux/kernel.h>
#include <mach/hardware.h>
#include <mach/imx-regs.h>
#define IMX_GPIO_ALLOC_MODE_NORMAL 0

2
arch/arm/mach-imx/time.c
View File

@ -73,7 +73,7 @@ static void __init imx_timer_hardware_init(void)
IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_TEN;
}
cycle_t imx_get_cycles(void)
cycle_t imx_get_cycles(struct clocksource *cs)
{
return IMX_TCN(TIMER_BASE);
}

2
arch/arm/mach-ixp4xx/common.c
View File

@ -401,7 +401,7 @@ void __init ixp4xx_sys_init(void)
/*
* clocksource
*/
cycle_t ixp4xx_get_cycles(void)
cycle_t ixp4xx_get_cycles(struct clocksource *cs)
{
return *IXP4XX_OSTS;
}

1
arch/arm/mach-kirkwood/common.c
View File

@ -23,6 +23,7 @@
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/kirkwood.h>
#include <mach/bridge-regs.h>
#include <plat/cache-feroceon-l2.h>
#include <plat/ehci-orion.h>
#include <plat/mvsdio.h>

42
arch/arm/mach-kirkwood/include/mach/bridge-regs.h Normal file
View File

@ -0,0 +1,42 @@
/*
* arch/arm/mach-kirkwood/include/mach/bridge-regs.h
*
* Mbus-L to Mbus Bridge Registers
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_BRIDGE_REGS_H
#define __ASM_ARCH_BRIDGE_REGS_H
#include <mach/kirkwood.h>
#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
#define CPU_RESET 0x00000002
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_CAUSE_LOW_OFF 0x0000
#define IRQ_MASK_LOW_OFF 0x0004
#define IRQ_CAUSE_HIGH_OFF 0x0010
#define IRQ_MASK_HIGH_OFF 0x0014
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
#define L2_WRITETHROUGH 0x00000010
#endif

2
arch/arm/mach-kirkwood/include/mach/debug-macro.S
View File

@ -6,7 +6,7 @@
* published by the Free Software Foundation.
*/
#include <mach/kirkwood.h>
#include <mach/bridge-regs.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0

2
arch/arm/mach-kirkwood/include/mach/entry-macro.S
View File

@ -8,7 +8,7 @@
* warranty of any kind, whether express or implied.
*/
#include <mach/kirkwood.h>
#include <mach/bridge-regs.h>
.macro disable_fiq
.endm

53
arch/arm/mach-kirkwood/include/mach/kirkwood.h
View File

@ -43,44 +43,6 @@
#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
/*
* MBUS bridge registers.
*/
#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
#define CPU_RESET 0x00000002
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_CAUSE_LOW_OFF 0x0000
#define IRQ_MASK_LOW_OFF 0x0004
#define IRQ_CAUSE_HIGH_OFF 0x0010
#define IRQ_MASK_HIGH_OFF 0x0014
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
#define L2_WRITETHROUGH 0x00000010
/*
* Supported devices and revisions.
*/
#define MV88F6281_DEV_ID 0x6281
#define MV88F6281_REV_Z0 0
#define MV88F6281_REV_A0 2
#define MV88F6192_DEV_ID 0x6192
#define MV88F6192_REV_Z0 0
#define MV88F6192_REV_A0 2
#define MV88F6180_DEV_ID 0x6180
#define MV88F6180_REV_A0 2
/*
* Register Map
*/
@ -99,6 +61,8 @@
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
@ -119,5 +83,18 @@
#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
/*
* Supported devices and revisions.
*/
#define MV88F6281_DEV_ID 0x6281
#define MV88F6281_REV_Z0 0
#define MV88F6281_REV_A0 2
#define MV88F6192_DEV_ID 0x6192
#define MV88F6192_REV_Z0 0
#define MV88F6192_REV_A0 2
#define MV88F6180_DEV_ID 0x6180
#define MV88F6180_REV_A0 2
#endif

3
arch/arm/mach-kirkwood/include/mach/system.h
View File

@ -9,8 +9,7 @@
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <mach/hardware.h>
#include <mach/kirkwood.h>
#include <mach/bridge-regs.h>
static inline void arch_idle(void)
{

1
arch/arm/mach-kirkwood/irq.c
View File

@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/bridge-regs.h>
#include <plat/irq.h>
#include <asm/gpio.h>
#include "common.h"

1
arch/arm/mach-loki/addr-map.c
View File

@ -38,6 +38,7 @@
/*
* CPU Address Decode Windows registers
*/
#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
#define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 | ((n) << 4))
#define CPU_WIN_BASE(n) BRIDGE_REG(0x004 | ((n) << 4))
#define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 | ((n) << 4))

33
arch/arm/mach-loki/include/mach/bridge-regs.h Normal file
View File

@ -0,0 +1,33 @@
/*
* arch/arm/mach-loki/include/mach/bridge-regs.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_BRIDGE_REGS_H
#define __ASM_ARCH_BRIDGE_REGS_H
#include <mach/loki.h>
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR 0x0004
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_CAUSE_OFF 0x0000
#define IRQ_MASK_OFF 0x0004
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#endif

2
arch/arm/mach-loki/include/mach/entry-macro.S
View File

@ -8,7 +8,7 @@
* warranty of any kind, whether express or implied.
*/
#include <mach/loki.h>
#include <mach/bridge-regs.h>
.macro disable_fiq
.endm

14
arch/arm/mach-loki/include/mach/loki.h
View File

@ -58,20 +58,6 @@
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR 0x0004
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_CAUSE_OFF 0x0000
#define IRQ_MASK_OFF 0x0004
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)

3
arch/arm/mach-loki/include/mach/system.h
View File

@ -9,8 +9,7 @@
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <mach/hardware.h>
#include <mach/loki.h>
#include <mach/bridge-regs.h>
static inline void arch_idle(void)
{

1
arch/arm/mach-loki/irq.c
View File

@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/bridge-regs.h>
#include <plat/irq.h>
#include "common.h"

4
arch/arm/mach-msm/timer.c
View File

@ -57,12 +57,12 @@ static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
static cycle_t msm_gpt_read(void)
static cycle_t msm_gpt_read(struct clocksource *cs)
{
return readl(MSM_GPT_BASE + TIMER_COUNT_VAL);
}
static cycle_t msm_dgt_read(void)
static cycle_t msm_dgt_read(struct clocksource *cs)
{
return readl(MSM_DGT_BASE + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT;
}

1
arch/arm/mach-mv78xx0/common.c
View File

@ -20,6 +20,7 @@
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/mv78xx0.h>
#include <mach/bridge-regs.h>
#include <plat/cache-feroceon-l2.h>
#include <plat/ehci-orion.h>
#include <plat/orion_nand.h>

39
arch/arm/mach-mv78xx0/include/mach/bridge-regs.h Normal file
View File

@ -0,0 +1,39 @@
/*
* arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_BRIDGE_REGS_H
#define __ASM_ARCH_BRIDGE_REGS_H
#include <mach/mv78xx0.h>
#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
#define L2_WRITETHROUGH 0x00020000
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_CAUSE_ERR_OFF 0x0000
#define IRQ_CAUSE_LOW_OFF 0x0004
#define IRQ_CAUSE_HIGH_OFF 0x0008
#define IRQ_MASK_ERR_OFF 0x000c
#define IRQ_MASK_LOW_OFF 0x0010
#define IRQ_MASK_HIGH_OFF 0x0014
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
#endif

2
arch/arm/mach-mv78xx0/include/mach/entry-macro.S
View File

@ -8,7 +8,7 @@
* warranty of any kind, whether express or implied.
*/
#include <mach/mv78xx0.h>
#include <mach/bridge-regs.h>
.macro disable_fiq
.endm

42
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
View File

@ -59,37 +59,6 @@
* Core-specific peripheral registers.
*/
#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
#define L2_WRITETHROUGH 0x00020000
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
#define SOFT_RESET_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
#define SOFT_RESET 0x00000001
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
#define IRQ_CAUSE_ERR_OFF 0x0000
#define IRQ_CAUSE_LOW_OFF 0x0004
#define IRQ_CAUSE_HIGH_OFF 0x0008
#define IRQ_MASK_ERR_OFF 0x000c
#define IRQ_MASK_LOW_OFF 0x0010
#define IRQ_MASK_HIGH_OFF 0x0014
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
/*
* Supported devices and revisions.
*/
#define MV78X00_Z0_DEV_ID 0x6381
#define MV78X00_REV_Z0 1
#define MV78100_DEV_ID 0x7810
#define MV78100_REV_A0 1
#define MV78200_DEV_ID 0x7820
#define MV78200_REV_A0 1
/*
* Register Map
@ -135,5 +104,16 @@
#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000)
/*
* Supported devices and revisions.
*/
#define MV78X00_Z0_DEV_ID 0x6381
#define MV78X00_REV_Z0 1
#define MV78100_DEV_ID 0x7810
#define MV78100_REV_A0 1
#define MV78200_DEV_ID 0x7820
#define MV78200_REV_A0 1
#endif

3
arch/arm/mach-mv78xx0/include/mach/system.h
View File

@ -9,8 +9,7 @@
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <mach/hardware.h>
#include <mach/mv78xx0.h>
#include <mach/bridge-regs.h>
static inline void arch_idle(void)
{

2
arch/arm/mach-mv78xx0/irq.c
View File

@ -13,7 +13,7 @@
#include <linux/pci.h>
#include <linux/irq.h>
#include <asm/gpio.h>
#include <mach/mv78xx0.h>
#include <mach/bridge-regs.h>
#include <plat/irq.h>
#include "common.h"

2
arch/arm/mach-netx/time.c
View File

@ -104,7 +104,7 @@ static struct irqaction netx_timer_irq = {
.handler = netx_timer_interrupt,
};
cycle_t netx_get_cycles(void)
cycle_t netx_get_cycles(struct clocksource *cs)
{
return readl(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE));
}

2
arch/arm/mach-ns9xxx/time-ns9360.c
View File

@ -25,7 +25,7 @@
#define TIMER_CLOCKEVENT 1
static u32 latch;
static cycle_t ns9360_clocksource_read(void)
static cycle_t ns9360_clocksource_read(struct clocksource *cs)
{
return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE));
}

2
arch/arm/mach-omap1/time.c
View File

@ -198,7 +198,7 @@ static struct irqaction omap_mpu_timer2_irq = {
.handler = omap_mpu_timer2_interrupt,
};
static cycle_t mpu_read(void)
static cycle_t mpu_read(struct clocksource *cs)
{
return ~omap_mpu_timer_read(1);
}

2
arch/arm/mach-omap2/timer-gp.c
View File

@ -138,7 +138,7 @@ static inline void __init omap2_gp_clocksource_init(void) {}
* clocksource
*/
static struct omap_dm_timer *gpt_clocksource;
static cycle_t clocksource_read_cycles(void)
static cycle_t clocksource_read_cycles(struct clocksource *cs)
{
return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
}

2
arch/arm/mach-orion5x/addr-map.c
View File

@ -57,12 +57,14 @@
/*
* Helpers to get DDR bank info
*/
#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x))
#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3))
#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3))
/*
* CPU Address Decode Windows registers
*/
#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x))
#define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
#define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))

41
arch/arm/mach-orion5x/include/mach/bridge-regs.h Normal file
View File

@ -0,0 +1,41 @@
/*
* arch/arm/mach-orion5x/include/mach/bridge-regs.h
*
* Orion CPU Bridge Registers
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ASM_ARCH_BRIDGE_REGS_H
#define __ASM_ARCH_BRIDGE_REGS_H
#include <mach/orion5x.h>
#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100)
#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104)
#define CPU_RESET_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108)
#define WDT_RESET 0x0002
#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
#define WDT_INT_REQ 0x0008
#define BRIDGE_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200)
#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204)
#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
#endif

2
arch/arm/mach-orion5x/include/mach/entry-macro.S
View File

@ -8,7 +8,7 @@
* warranty of any kind, whether express or implied.
*/
#include <mach/orion5x.h>
#include <mach/bridge-regs.h>
.macro disable_fiq
.endm

134
arch/arm/mach-orion5x/include/mach/orion5x.h
View File

@ -60,6 +60,59 @@
#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000
#define ORION5X_PCI_MEM_SIZE SZ_128M
/*******************************************************************************
* Orion Registers Map
******************************************************************************/
#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000)
#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000)
#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000)
#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000)
#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000)
#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900)
#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900)
#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000)
#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000)
#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000)
#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000)
#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000)
#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000)
/*******************************************************************************
* Device Bus Registers
******************************************************************************/
#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000)
#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004)
#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c)
#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
/*******************************************************************************
* Supported Devices & Revisions
******************************************************************************/
@ -80,85 +133,4 @@
#define MV88F6183_DEV_ID 0x6183
#define MV88F6183_REV_B0 3
/*******************************************************************************
* Orion Registers Map
******************************************************************************/
#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000)
#define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x))
#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000)
#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000)
#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x))
#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000)
#define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x))
#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)
#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000)
#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x))
#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000)
#define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x))
#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000)
#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000)
#define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x))
#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900)
#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900)
#define ORION5X_XOR_REG(x) (ORION5X_XOR_VIRT_BASE | (x))
#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000)
#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000)
#define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x))
#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000)
#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000)
#define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x))
#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000)
#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000)
#define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x))
/*******************************************************************************
* Device Bus Registers
******************************************************************************/
#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000)
#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004)
#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050)
#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008)
#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010)
#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c)
#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460)
#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464)
#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c)
#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0)
#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0)
#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4)
/***************************************************************************
* Orion CPU Bridge Registers
**************************************************************************/
#define CPU_CONF ORION5X_BRIDGE_REG(0x100)
#define CPU_CTRL ORION5X_BRIDGE_REG(0x104)
#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108)
#define WDT_RESET 0x0002
#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c)
#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C)
#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110)
#define WDT_INT_REQ 0x0008
#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
#define BRIDGE_INT_TIMER0 0x0002
#define BRIDGE_INT_TIMER1 0x0004
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200)
#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204)
#endif

3
arch/arm/mach-orion5x/include/mach/system.h
View File

@ -11,8 +11,7 @@
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <mach/hardware.h>
#include <mach/orion5x.h>
#include <mach/bridge-regs.h>
static inline void arch_idle(void)
{

2
arch/arm/mach-orion5x/irq.c
View File

@ -15,7 +15,7 @@
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/gpio.h>
#include <mach/orion5x.h>
#include <mach/bridge-regs.h>
#include <plat/irq.h>
#include "common.h"

1
arch/arm/mach-orion5x/mss2-setup.c
View File

@ -26,6 +26,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include <mach/orion5x.h>
#include <mach/bridge-regs.h>
#include "common.h"
#include "mpp.h"

1
arch/arm/mach-orion5x/pci.c
View File

@ -196,6 +196,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
/*****************************************************************************
* PCI controller
****************************************************************************/
#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x))
#define PCI_MODE ORION5X_PCI_REG(0xd00)
#define PCI_CMD ORION5X_PCI_REG(0xc00)
#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)

10
arch/arm/mach-pxa/include/mach/audio.h
View File

@ -4,12 +4,22 @@
#include <sound/core.h>
#include <sound/pcm.h>
/*
* @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95)
* a -1 value means no gpio will be used for reset
* reset_gpio should only be specified for pxa27x CPUs where a silicon
* bug prevents correct operation of the reset line. If not specified,
* the default behaviour on these CPUs is to consider gpio 113 as the
* AC97 reset line, which is the default on most boards.
*/
typedef struct {
int (*startup)(struct snd_pcm_substream *, void *);
void (*shutdown)(struct snd_pcm_substream *, void *);
void (*suspend)(void *);
void (*resume)(void *);
void *priv;
int reset_gpio;
} pxa2xx_audio_ops_t;
extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);

7
arch/arm/mach-pxa/include/mach/palmasoc.h
View File

@ -1,13 +1,8 @@
#ifndef _INCLUDE_PALMASOC_H_
#define _INCLUDE_PALMASOC_H_
struct palm27x_asoc_info {
int jack_gpio;
};
#ifdef CONFIG_SND_PXA2XX_SOC_PALM27X
void __init palm27x_asoc_set_pdata(struct palm27x_asoc_info *data);
#else
static inline void palm27x_asoc_set_pdata(struct palm27x_asoc_info *data) {}
#endif
#endif

6
arch/arm/mach-pxa/mioa701.c
View File

@ -742,6 +742,10 @@ struct i2c_pxa_platform_data i2c_pdata = {
.fast_mode = 1,
};
static pxa2xx_audio_ops_t mioa701_ac97_info = {
.reset_gpio = 95,
};
/*
* Mio global
*/
@ -815,7 +819,7 @@ static void __init mioa701_machine_init(void)
pxa_set_keypad_info(&mioa701_keypad_info);
wm97xx_bat_set_pdata(&mioa701_battery_data);
pxa_set_udc_info(&mioa701_udc_info);
pxa_set_ac97_info(NULL);
pxa_set_ac97_info(&mioa701_ac97_info);
pm_power_off = mioa701_poweroff;
arm_pm_restart = mioa701_restart;
platform_add_devices(devices, ARRAY_SIZE(devices));

18
arch/arm/mach-pxa/palmld.c
View File

@ -477,10 +477,22 @@ static struct wm97xx_batt_info wm97xx_batt_pdata = {
/******************************************************************************
* aSoC audio
******************************************************************************/
static struct palm27x_asoc_info palm27x_asoc_pdata = {
static struct palm27x_asoc_info palmld_asoc_pdata = {
.jack_gpio = GPIO_NR_PALMLD_EARPHONE_DETECT,
};
static pxa2xx_audio_ops_t palmld_ac97_pdata = {
.reset_gpio = 95,
};
static struct platform_device palmld_asoc = {
.name = "palm27x-asoc",
.id = -1,
.dev = {
.platform_data = &palmld_asoc_pdata,
},
};
/******************************************************************************
* Framebuffer
******************************************************************************/
@ -544,6 +556,7 @@ static struct platform_device *devices[] __initdata = {
&palmld_backlight,
&palmld_leds,
&power_supply,
&palmld_asoc,
};
static struct map_desc palmld_io_desc[] __initdata = {
@ -573,11 +586,10 @@ static void __init palmld_init(void)
set_pxa_fb_info(&palmld_lcd_screen);
pxa_set_mci_info(&palmld_mci_platform_data);
pxa_set_ac97_info(NULL);
pxa_set_ac97_info(&palmld_ac97_pdata);
pxa_set_ficp_info(&palmld_ficp_platform_data);
pxa_set_keypad_info(&palmld_keypad_platform_data);
wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
palm27x_asoc_set_pdata(&palm27x_asoc_pdata);
platform_add_devices(devices, ARRAY_SIZE(devices));
}

18
arch/arm/mach-pxa/palmt5.c
View File

@ -420,10 +420,22 @@ static struct wm97xx_batt_info wm97xx_batt_pdata = {
/******************************************************************************
* aSoC audio
******************************************************************************/
static struct palm27x_asoc_info palm27x_asoc_pdata = {
static struct palm27x_asoc_info palmt5_asoc_pdata = {
.jack_gpio = GPIO_NR_PALMT5_EARPHONE_DETECT,
};
static pxa2xx_audio_ops_t palmt5_ac97_pdata = {
.reset_gpio = 95,
};
static struct platform_device palmt5_asoc = {
.name = "palm27x-asoc",
.id = -1,
.dev = {
.platform_data = &palmt5_asoc_pdata,
},
};
/******************************************************************************
* Framebuffer
******************************************************************************/
@ -486,6 +498,7 @@ static struct platform_device *devices[] __initdata = {
#endif
&palmt5_backlight,
&power_supply,
&palmt5_asoc,
};
/* setup udc GPIOs initial state */
@ -504,12 +517,11 @@ static void __init palmt5_init(void)
set_pxa_fb_info(&palmt5_lcd_screen);
pxa_set_mci_info(&palmt5_mci_platform_data);
palmt5_udc_init();
pxa_set_ac97_info(&palmt5_ac97_pdata);
pxa_set_udc_info(&palmt5_udc_info);
pxa_set_ac97_info(NULL);
pxa_set_ficp_info(&palmt5_ficp_platform_data);
pxa_set_keypad_info(&palmt5_keypad_platform_data);
wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
palm27x_asoc_set_pdata(&palm27x_asoc_pdata);
platform_add_devices(devices, ARRAY_SIZE(devices));
}

23
arch/arm/mach-pxa/palmtx.c
View File

@ -40,6 +40,7 @@
#include <mach/irda.h>
#include <mach/pxa27x_keypad.h>
#include <mach/udc.h>
#include <mach/palmasoc.h>
#include "generic.h"
#include "devices.h"
@ -433,6 +434,25 @@ static struct wm97xx_batt_info wm97xx_batt_pdata = {
.batt_name = "main-batt",
};
/******************************************************************************
* aSoC audio
******************************************************************************/
static struct palm27x_asoc_info palmtx_asoc_pdata = {
.jack_gpio = GPIO_NR_PALMTX_EARPHONE_DETECT,
};
static pxa2xx_audio_ops_t palmtx_ac97_pdata = {
.reset_gpio = 95,
};
static struct platform_device palmtx_asoc = {
.name = "palm27x-asoc",
.id = -1,
.dev = {
.platform_data = &palmtx_asoc_pdata,
},
};
/******************************************************************************
* Framebuffer
******************************************************************************/
@ -495,6 +515,7 @@ static struct platform_device *devices[] __initdata = {
#endif
&palmtx_backlight,
&power_supply,
&palmtx_asoc,
};
static struct map_desc palmtx_io_desc[] __initdata = {
@ -529,8 +550,8 @@ static void __init palmtx_init(void)
set_pxa_fb_info(&palmtx_lcd_screen);
pxa_set_mci_info(&palmtx_mci_platform_data);
palmtx_udc_init();
pxa_set_ac97_info(&palmtx_ac97_pdata);
pxa_set_udc_info(&palmtx_udc_info);
pxa_set_ac97_info(NULL);
pxa_set_ficp_info(&palmtx_ficp_platform_data);
pxa_set_keypad_info(&palmtx_keypad_platform_data);
wm97xx_bat_set_pdata(&wm97xx_batt_pdata);

6
arch/arm/mach-pxa/pcm990-baseboard.c
View File

@ -377,7 +377,7 @@ struct pxacamera_platform_data pcm990_pxacamera_platform_data = {
#include <linux/i2c/pca953x.h>
static struct pca953x_platform_data pca9536_data = {
.gpio_base = NR_BUILTIN_GPIO + 1,
.gpio_base = NR_BUILTIN_GPIO,
};
static int gpio_bus_switch;
@ -405,9 +405,9 @@ static unsigned long pcm990_camera_query_bus_param(struct soc_camera_link *link)
int ret;
if (!gpio_bus_switch) {
ret = gpio_request(NR_BUILTIN_GPIO + 1, "camera");
ret = gpio_request(NR_BUILTIN_GPIO, "camera");
if (!ret) {
gpio_bus_switch = NR_BUILTIN_GPIO + 1;
gpio_bus_switch = NR_BUILTIN_GPIO;
gpio_direction_output(gpio_bus_switch, 0);
} else
gpio_bus_switch = -EINVAL;

2
arch/arm/mach-pxa/time.c
View File

@ -125,7 +125,7 @@ static struct clock_event_device ckevt_pxa_osmr0 = {
.set_mode = pxa_osmr0_set_mode,
};
static cycle_t pxa_read_oscr(void)
static cycle_t pxa_read_oscr(struct clocksource *cs)
{
return OSCR;
}

2
arch/arm/mach-realview/core.c
View File

@ -715,7 +715,7 @@ static struct irqaction realview_timer_irq = {
.handler = realview_timer_interrupt,
};
static cycle_t realview_get_cycles(void)
static cycle_t realview_get_cycles(struct clocksource *cs)
{
return ~readl(timer3_va_base + TIMER_VALUE);
}

2
arch/arm/mach-versatile/core.c
View File

@ -948,7 +948,7 @@ static struct irqaction versatile_timer_irq = {
.handler = versatile_timer_interrupt,
};
static cycle_t versatile_get_cycles(void)
static cycle_t versatile_get_cycles(struct clocksource *cs)
{
return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
}

3
arch/arm/mm/proc-v6.S
View File

@ -10,6 +10,7 @@
*
* This is the "shell" of the ARMv6 processor support.
*/
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
@ -132,7 +133,7 @@ cpu_v6_name:
.asciz "ARMv6-compatible processor"
.align
.section ".text.init", #alloc, #execinstr
__INIT
/*
* __v6_setup

3
arch/arm/mm/proc-v7.S
View File

@ -9,6 +9,7 @@
*
* This is the "shell" of the ARMv7 processor support.
*/
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
@ -153,7 +154,7 @@ cpu_v7_name:
.ascii "ARMv7 Processor"
.align
.section ".text.init", #alloc, #execinstr
__INIT
/*
* __v7_setup

3
arch/arm/mm/tlb-v6.S
View File

@ -10,6 +10,7 @@
* ARM architecture version 6 TLB handling functions.
* These assume a split I/D TLB.
*/
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/asm-offsets.h>
#include <asm/page.h>
@ -87,7 +88,7 @@ ENTRY(v6wbi_flush_kern_tlb_range)
mcr p15, 0, r2, c7, c5, 4 @ prefetch flush
mov pc, lr
.section ".text.init", #alloc, #execinstr
__INIT
.type v6wbi_tlb_fns, #object
ENTRY(v6wbi_tlb_fns)

3
arch/arm/mm/tlb-v7.S
View File

@ -11,6 +11,7 @@
* ARM architecture version 6 TLB handling functions.
* These assume a split I/D TLB.
*/
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/asm-offsets.h>
#include <asm/page.h>
@ -80,7 +81,7 @@ ENTRY(v7wbi_flush_kern_tlb_range)
mov pc, lr
ENDPROC(v7wbi_flush_kern_tlb_range)
.section ".text.init", #alloc, #execinstr
__INIT
.type v7wbi_tlb_fns, #object
ENTRY(v7wbi_tlb_fns)

2
arch/arm/plat-mxc/time.c
View File

@ -36,7 +36,7 @@ static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
/* clock source */
static cycle_t mxc_get_cycles(void)
static cycle_t mxc_get_cycles(struct clocksource *cs)
{
return __raw_readl(TIMER_BASE + MXC_TCN);
}

4
arch/arm/plat-omap/common.c
View File

@ -185,7 +185,7 @@ console_initcall(omap_add_serial_console);
#include <linux/clocksource.h>
static cycle_t omap_32k_read(void)
static cycle_t omap_32k_read(struct clocksource *cs)
{
return omap_readl(TIMER_32K_SYNCHRONIZED);
}
@ -207,7 +207,7 @@ unsigned long long sched_clock(void)
{
unsigned long long ret;
ret = (unsigned long long)omap_32k_read();
ret = (unsigned long long)omap_32k_read(&clocksource_32k);
ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift;
return ret;
}

4
arch/arm/plat-orion/time.c
View File

@ -16,7 +16,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/bridge-regs.h>
/*
* Number of timer ticks per jiffy.
@ -41,7 +41,7 @@ static u32 ticks_per_jiffy;
/*
* Clocksource handling.
*/
static cycle_t orion_clksrc_read(void)
static cycle_t orion_clksrc_read(struct clocksource *cs)
{
return 0xffffffff - readl(TIMER0_VAL);
}

2
arch/avr32/kernel/time.c
View File

@ -18,7 +18,7 @@
#include <mach/pm.h>
static cycle_t read_cycle_count(void)
static cycle_t read_cycle_count(struct clocksource *cs)
{
return (cycle_t)sysreg_read(COUNT);
}

12
arch/blackfin/kernel/time-ts.c
View File

@ -58,16 +58,11 @@ static inline unsigned long long cycles_2_ns(cycle_t cyc)
return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
}
static cycle_t read_cycles(void)
static cycle_t read_cycles(struct clocksource *cs)
{
return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
}
unsigned long long sched_clock(void)
{
return cycles_2_ns(read_cycles());
}
static struct clocksource clocksource_bfin = {
.name = "bfin_cycles",
.rating = 350,
@ -77,6 +72,11 @@ static struct clocksource clocksource_bfin = {
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
unsigned long long sched_clock(void)
{
return cycles_2_ns(read_cycles(&clocksource_bfin));
}
static int __init bfin_clocksource_init(void)
{
set_cyc2ns_scale(get_cclk() / 1000);

5
arch/frv/include/asm/bug.h
View File

@ -30,7 +30,7 @@ extern void __debug_bug_printk(const char *file, unsigned line);
do { \
__debug_bug_trap(signr); \
asm volatile("nop"); \
} while(0)
} while(1)
#define HAVE_ARCH_BUG
#define BUG() \
@ -46,7 +46,8 @@ do { \
#define HAVE_ARCH_KGDB_BAD_PAGE
#define kgdb_bad_page(page) do { kgdb_raise(SIGABRT); } while(0)
#endif
#endif
#endif /* CONFIG_BUG */
#include <asm-generic/bug.h>

12
arch/frv/include/asm/init.h
View File

@ -1,12 +0,0 @@
#ifndef _ASM_INIT_H
#define _ASM_INIT_H
#define __init __attribute__ ((__section__ (".text.init")))
#define __initdata __attribute__ ((__section__ (".data.init")))
/* For assembly routines */
#define __INIT .section ".text.init",#alloc,#execinstr
#define __FINIT .previous
#define __INITDATA .section ".data.init",#alloc,#write
#endif

4
arch/frv/include/asm/unistd.h
View File

@ -339,10 +339,12 @@
#define __NR_dup3 330
#define __NR_pipe2 331
#define __NR_inotify_init1 332
#define __NR_preadv 333
#define __NR_pwritev 334
#ifdef __KERNEL__
#define NR_syscalls 333
#define NR_syscalls 335
#define __ARCH_WANT_IPC_PARSE_VERSION
/* #define __ARCH_WANT_OLD_READDIR */

2
arch/frv/kernel/entry.S
View File

@ -1525,5 +1525,7 @@ sys_call_table:
.long sys_dup3 /* 330 */
.long sys_pipe2
.long sys_inotify_init1
.long sys_preadv
.long sys_pwritev
syscall_table_size = (. - sys_call_table)

3
arch/frv/kernel/head-mmu-fr451.S
View File

@ -9,6 +9,7 @@
* 2 of the License, or (at your option) any later version.
*/
#include <linux/init.h>
#include <linux/threads.h>
#include <linux/linkage.h>
#include <asm/ptrace.h>
@ -31,7 +32,7 @@
#define __400_LCR 0xfe000100
#define __400_LSBR 0xfe000c00
.section .text.init,"ax"
__INIT
.balign 4
###############################################################################

3
arch/frv/kernel/head-uc-fr401.S
View File

@ -9,6 +9,7 @@
* 2 of the License, or (at your option) any later version.
*/
#include <linux/init.h>
#include <linux/threads.h>
#include <linux/linkage.h>
#include <asm/ptrace.h>
@ -30,7 +31,7 @@
#define __400_LCR 0xfe000100
#define __400_LSBR 0xfe000c00
.section .text.init,"ax"
__INIT
.balign 4
###############################################################################

3
arch/frv/kernel/head-uc-fr451.S
View File

@ -9,6 +9,7 @@
* 2 of the License, or (at your option) any later version.
*/
#include <linux/init.h>
#include <linux/threads.h>
#include <linux/linkage.h>
#include <asm/ptrace.h>
@ -30,7 +31,7 @@
#define __400_LCR 0xfe000100
#define __400_LSBR 0xfe000c00
.section .text.init,"ax"
__INIT
.balign 4
###############################################################################

3
arch/frv/kernel/head-uc-fr555.S
View File

@ -9,6 +9,7 @@
* 2 of the License, or (at your option) any later version.
*/
#include <linux/init.h>
#include <linux/threads.h>
#include <linux/linkage.h>
#include <asm/ptrace.h>
@ -29,7 +30,7 @@
#define __551_LCR 0xfeff1100
#define __551_LSBR 0xfeff1c00
.section .text.init,"ax"
__INIT
.balign 4
###############################################################################

3
arch/frv/kernel/head.S
View File

@ -9,6 +9,7 @@
* 2 of the License, or (at your option) any later version.
*/
#include <linux/init.h>
#include <linux/threads.h>
#include <linux/linkage.h>
#include <asm/thread_info.h>
@ -27,7 +28,7 @@
# command line string
#
###############################################################################
.section .text.head,"ax"
__HEAD
.balign 4
.globl _boot, __head_reference

2
arch/frv/kernel/vmlinux.lds.S
View File

@ -26,7 +26,7 @@ SECTIONS
_sinittext = .;
.init.text : {
*(.text.head)
HEAD_TEXT
#ifndef CONFIG_DEBUG_INFO
INIT_TEXT
EXIT_TEXT

63
arch/frv/mb93090-mb00/pci-vdk.c
View File

@ -30,6 +30,29 @@ int __nongpreldata pcibios_last_bus = -1;
struct pci_bus *__nongpreldata pci_root_bus;
struct pci_ops *__nongpreldata pci_root_ops;
/*
* The accessible PCI window does not cover the entire CPU address space, but
* there are devices we want to access outside of that window, so we need to
* insert specific PCI bus resources instead of using the platform-level bus
* resources directly for the PCI root bus.
*
* These are configured and inserted by pcibios_init() and are attached to the
* root bus by pcibios_fixup_bus().
*/
static struct resource pci_ioport_resource = {
.name = "PCI IO",
.start = 0,
.end = IO_SPACE_LIMIT,
.flags = IORESOURCE_IO,
};
static struct resource pci_iomem_resource = {
.name = "PCI mem",
.start = 0,
.end = -1,
.flags = IORESOURCE_MEM,
};
/*
* Functions for accessing PCI configuration space
*/
@ -304,6 +327,12 @@ void __init pcibios_fixup_bus(struct pci_bus *bus)
#if 0
printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);
#endif
if (bus->number == 0) {
bus->resource[0] = &pci_ioport_resource;
bus->resource[1] = &pci_iomem_resource;
}
pci_read_bridge_bases(bus);
if (bus->number == 0) {
@ -350,28 +379,36 @@ int __init pcibios_init(void)
/* enable PCI arbitration */
__reg_MB86943_pci_arbiter = MB86943_PCIARB_EN;
ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
ioport_resource.end += ioport_resource.start;
pci_ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
pci_ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
pci_ioport_resource.end += pci_ioport_resource.start;
printk("PCI IO window: %08llx-%08llx\n",
(unsigned long long) ioport_resource.start,
(unsigned long long) ioport_resource.end);
(unsigned long long) pci_ioport_resource.start,
(unsigned long long) pci_ioport_resource.end);
iomem_resource.start = (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00;
pci_iomem_resource.start = (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00;
pci_iomem_resource.end = (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff;
pci_iomem_resource.end += pci_iomem_resource.start;
/* Reserve somewhere to write to flush posted writes. */
iomem_resource.start += 0x400;
iomem_resource.end = (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff;
iomem_resource.end += iomem_resource.start;
/* Reserve somewhere to write to flush posted writes. This is used by
* __flush_PCI_writes() from asm/io.h to force the write FIFO in the
* CPU-PCI bridge to flush as this doesn't happen automatically when a
* read is performed on the MB93090 development kit motherboard.
*/
pci_iomem_resource.start += 0x400;
printk("PCI MEM window: %08llx-%08llx\n",
(unsigned long long) iomem_resource.start,
(unsigned long long) iomem_resource.end);
(unsigned long long) pci_iomem_resource.start,
(unsigned long long) pci_iomem_resource.end);
printk("PCI DMA memory: %08lx-%08lx\n",
dma_coherent_mem_start, dma_coherent_mem_end);
if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
panic("Unable to insert PCI IOMEM resource\n");
if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
panic("Unable to insert PCI IOPORT resource\n");
if (!pci_probe)
return -ENXIO;

2
arch/ia64/include/asm/paravirt_privop.h
View File

@ -445,7 +445,6 @@ paravirt_set_rr0_to_rr4(unsigned long val0, unsigned long val1,
register unsigned long ia64_intri_res asm ("r8"); \
register unsigned long __reg asm ("r8") = (reg); \
\
BUILD_BUG_ON(!__builtin_constant_p(reg)); \
asm volatile (paravirt_alt_bundle(__PARAVIRT_BR, \
PARAVIRT_TYPE(GETREG) \
+ (reg)) \
@ -464,7 +463,6 @@ paravirt_set_rr0_to_rr4(unsigned long val0, unsigned long val1,
register unsigned long ia64_clobber1 asm ("r8"); \
register unsigned long ia64_clobber2 asm ("r9"); \
\
BUILD_BUG_ON(!__builtin_constant_p(reg)); \
asm volatile (paravirt_alt_bundle(__PARAVIRT_BR, \
PARAVIRT_TYPE(SETREG) \
+ (reg)) \

2
arch/ia64/include/asm/smp.h
View File

@ -58,7 +58,7 @@ extern struct smp_boot_data {
extern char no_int_routing __devinitdata;
extern cpumask_t cpu_core_map[NR_CPUS];
DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
DECLARE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map);
extern int smp_num_siblings;
extern void __iomem *ipi_base_addr;
extern unsigned char smp_int_redirect;

2
arch/ia64/kernel/cyclone.c
View File

@ -21,7 +21,7 @@ void __init cyclone_setup(void)
static void __iomem *cyclone_mc;
static cycle_t read_cyclone(void)
static cycle_t read_cyclone(struct clocksource *cs)
{
return (cycle_t)readq((void __iomem *)cyclone_mc);
}

14
arch/ia64/kernel/smp.c
View File

@ -225,6 +225,7 @@ smp_send_reschedule (int cpu)
{
platform_send_ipi(cpu, IA64_IPI_RESCHEDULE, IA64_IPI_DM_INT, 0);
}
EXPORT_SYMBOL_GPL(smp_send_reschedule);
/*
* Called with preemption disabled.
@ -300,15 +301,12 @@ smp_flush_tlb_mm (struct mm_struct *mm)
return;
}
smp_call_function_mask(mm->cpu_vm_mask,
(void (*)(void *))local_finish_flush_tlb_mm, mm, 1);
local_irq_disable();
local_finish_flush_tlb_mm(mm);
local_irq_enable();
preempt_enable();
/*
* We could optimize this further by using mm->cpu_vm_mask to track which CPUs
* have been running in the address space. It's not clear that this is worth the
* trouble though: to avoid races, we have to raise the IPI on the target CPU
* anyhow, and once a CPU is interrupted, the cost of local_flush_tlb_all() is
* rather trivial.
*/
on_each_cpu((void (*)(void *))local_finish_flush_tlb_mm, mm, 1);
}
void arch_send_call_function_single_ipi(int cpu)

4
arch/ia64/kernel/time.c
View File

@ -33,7 +33,7 @@
#include "fsyscall_gtod_data.h"
static cycle_t itc_get_cycles(void);
static cycle_t itc_get_cycles(struct clocksource *cs);
struct fsyscall_gtod_data_t fsyscall_gtod_data = {
.lock = SEQLOCK_UNLOCKED,
@ -383,7 +383,7 @@ ia64_init_itm (void)
}
}
static cycle_t itc_get_cycles(void)
static cycle_t itc_get_cycles(struct clocksource *cs)
{
u64 lcycle, now, ret;

14
arch/ia64/kvm/kvm-ia64.c
View File

@ -610,20 +610,22 @@ static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
int r;
again:
preempt_disable();
local_irq_disable();
if (signal_pending(current)) {
local_irq_enable();
preempt_enable();
r = -EINTR;
kvm_run->exit_reason = KVM_EXIT_INTR;
goto out;
}
/*
* down_read() may sleep and return with interrupts enabled
*/
down_read(&vcpu->kvm->slots_lock);
preempt_disable();
local_irq_disable();
vcpu->guest_mode = 1;
kvm_guest_enter();
down_read(&vcpu->kvm->slots_lock);
r = vti_vcpu_run(vcpu, kvm_run);
if (r < 0) {
local_irq_enable();

2
arch/ia64/sn/kernel/sn2/timer.c
View File

@ -23,7 +23,7 @@
extern unsigned long sn_rtc_cycles_per_second;
static cycle_t read_sn2(void)
static cycle_t read_sn2(struct clocksource *cs)
{
return (cycle_t)readq(RTC_COUNTER_ADDR);
}

2
arch/m32r/kernel/head.S
View File

@ -23,7 +23,7 @@ __INITDATA
/*
* References to members of the boot_cpu_data structure.
*/
.section .text.head, "ax"
__HEAD
.global start_kernel
.global __bss_start
.global _end

2
arch/m32r/kernel/vmlinux.lds.S
View File

@ -27,7 +27,7 @@ SECTIONS
_text = .; /* Text and read-only data */
.boot : { *(.boot) } = 0
.text : {
*(.text.head)
HEAD_TEXT
TEXT_TEXT
SCHED_TEXT
LOCK_TEXT

163
arch/m68k/configs/amiga_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28-rc7
# Tue Dec 2 20:27:42 2008
# Linux kernel version: 2.6.30-rc3
# Wed Apr 22 20:47:52 2009
#
CONFIG_M68K=y
CONFIG_MMU=y
@ -29,14 +29,24 @@ CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
#
# RCU Subsystem
#
CONFIG_CLASSIC_RCU=y
# CONFIG_TREE_RCU is not set
# CONFIG_PREEMPT_RCU is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_PREEMPT_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
CONFIG_RELAY=y
CONFIG_NAMESPACES=y
@ -44,23 +54,27 @@ CONFIG_NAMESPACES=y
# CONFIG_IPC_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_NET_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
# CONFIG_EMBEDDED is not set
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
@ -68,15 +82,16 @@ CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
@ -84,11 +99,8 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
CONFIG_BLK_DEV_BSG=y
# CONFIG_BLK_DEV_INTEGRITY is not set
@ -104,7 +116,6 @@ CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_CLASSIC_RCU=y
# CONFIG_FREEZER is not set
#
@ -140,12 +151,13 @@ CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_NEED_MULTIPLE_NODES=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_UNEVICTABLE_LRU=y
CONFIG_HAVE_MLOCK=y
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
#
# General setup
@ -157,7 +169,7 @@ CONFIG_BINFMT_AOUT=m
CONFIG_BINFMT_MISC=m
CONFIG_ZORRO=y
CONFIG_AMIGA_PCMCIA=y
# CONFIG_HEARTBEAT is not set
CONFIG_HEARTBEAT=y
CONFIG_PROC_HARDWARE=y
CONFIG_ISA=y
CONFIG_GENERIC_ISA_DMA=y
@ -184,7 +196,10 @@ CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
# CONFIG_IP_PNP is not set
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE=m
# CONFIG_ARPD is not set
@ -258,6 +273,7 @@ CONFIG_NETFILTER_XTABLES=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
CONFIG_NETFILTER_XT_TARGET_DSCP=m
CONFIG_NETFILTER_XT_TARGET_HL=m
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
@ -266,6 +282,7 @@ CONFIG_NETFILTER_XT_TARGET_RATEEST=m
CONFIG_NETFILTER_XT_TARGET_TRACE=m
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
@ -276,6 +293,7 @@ CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
@ -354,25 +372,20 @@ CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_TARGET_LOG=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_RAW=m
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m
CONFIG_IP_DCCP_ACKVEC=y
#
# DCCP CCIDs Configuration (EXPERIMENTAL)
#
CONFIG_IP_DCCP_CCID2=m
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=m
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_CCID3_RTO=100
CONFIG_IP_DCCP_TFRC_LIB=m
# CONFIG_IP_DCCP_CCID3 is not set
CONFIG_IP_SCTP=m
# CONFIG_SCTP_DBG_MSG is not set
# CONFIG_SCTP_DBG_OBJCNT is not set
@ -394,8 +407,10 @@ CONFIG_ATALK=m
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_PHONET is not set
# CONFIG_NET_SCHED is not set
CONFIG_NET_CLS_ROUTE=y
# CONFIG_DCB is not set
#
# Network testing
@ -406,8 +421,8 @@ CONFIG_NET_CLS_ROUTE=y
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_PHONET is not set
# CONFIG_WIRELESS is not set
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
@ -453,15 +468,20 @@ CONFIG_CDROM_PKTCDVD_BUFFERS=8
CONFIG_ATA_OVER_ETH=m
# CONFIG_BLK_DEV_HD is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_C2PORT is not set
#
# EEPROM support
#
# CONFIG_EEPROM_93CX6 is not set
CONFIG_HAVE_IDE=y
CONFIG_IDE=y
#
# Please see Documentation/ide/ide.txt for help/info on IDE drives
#
CONFIG_IDE_ATAPI=y
# CONFIG_BLK_DEV_IDE_SATA is not set
CONFIG_IDE_GD=y
CONFIG_IDE_GD_ATA=y
@ -469,7 +489,6 @@ CONFIG_IDE_GD_ATA=y
CONFIG_BLK_DEV_IDECD=y
CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
# CONFIG_BLK_DEV_IDETAPE is not set
# CONFIG_BLK_DEV_IDESCSI is not set
# CONFIG_IDE_TASK_IOCTL is not set
CONFIG_IDE_PROC_FS=y
@ -478,7 +497,6 @@ CONFIG_IDE_PROC_FS=y
#
# CONFIG_BLK_DEV_PLATFORM is not set
CONFIG_BLK_DEV_GAYLE=y
CONFIG_BLK_DEV_IDEDOUBLER=y
CONFIG_BLK_DEV_BUDDHA=y
# CONFIG_BLK_DEV_IDEDMA is not set
@ -530,6 +548,8 @@ CONFIG_ISCSI_TCP=m
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_LIBFC is not set
# CONFIG_LIBFCOE is not set
# CONFIG_SCSI_DTC3280 is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GENERIC_NCR5380 is not set
@ -547,6 +567,7 @@ CONFIG_GVP11_SCSI=y
CONFIG_SCSI_A4000T=y
CONFIG_SCSI_ZORRO7XX=y
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
@ -554,7 +575,7 @@ CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
# CONFIG_MD_RAID10 is not set
CONFIG_MD_RAID456=m
CONFIG_MD_RAID5_RESHAPE=y
CONFIG_MD_RAID6_PQ=m
# CONFIG_MD_MULTIPATH is not set
# CONFIG_MD_FAULTY is not set
CONFIG_BLK_DEV_DM=m
@ -567,6 +588,7 @@ CONFIG_DM_MULTIPATH=m
# CONFIG_DM_DELAY is not set
CONFIG_DM_UEVENT=y
CONFIG_NETDEVICES=y
CONFIG_COMPAT_NET_DEV_OPS=y
CONFIG_DUMMY=m
# CONFIG_BONDING is not set
CONFIG_MACVLAN=m
@ -577,14 +599,16 @@ CONFIG_VETH=m
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
# CONFIG_MII is not set
CONFIG_ARIADNE=m
CONFIG_A2065=m
CONFIG_HYDRA=m
CONFIG_ZORRO8390=m
CONFIG_APNE=m
CONFIG_ARIADNE=y
CONFIG_A2065=y
CONFIG_HYDRA=y
CONFIG_ZORRO8390=y
CONFIG_APNE=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_DNET is not set
# CONFIG_AT1700 is not set
# CONFIG_DEPCA is not set
# CONFIG_HP100 is not set
@ -609,7 +633,10 @@ CONFIG_APNE=m
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_IWLWIFI_LEDS is not set
#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
# CONFIG_PLIP is not set
CONFIG_PPP=m
@ -719,7 +746,7 @@ CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
# CONFIG_DEVKMEM is not set
# CONFIG_SERIAL_NONSTANDARD is not set
CONFIG_A2232=m
CONFIG_A2232=y
#
# Serial drivers
@ -730,6 +757,7 @@ CONFIG_A2232=m
# Non-8250 serial port support
#
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
CONFIG_PRINTER=m
@ -821,6 +849,7 @@ CONFIG_FB_FM2=y
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_BROADSHEET is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
@ -856,7 +885,6 @@ CONFIG_HIDRAW=y
#
# Special HID drivers
#
CONFIG_HID_COMPAT=y
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
@ -867,14 +895,13 @@ CONFIG_HID_COMPAT=y
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
# CONFIG_STAGING is not set
CONFIG_STAGING_EXCLUDE_BUILD=y
#
# Character devices
#
CONFIG_AMIGA_BUILTIN_SERIAL=y
CONFIG_MULTIFACE_III_TTY=m
# CONFIG_SERIAL_CONSOLE is not set
CONFIG_SERIAL_CONSOLE=y
#
# File systems
@ -883,6 +910,7 @@ CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
# CONFIG_EXT3_FS_XATTR is not set
# CONFIG_EXT4_FS is not set
CONFIG_JBD=y
@ -909,13 +937,15 @@ CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
# CONFIG_OCFS2_FS_STATS is not set
# CONFIG_OCFS2_DEBUG_MASKLOG is not set
# CONFIG_OCFS2_DEBUG_FS is not set
# CONFIG_OCFS2_COMPAT_JBD is not set
# CONFIG_OCFS2_FS_POSIX_ACL is not set
# CONFIG_BTRFS_FS is not set
CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_PRINT_QUOTA_WARNING is not set
CONFIG_QUOTA_TREE=m
# CONFIG_QFMT_V1 is not set
# CONFIG_QFMT_V2 is not set
CONFIG_QUOTACTL=y
@ -923,6 +953,11 @@ CONFIG_AUTOFS_FS=m
CONFIG_AUTOFS4_FS=m
CONFIG_FUSE_FS=m
#
# Caches
#
# CONFIG_FSCACHE is not set
#
# CD-ROM/DVD Filesystems
#
@ -935,8 +970,8 @@ CONFIG_UDF_NLS=y
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=m
CONFIG_MSDOS_FS=m
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
@ -954,10 +989,7 @@ CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_CONFIGFS_FS=m
#
# Miscellaneous filesystems
#
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ADFS_FS is not set
CONFIG_AFFS_FS=m
CONFIG_HFS_FS=m
@ -966,6 +998,9 @@ CONFIG_HFSPLUS_FS=m
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_CRAMFS=m
CONFIG_SQUASHFS=m
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
CONFIG_MINIX_FS=y
# CONFIG_OMFS_FS is not set
@ -976,23 +1011,24 @@ CONFIG_SYSV_FS=m
CONFIG_UFS_FS=m
# CONFIG_UFS_FS_WRITE is not set
# CONFIG_UFS_DEBUG is not set
# CONFIG_NILFS2_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
CONFIG_NFS_V4=y
# CONFIG_ROOT_NFS is not set
CONFIG_NFSD=m
CONFIG_NFSD_V3=y
# CONFIG_NFSD_V3_ACL is not set
# CONFIG_NFSD_V4 is not set
CONFIG_LOCKD=m
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_EXPORTFS=m
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
# CONFIG_SUNRPC_REGISTER_V4 is not set
CONFIG_RPCSEC_GSS_KRB5=m
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
CONFIG_SMB_NLS_DEFAULT=y
@ -1067,11 +1103,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
#
# Tracers
#
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
# CONFIG_SAMPLES is not set
#
@ -1092,13 +1123,21 @@ CONFIG_CRYPTO=y
#
# CONFIG_CRYPTO_FIPS is not set
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=m
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=m
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_PCOMP=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_GF128MUL=m
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
CONFIG_CRYPTO_TEST=m
@ -1113,7 +1152,7 @@ CONFIG_CRYPTO_SEQIV=m
#
# Block modes
#
CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=m
CONFIG_CRYPTO_CTS=m
CONFIG_CRYPTO_ECB=m
@ -1132,7 +1171,7 @@ CONFIG_CRYPTO_XCBC=m
#
CONFIG_CRYPTO_CRC32C=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_RMD128=m
CONFIG_CRYPTO_RMD160=m
@ -1154,7 +1193,7 @@ CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=m
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SALSA20=m
@ -1168,6 +1207,7 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m
# Compression
#
CONFIG_CRYPTO_DEFLATE=m
CONFIG_CRYPTO_ZLIB=m
CONFIG_CRYPTO_LZO=m
#
@ -1175,11 +1215,13 @@ CONFIG_CRYPTO_LZO=m
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
# CONFIG_BINARY_PRINTF is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_CRC_CCITT=m
CONFIG_CRC16=m
CONFIG_CRC_T10DIF=y
@ -1191,10 +1233,13 @@ CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=m
CONFIG_LZO_COMPRESS=m
CONFIG_LZO_DECOMPRESS=m
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_DMA=y
CONFIG_NLATTR=y

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