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gma500: Fix n, m1 and m2 clock limits for sdvo and lvds

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The values of n, m1 and m2 needs to be subtracted by 2 before writing them to
the FP register. The dot clock calculation already thinks of these values in
register form so we must also specify them as such.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Patrik Jakobsson 2013-02-16 13:04:21 +01:00 committed by Dave Airlie
parent ca18e1426b
commit 907a773ba3
1 changed files with 6 additions and 6 deletions
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12
drivers/gpu/drm/gma500/psb_intel_display.c
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@ -85,14 +85,14 @@ struct psb_intel_limit_t {
#define I9XX_DOT_MAX 400000 #define I9XX_DOT_MAX 400000
#define I9XX_VCO_MIN 1400000 #define I9XX_VCO_MIN 1400000
#define I9XX_VCO_MAX 2800000 #define I9XX_VCO_MAX 2800000
#define I9XX_N_MIN 3 #define I9XX_N_MIN 1
#define I9XX_N_MAX 8 #define I9XX_N_MAX 6
#define I9XX_M_MIN 70 #define I9XX_M_MIN 70
#define I9XX_M_MAX 120 #define I9XX_M_MAX 120
#define I9XX_M1_MIN 10 #define I9XX_M1_MIN 8
#define I9XX_M1_MAX 20 #define I9XX_M1_MAX 18
#define I9XX_M2_MIN 5 #define I9XX_M2_MIN 3
#define I9XX_M2_MAX 9 #define I9XX_M2_MAX 7
#define I9XX_P_SDVO_DAC_MIN 5 #define I9XX_P_SDVO_DAC_MIN 5
#define I9XX_P_SDVO_DAC_MAX 80 #define I9XX_P_SDVO_DAC_MAX 80
#define I9XX_P_LVDS_MIN 7 #define I9XX_P_LVDS_MIN 7