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ARM: clps711x: autcpu12: Special driver for handling NAND memory is removed
This patch provide migration to using "gpio-nand" and "basic-mmio-gpio" drivers instead of using special driver for handling NAND memory. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Alexander Shiyan
Olof Johansson
parent
49e67de364
commit
90383e0ac2
@ -23,9 +23,13 @@
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand-gpio.h>
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#include <linux/platform_device.h>
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#include <linux/basic_mmio_gpio.h>
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#include <mach/hardware.h>
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#include <asm/sizes.h>
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@ -43,6 +47,15 @@
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#define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300)
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#define AUTCPU12_CS8900_IRQ (IRQ_EINT3)
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#define AUTCPU12_SMC_BASE (CS1_PHYS_BASE + 0x06000000)
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#define AUTCPU12_SMC_SEL_BASE (AUTCPU12_SMC_BASE + 0x10)
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#define AUTCPU12_MMGPIO_BASE (CLPS711X_NR_GPIO)
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#define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
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#define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2)
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#define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3)
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#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 3)
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static struct resource autcpu12_cs8900_resource[] __initdata = {
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DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
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DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
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@ -59,14 +72,98 @@ static struct platform_device autcpu12_nvram_pdev __initdata = {
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.num_resources = ARRAY_SIZE(autcpu12_nvram_resource),
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};
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static struct resource autcpu12_nand_resource[] __initdata = {
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DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
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};
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static struct mtd_partition autcpu12_nand_parts[] __initdata = {
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{
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.name = "Flash partition 1",
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.offset = 0,
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.size = SZ_8M,
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},
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{
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.name = "Flash partition 2",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static void __init autcpu12_adjust_parts(struct gpio_nand_platdata *pdata,
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size_t sz)
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{
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switch (sz) {
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case SZ_16M:
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case SZ_32M:
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break;
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case SZ_64M:
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case SZ_128M:
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pdata->parts[0].size = SZ_16M;
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break;
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default:
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pr_warn("Unsupported SmartMedia device size %u\n", sz);
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break;
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}
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}
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static struct gpio_nand_platdata autcpu12_nand_pdata __initdata = {
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.gpio_rdy = AUTCPU12_SMC_RDY,
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.gpio_nce = AUTCPU12_SMC_NCE,
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.gpio_ale = AUTCPU12_SMC_ALE,
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.gpio_cle = AUTCPU12_SMC_CLE,
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.gpio_nwp = -1,
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.chip_delay = 20,
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.parts = autcpu12_nand_parts,
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.num_parts = ARRAY_SIZE(autcpu12_nand_parts),
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.adjust_parts = autcpu12_adjust_parts,
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};
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static struct platform_device autcpu12_nand_pdev __initdata = {
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.name = "gpio-nand",
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.id = -1,
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.resource = autcpu12_nand_resource,
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.num_resources = ARRAY_SIZE(autcpu12_nand_resource),
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.dev = {
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.platform_data = &autcpu12_nand_pdata,
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},
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};
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static struct resource autcpu12_mmgpio_resource[] __initdata = {
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DEFINE_RES_MEM_NAMED(AUTCPU12_SMC_SEL_BASE, SZ_1, "dat"),
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};
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static struct bgpio_pdata autcpu12_mmgpio_pdata __initdata = {
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.base = AUTCPU12_MMGPIO_BASE,
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.ngpio = 8,
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};
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static struct platform_device autcpu12_mmgpio_pdev __initdata = {
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.name = "basic-mmio-gpio",
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.id = -1,
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.resource = autcpu12_mmgpio_resource,
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.num_resources = ARRAY_SIZE(autcpu12_mmgpio_resource),
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.dev = {
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.platform_data = &autcpu12_mmgpio_pdata,
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},
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};
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static void __init autcpu12_init(void)
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{
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platform_device_register_simple("video-clps711x", 0, NULL, 0);
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platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
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ARRAY_SIZE(autcpu12_cs8900_resource));
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platform_device_register(&autcpu12_mmgpio_pdev);
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platform_device_register(&autcpu12_nvram_pdev);
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}
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static void __init autcpu12_init_late(void)
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{
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if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
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/* We are need both drivers to handle NAND */
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platform_device_register(&autcpu12_nand_pdev);
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}
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}
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MACHINE_START(AUTCPU12, "autronix autcpu12")
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/* Maintainer: Thomas Gleixner */
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.atag_offset = 0x20000,
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@ -75,6 +172,7 @@ MACHINE_START(AUTCPU12, "autronix autcpu12")
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.init_irq = clps711x_init_irq,
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.timer = &clps711x_timer,
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.init_machine = autcpu12_init,
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.init_late = autcpu12_init_late,
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.handle_irq = clps711x_handle_irq,
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.restart = clps711x_restart,
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MACHINE_END
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@ -40,8 +40,6 @@
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#define AUTCPU12_PHYS_CSAUX1 CS1_PHYS_BASE +0x04000000 /* physical */
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#define AUTCPU12_PHYS_SMC CS1_PHYS_BASE +0x06000000 /* physical */
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#define AUTCPU12_PHYS_CAN CS1_PHYS_BASE +0x08000000 /* physical */
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#define AUTCPU12_PHYS_TOUCH CS1_PHYS_BASE +0x0A000000 /* physical */
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@ -50,14 +48,6 @@
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#define AUTCPU12_PHYS_LPT CS1_PHYS_BASE +0x0E000000 /* physical */
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/*
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* defines for smartmedia card access
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*/
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#define AUTCPU12_SMC_RDY (1<<2)
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#define AUTCPU12_SMC_ALE (1<<3)
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#define AUTCPU12_SMC_CLE (1<<4)
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#define AUTCPU12_SMC_PORT_OFFSET PBDR
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#define AUTCPU12_SMC_SELECT_OFFSET 0x10
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/*
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* defines for lcd contrast
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*/
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@ -49,13 +49,6 @@ config MTD_NAND_MUSEUM_IDS
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NAND chips (page size 256 byte, erase size 4-8KiB). The IDs
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of these chips were reused by later, larger chips.
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config MTD_NAND_AUTCPU12
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tristate "SmartMediaCard on autronix autcpu12 board"
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depends on ARCH_AUTCPU12
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help
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This enables the driver for the autronix autcpu12 board to
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access the SmartMediaCard.
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config MTD_NAND_DENALI
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depends on PCI
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tristate "Support Denali NAND controller on Intel Moorestown"
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@ -11,7 +11,6 @@ obj-$(CONFIG_MTD_SM_COMMON) += sm_common.o
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obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o
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obj-$(CONFIG_MTD_NAND_SPIA) += spia.o
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obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o
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obj-$(CONFIG_MTD_NAND_AUTCPU12) += autcpu12.o
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obj-$(CONFIG_MTD_NAND_DENALI) += denali.o
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obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
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obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o
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@ -1,237 +0,0 @@
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/*
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* drivers/mtd/autcpu12.c
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*
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* Copyright (c) 2002 Thomas Gleixner <tgxl@linutronix.de>
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*
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* Derived from drivers/mtd/spia.c
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* Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Overview:
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* This is a device driver for the NAND flash device found on the
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* autronix autcpu12 board, which is a SmartMediaCard. It supports
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* 16MiB, 32MiB and 64MiB cards.
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*
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*
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* 02-12-2002 TG Cleanup of module params
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*
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* 02-20-2002 TG adjusted for different rd/wr address support
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* added support for read device ready/busy line
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* added page_cache
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*
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* 10-06-2002 TG 128K card support added
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <asm/io.h>
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#include <mach/hardware.h>
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#include <asm/sizes.h>
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#include <mach/autcpu12.h>
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/*
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* MTD structure for AUTCPU12 board
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*/
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static struct mtd_info *autcpu12_mtd = NULL;
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static void __iomem *autcpu12_fio_base;
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/*
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* Define partitions for flash devices
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*/
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static struct mtd_partition partition_info16k[] = {
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{ .name = "AUTCPU12 flash partition 1",
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.offset = 0,
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.size = 8 * SZ_1M },
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{ .name = "AUTCPU12 flash partition 2",
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.offset = 8 * SZ_1M,
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.size = 8 * SZ_1M },
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};
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static struct mtd_partition partition_info32k[] = {
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{ .name = "AUTCPU12 flash partition 1",
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.offset = 0,
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.size = 8 * SZ_1M },
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{ .name = "AUTCPU12 flash partition 2",
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.offset = 8 * SZ_1M,
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.size = 24 * SZ_1M },
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};
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static struct mtd_partition partition_info64k[] = {
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{ .name = "AUTCPU12 flash partition 1",
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.offset = 0,
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.size = 16 * SZ_1M },
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{ .name = "AUTCPU12 flash partition 2",
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.offset = 16 * SZ_1M,
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.size = 48 * SZ_1M },
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};
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static struct mtd_partition partition_info128k[] = {
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{ .name = "AUTCPU12 flash partition 1",
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.offset = 0,
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.size = 16 * SZ_1M },
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{ .name = "AUTCPU12 flash partition 2",
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.offset = 16 * SZ_1M,
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.size = 112 * SZ_1M },
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};
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#define NUM_PARTITIONS16K 2
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#define NUM_PARTITIONS32K 2
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#define NUM_PARTITIONS64K 2
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#define NUM_PARTITIONS128K 2
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/*
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* hardware specific access to control-lines
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*
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* ALE bit 4 autcpu12_pedr
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* CLE bit 5 autcpu12_pedr
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* NCE bit 0 fio_ctrl
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*
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*/
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static void autcpu12_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *chip = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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void __iomem *addr;
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unsigned char bits;
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bits = clps_readb(AUTCPU12_SMC_PORT_OFFSET) & ~0x30;
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bits |= (ctrl & NAND_CLE) << 4;
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bits |= (ctrl & NAND_ALE) << 2;
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clps_writeb(bits, AUTCPU12_SMC_PORT_OFFSET);
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addr = autcpu12_fio_base + AUTCPU12_SMC_SELECT_OFFSET;
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writeb((readb(addr) & ~0x1) | (ctrl & NAND_NCE), addr);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, chip->IO_ADDR_W);
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}
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/*
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* read device ready pin
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*/
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int autcpu12_device_ready(struct mtd_info *mtd)
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{
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return clps_readb(AUTCPU12_SMC_PORT_OFFSET) & AUTCPU12_SMC_RDY;
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}
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/*
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* Main initialization routine
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*/
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static int __init autcpu12_init(void)
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{
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struct nand_chip *this;
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int err = 0;
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/* Allocate memory for MTD device structure and private data */
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autcpu12_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
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GFP_KERNEL);
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if (!autcpu12_mtd) {
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printk("Unable to allocate AUTCPU12 NAND MTD device structure.\n");
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err = -ENOMEM;
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goto out;
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}
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/* map physical address */
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autcpu12_fio_base = ioremap(AUTCPU12_PHYS_SMC, SZ_1K);
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if (!autcpu12_fio_base) {
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printk("Ioremap autcpu12 SmartMedia Card failed\n");
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err = -EIO;
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goto out_mtd;
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}
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/* Get pointer to private data */
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this = (struct nand_chip *)(&autcpu12_mtd[1]);
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/* Initialize structures */
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memset(autcpu12_mtd, 0, sizeof(struct mtd_info));
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memset(this, 0, sizeof(struct nand_chip));
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/* Link the private data with the MTD structure */
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autcpu12_mtd->priv = this;
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autcpu12_mtd->owner = THIS_MODULE;
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/* Set address of NAND IO lines */
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this->IO_ADDR_R = autcpu12_fio_base;
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this->IO_ADDR_W = autcpu12_fio_base;
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this->cmd_ctrl = autcpu12_hwcontrol;
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this->dev_ready = autcpu12_device_ready;
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/* 20 us command delay time */
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this->chip_delay = 20;
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this->ecc.mode = NAND_ECC_SOFT;
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/* Enable the following for a flash based bad block table */
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/*
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this->bbt_options = NAND_BBT_USE_FLASH;
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*/
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this->bbt_options = NAND_BBT_USE_FLASH;
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/* Scan to find existence of the device */
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if (nand_scan(autcpu12_mtd, 1)) {
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err = -ENXIO;
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goto out_ior;
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}
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/* Register the partitions */
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switch (autcpu12_mtd->size) {
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case SZ_16M:
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mtd_device_register(autcpu12_mtd, partition_info16k,
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NUM_PARTITIONS16K);
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break;
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case SZ_32M:
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mtd_device_register(autcpu12_mtd, partition_info32k,
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NUM_PARTITIONS32K);
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break;
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case SZ_64M:
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mtd_device_register(autcpu12_mtd, partition_info64k,
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NUM_PARTITIONS64K);
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break;
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case SZ_128M:
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mtd_device_register(autcpu12_mtd, partition_info128k,
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NUM_PARTITIONS128K);
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break;
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default:
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printk("Unsupported SmartMedia device\n");
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err = -ENXIO;
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goto out_ior;
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}
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goto out;
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out_ior:
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iounmap(autcpu12_fio_base);
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out_mtd:
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kfree(autcpu12_mtd);
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out:
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return err;
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}
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module_init(autcpu12_init);
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/*
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* Clean up routine
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*/
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static void __exit autcpu12_cleanup(void)
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{
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/* Release resources, unregister device */
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nand_release(autcpu12_mtd);
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/* unmap physical address */
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iounmap(autcpu12_fio_base);
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/* Free the MTD device structure */
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kfree(autcpu12_mtd);
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}
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module_exit(autcpu12_cleanup);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
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MODULE_DESCRIPTION("Glue layer for SmartMediaCard on autronix autcpu12");
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