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ARM: mmp: add pm support for pxa910
add suspend/resume functionality for pxa910 Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Raul Xiong <xjian@marvell.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
This commit is contained in:
Chao Xie
Haojian Zhuang
parent
f4466946c1
commit
902ca22971
@ -10,6 +10,7 @@ obj-$(CONFIG_CPU_PXA910) += pxa910.o
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obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o
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ifeq ($(CONFIG_PM),y)
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obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
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obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o
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endif
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77
arch/arm/mach-mmp/include/mach/pm-pxa910.h
Normal file
77
arch/arm/mach-mmp/include/mach/pm-pxa910.h
Normal file
@ -0,0 +1,77 @@
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/*
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* PXA910 Power Management Routines
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*
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* This software program is licensed subject to the GNU General Public License
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* (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
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*
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* (C) Copyright 2009 Marvell International Ltd.
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* All Rights Reserved
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*/
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#ifndef __PXA910_PM_H__
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#define __PXA910_PM_H__
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#define APMU_MOH_IDLE_CFG APMU_REG(0x0018)
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#define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1)
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#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5)
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#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6)
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#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16)
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#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18)
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#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21)
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#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20)
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#define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c)
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#define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
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#define MPMU_FCCR MPMU_REG(0x0008)
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#define MPMU_APCR MPMU_REG(0x1000)
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#define MPMU_APCR_AXISD (1 << 31)
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#define MPMU_APCR_DSPSD (1 << 30)
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#define MPMU_APCR_SLPEN (1 << 29)
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#define MPMU_APCR_DTCMSD (1 << 28)
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#define MPMU_APCR_DDRCORSD (1 << 27)
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#define MPMU_APCR_APBSD (1 << 26)
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#define MPMU_APCR_BBSD (1 << 25)
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#define MPMU_APCR_SLPWP0 (1 << 23)
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#define MPMU_APCR_SLPWP1 (1 << 22)
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#define MPMU_APCR_SLPWP2 (1 << 21)
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#define MPMU_APCR_SLPWP3 (1 << 20)
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#define MPMU_APCR_VCTCXOSD (1 << 19)
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#define MPMU_APCR_SLPWP4 (1 << 18)
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#define MPMU_APCR_SLPWP5 (1 << 17)
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#define MPMU_APCR_SLPWP6 (1 << 16)
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#define MPMU_APCR_SLPWP7 (1 << 15)
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#define MPMU_APCR_MSASLPEN (1 << 14)
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#define MPMU_APCR_STBYEN (1 << 13)
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#define MPMU_AWUCRM MPMU_REG(0x104c)
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#define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25)
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#define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24)
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#define MPMU_AWUCRM_SDH1 (1 << 23)
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#define MPMU_AWUCRM_SDH2 (1 << 22)
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#define MPMU_AWUCRM_KEYPRESS (1 << 21)
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#define MPMU_AWUCRM_TRACKBALL (1 << 20)
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#define MPMU_AWUCRM_NEWROTARY (1 << 19)
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#define MPMU_AWUCRM_RTC_ALARM (1 << 17)
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#define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13)
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#define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12)
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#define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11)
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#define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10)
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#define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9)
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#define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8)
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#define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7))
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enum {
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POWER_MODE_ACTIVE = 0,
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POWER_MODE_CORE_INTIDLE,
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POWER_MODE_CORE_EXTIDLE,
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POWER_MODE_APPS_IDLE,
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POWER_MODE_APPS_SLEEP,
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POWER_MODE_SYS_SLEEP,
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POWER_MODE_HIBERNATE,
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POWER_MODE_UDR,
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};
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extern int pxa910_set_wake(struct irq_data *data, unsigned int on);
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#endif
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@ -26,6 +26,9 @@
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#ifdef CONFIG_CPU_MMP2
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#include <mach/pm-mmp2.h>
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#endif
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#ifdef CONFIG_CPU_PXA910
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#include <mach/pm-pxa910.h>
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#endif
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#include "common.h"
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@ -213,6 +216,9 @@ void __init icu_init_irq(void)
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set_irq_flags(irq, IRQF_VALID);
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}
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irq_set_default_host(icu_data[0].domain);
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#ifdef CONFIG_CPU_PXA910
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icu_irq_chip.irq_set_wake = pxa910_set_wake;
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#endif
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}
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/* MMP2 (ARMv7) */
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285
arch/arm/mach-mmp/pm-pxa910.c
Normal file
285
arch/arm/mach-mmp/pm-pxa910.c
Normal file
@ -0,0 +1,285 @@
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/*
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* PXA910 Power Management Routines
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*
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* This software program is licensed subject to the GNU General Public License
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* (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
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*
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* (C) Copyright 2009 Marvell International Ltd.
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* All Rights Reserved
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/time.h>
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#include <linux/delay.h>
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#include <linux/suspend.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <asm/mach-types.h>
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#include <mach/hardware.h>
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#include <mach/cputype.h>
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#include <mach/addr-map.h>
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#include <mach/pm-pxa910.h>
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#include <mach/regs-icu.h>
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#include <mach/irqs.h>
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int pxa910_set_wake(struct irq_data *data, unsigned int on)
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{
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int irq = data->irq;
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struct irq_desc *desc = irq_to_desc(data->irq);
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uint32_t awucrm = 0, apcr = 0;
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if (unlikely(irq >= nr_irqs)) {
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pr_err("IRQ nubmers are out of boundary!\n");
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return -EINVAL;
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}
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if (on) {
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if (desc->action)
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desc->action->flags |= IRQF_NO_SUSPEND;
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} else {
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if (desc->action)
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desc->action->flags &= ~IRQF_NO_SUSPEND;
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}
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/* setting wakeup sources */
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switch (irq) {
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/* wakeup line 2 */
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case IRQ_PXA910_AP_GPIO:
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awucrm = MPMU_AWUCRM_WAKEUP(2);
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apcr |= MPMU_APCR_SLPWP2;
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break;
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/* wakeup line 3 */
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case IRQ_PXA910_KEYPAD:
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awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_KEYPRESS;
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apcr |= MPMU_APCR_SLPWP3;
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break;
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case IRQ_PXA910_ROTARY:
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awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_NEWROTARY;
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apcr |= MPMU_APCR_SLPWP3;
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break;
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case IRQ_PXA910_TRACKBALL:
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awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_TRACKBALL;
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apcr |= MPMU_APCR_SLPWP3;
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break;
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/* wakeup line 4 */
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case IRQ_PXA910_AP1_TIMER1:
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awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_1;
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apcr |= MPMU_APCR_SLPWP4;
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break;
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case IRQ_PXA910_AP1_TIMER2:
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awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_2;
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apcr |= MPMU_APCR_SLPWP4;
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break;
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case IRQ_PXA910_AP1_TIMER3:
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awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_3;
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apcr |= MPMU_APCR_SLPWP4;
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break;
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case IRQ_PXA910_AP2_TIMER1:
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awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_1;
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apcr |= MPMU_APCR_SLPWP4;
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break;
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case IRQ_PXA910_AP2_TIMER2:
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awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_2;
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apcr |= MPMU_APCR_SLPWP4;
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break;
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case IRQ_PXA910_AP2_TIMER3:
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awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_3;
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apcr |= MPMU_APCR_SLPWP4;
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break;
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case IRQ_PXA910_RTC_ALARM:
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awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_RTC_ALARM;
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apcr |= MPMU_APCR_SLPWP4;
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break;
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/* wakeup line 5 */
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case IRQ_PXA910_USB1:
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case IRQ_PXA910_USB2:
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awucrm = MPMU_AWUCRM_WAKEUP(5);
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apcr |= MPMU_APCR_SLPWP5;
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break;
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/* wakeup line 6 */
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case IRQ_PXA910_MMC:
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awucrm = MPMU_AWUCRM_WAKEUP(6)
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| MPMU_AWUCRM_SDH1
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| MPMU_AWUCRM_SDH2;
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apcr |= MPMU_APCR_SLPWP6;
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break;
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/* wakeup line 7 */
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case IRQ_PXA910_PMIC_INT:
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awucrm = MPMU_AWUCRM_WAKEUP(7);
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apcr |= MPMU_APCR_SLPWP7;
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break;
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default:
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if (irq >= IRQ_GPIO_START && irq < IRQ_BOARD_START) {
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awucrm = MPMU_AWUCRM_WAKEUP(2);
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apcr |= MPMU_APCR_SLPWP2;
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} else
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printk(KERN_ERR "Error: no defined wake up source irq: %d\n",
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irq);
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}
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if (on) {
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if (awucrm) {
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awucrm |= __raw_readl(MPMU_AWUCRM);
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__raw_writel(awucrm, MPMU_AWUCRM);
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}
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if (apcr) {
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apcr = ~apcr & __raw_readl(MPMU_APCR);
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__raw_writel(apcr, MPMU_APCR);
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}
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} else {
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if (awucrm) {
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awucrm = ~awucrm & __raw_readl(MPMU_AWUCRM);
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__raw_writel(awucrm, MPMU_AWUCRM);
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}
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if (apcr) {
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apcr |= __raw_readl(MPMU_APCR);
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__raw_writel(apcr, MPMU_APCR);
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}
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}
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return 0;
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}
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void pxa910_pm_enter_lowpower_mode(int state)
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{
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uint32_t idle_cfg, apcr;
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idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG);
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apcr = __raw_readl(MPMU_APCR);
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apcr &= ~(MPMU_APCR_DDRCORSD | MPMU_APCR_APBSD | MPMU_APCR_AXISD
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| MPMU_APCR_VCTCXOSD | MPMU_APCR_STBYEN);
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idle_cfg &= ~(APMU_MOH_IDLE_CFG_MOH_IDLE
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| APMU_MOH_IDLE_CFG_MOH_PWRDWN);
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switch (state) {
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case POWER_MODE_UDR:
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/* only shutdown APB in UDR */
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apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD;
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/* fall through */
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case POWER_MODE_SYS_SLEEP:
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apcr |= MPMU_APCR_SLPEN; /* set the SLPEN bit */
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apcr |= MPMU_APCR_VCTCXOSD; /* set VCTCXOSD */
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/* fall through */
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case POWER_MODE_APPS_SLEEP:
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apcr |= MPMU_APCR_DDRCORSD; /* set DDRCORSD */
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/* fall through */
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case POWER_MODE_APPS_IDLE:
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apcr |= MPMU_APCR_AXISD; /* set AXISDD bit */
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/* fall through */
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case POWER_MODE_CORE_EXTIDLE:
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idle_cfg |= APMU_MOH_IDLE_CFG_MOH_IDLE;
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idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN;
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idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWR_SW(3)
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| APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(3);
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/* fall through */
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case POWER_MODE_CORE_INTIDLE:
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break;
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}
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/* program the memory controller hardware sleep type and auto wakeup */
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idle_cfg |= APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ;
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idle_cfg |= APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN;
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__raw_writel(0x0, APMU_MC_HW_SLP_TYPE); /* auto refresh */
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/* set DSPSD, DTCMSD, BBSD, MSASLPEN */
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apcr |= MPMU_APCR_DSPSD | MPMU_APCR_DTCMSD | MPMU_APCR_BBSD
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| MPMU_APCR_MSASLPEN;
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/*always set SLEPEN bit mainly for MSA*/
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apcr |= MPMU_APCR_SLPEN;
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/* finally write the registers back */
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__raw_writel(idle_cfg, APMU_MOH_IDLE_CFG);
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__raw_writel(apcr, MPMU_APCR);
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}
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static int pxa910_pm_enter(suspend_state_t state)
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{
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unsigned int idle_cfg, reg = 0;
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/*pmic thread not completed,exit;otherwise system can't be waked up*/
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reg = __raw_readl(ICU_INT_CONF(IRQ_PXA910_PMIC_INT));
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if ((reg & 0x3) == 0)
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return -EAGAIN;
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idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG);
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idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN
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| APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN;
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__raw_writel(idle_cfg, APMU_MOH_IDLE_CFG);
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/* disable L2 */
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outer_disable();
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/* wait for l2 idle */
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while (!(readl(CIU_REG(0x8)) & (1 << 16)))
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udelay(1);
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cpu_do_idle();
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/* enable L2 */
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outer_resume();
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/* wait for l2 idle */
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while (!(readl(CIU_REG(0x8)) & (1 << 16)))
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udelay(1);
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idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG);
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idle_cfg &= ~(APMU_MOH_IDLE_CFG_MOH_PWRDWN
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| APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN);
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__raw_writel(idle_cfg, APMU_MOH_IDLE_CFG);
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return 0;
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}
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/*
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* Called after processes are frozen, but before we shut down devices.
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*/
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static int pxa910_pm_prepare(void)
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{
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pxa910_pm_enter_lowpower_mode(POWER_MODE_UDR);
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return 0;
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}
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/*
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* Called after devices are re-setup, but before processes are thawed.
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*/
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static void pxa910_pm_finish(void)
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{
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pxa910_pm_enter_lowpower_mode(POWER_MODE_CORE_INTIDLE);
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}
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static int pxa910_pm_valid(suspend_state_t state)
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{
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return ((state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM));
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}
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static const struct platform_suspend_ops pxa910_pm_ops = {
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.valid = pxa910_pm_valid,
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.prepare = pxa910_pm_prepare,
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.enter = pxa910_pm_enter,
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.finish = pxa910_pm_finish,
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};
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static int __init pxa910_pm_init(void)
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{
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uint32_t awucrm = 0;
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if (!cpu_is_pxa910())
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return -EIO;
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suspend_set_ops(&pxa910_pm_ops);
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/* Set the following bits for MMP3 playback with VCTXO on */
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__raw_writel(__raw_readl(APMU_SQU_CLK_GATE_CTRL) | (1 << 30),
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APMU_SQU_CLK_GATE_CTRL);
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__raw_writel(__raw_readl(MPMU_FCCR) | (1 << 28), MPMU_FCCR);
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|
||||
awucrm |= MPMU_AWUCRM_AP_ASYNC_INT | MPMU_AWUCRM_AP_FULL_IDLE;
|
||||
__raw_writel(awucrm, MPMU_AWUCRM);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
late_initcall(pxa910_pm_init);
|
||||
Loading…
Reference in New Issue
Block a user